Change the IRQ interface to allow adding events.
Move code to send the lightbar sequence from gesture.c to motion task.
TEST=compile, works on Ryu.
BRANCH=smaug
BUG=chrome-os-partner:44754
Change-Id: I981ea123ebef0e8e3d6aa320eade89f10e83b6fc
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/296822
Reviewed-by: Alec Berg <alecaberg@chromium.org>
In motion_sense_init, gather the result of the sensor init routine.
BUG=none
BRANCH=smaug
TEST=Get the result of init() when calling accelinit.
Change-Id: I8d0219a2b81fdf6d512976db5a28646ee5f6b994
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/299946
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
When this script is searching through CONFIG_* options used in the repo,
it should ignore hidden files. I uncovered this by accidentally having
modified a file and the presubmit hook failed. This is because emacs
auto-saves files with the format ".#filename.ext". Now, the script will
ignore hidden files.
BUG=None
BRANCH=None
TEST=Use emacs to modify a c file but not save it. Run the script and
verify that no errors occur.
TEST=make -j buildall tests
Change-Id: Ie09cfcf66f2e416aeed99847945cb5168b457d1a
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/300954
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
This commit makes all prints with the TERR error level print to standard
error so that it's more obvious what's wrong when an error occurs.
BUG=None
BRANCH=None
TEST=Checkout tree @ 5dfe8d2. Build npcx_evb and see that the error is
displayed during the build process.
TEST=make buildall tests
Change-Id: I4117dd83a9a85ae81baf533302b0b70f4da174bc
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/300613
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
since we add debounce time (50 ms) for SUSPEND & POWER GOOD signal
after oak rev3 (commit e58a913b). It will causes the chipset_reset
function failure, because PMIC_COLD_RESET_L_HOLD_TIME is short.
PMIC_COLD_RESET_L_HOLD_TIME should be greater than 100 ms
[SUSPEND_DEBOUNCE_TIME (50 ms) + POWER_DEBOUNCE_TIME (50 ms)].
So, revise PMIC_COLD_RESET_L_HOLD_TIME to 120ms.
And, using hook to avoid blocking the EC console when executing
"apreset" EC console command.
BRANCH=none
BUG=chrome-os-partner:44955
TEST=manual
Run EC console command, after AP enter S0:
> apreset
AP should be reset normally.
Change-Id: I04e31aef8be3092ad39b5f1b1c2b75b78b4d1d7b
Signed-off-by: Ben Lok <ben.lok@mediatek.com>
Reviewed-on: https://chromium-review.googlesource.com/299625
Reviewed-by: Rong Chang <rongchang@chromium.org>
Since the firmware_ECPowerButton testcase holds down power button
about 10s to shut down without powerd, we set DELAY_FORCE_SHUTDOWN
about 8s to make sure the powerbutton is pressed long enough to
force shutdown.
BRANCH=none
BUG=chrome-os-partner:43412
TEST=manual
run "firmware_ECPowerButton" testcase on rev3.
Change-Id: Ib41cdecfa0342236d618e6fdffcb64bf7f51b557
Signed-off-by: YH Huang <yh.huang@mediatek.com>
Reviewed-on: https://chromium-review.googlesource.com/296884
Reviewed-by: Rong Chang <rongchang@chromium.org>
1. Host access to the PNPCFG registers is disabled.
2. UART2 for host if necessary.
Signed-off-by: Dino Li <dino.li@ite.com.tw>
BRANCH=none
BUG=none
TEST=1. host can't access the PNPCFG registers.
2. out I/O port 0x2f8 '0x30, 0x31, 0x32, 0x33, and 0x34'
will have console message '01234'.
Change-Id: If07bdc129105f5248661d929e6858d4063c452ee
Reviewed-on: https://chromium-review.googlesource.com/300266
Commit-Ready: Dino Li <dino.li@ite.com.tw>
Tested-by: Dino Li <dino.li@ite.com.tw>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
This commit adds the lid accelerometer to the list of motion sensors on
the board. It currently wrapped behind an ifdef for
HAS_TASK_MOTIONSENSE due to space contraints.
BUG=chrome-os-partner:43494
BRANCH=None
TEST=Build GLaDOS EC with driver enabled and verify that valid
accelerometer data is read, and that range, resolution, and odr can all
be modified.
TEST=Verified that signs of accelerometer data conform to those shown in
the doc.
TEST=make buildall tests
CQ-DEPEND=CL:299013
CQ-DEPEND=CL:300510
Change-Id: Ib566f8eb2818c0694bf673af244aedbc91eac80f
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/299504
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Set bq24773 charger switching frequency to 600kHz for
efficiency.
BUG=none
BRANCH=none
TEST=removed #ifdef BOARD_LUCID and tested on samus. verified
that the option0 register was set correctly when charger
plugged in:
> i2cxfer r16 0 0xd4 0
0xe04e
Change-Id: I60d563d0040efc7ca7746985156c4e70b423f3a7
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/300622
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
The previous commits left npcx in a bad state. Change
CONFIG_PROGRAM_MEMORY_BASE to point to the actual start of code memory
and correct the linker file.
This still results in a non-working npcx image (more changes
forthcoming) but it does build.
BUG=chrome-os-partner:23796
TEST=make clean; make buildall -j
BRANCH=None
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: Ia300c5d18695dccd8d9fd9a6122cd7d30353adfa
Reviewed-on: https://chromium-review.googlesource.com/300295
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Add config option to use the old accelerometer reference frame,
which is used on samus and products using 3.14 or earlier kernel.
This fixes samus so that the lid angle calculation is correct
again.
This also moves the accel_orientation structure out of the board
directory and into common code, since it purely is a function of
the reference frame being used.
BUG=chrome-os-partner:43494
BRANCH=none
TEST=test on samus, verify lid angle calculation is correct once
again. also, enable the motion_lid test and verify that it passes.
Change-Id: I948a74a71964b54c68be66e828a030ddd0418947
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/300510
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Gwendal Grignou <gwendal@chromium.org>
Fix motion_sense task to make sure the task never exits. Note,
before this change a task_wake(TASK_ID_MOTIONSENSE) would end
the task because task_wait_event() would return 0.
BUG=none
BRANCH=smaug
TEST=with following CL, run motion_lid test and make sure it
passes
Change-Id: I67bd2e535d67215baa0cc1dfd0010b8199152dbd
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/300630
Commit-Ready: Gwendal Grignou <gwendal@chromium.org>
Tested-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-by: Gwendal Grignou <gwendal@chromium.org>
ectool is only sending payload. kernel is adding header for v3 commands.
(length, crc, ...)
Put back the header I previously deleted in cl:274086
BRANCH=ryu
BUG=chrome-os-partner:45304
TEST=ectool flashwrite now works.
Change-Id: I40fa30bc477a090261048eb51b382483f28d4ab1
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/300024
Reviewed-by: Shawn N <shawnn@chromium.org>
1. Fix fan turns on during sysjump if fan is disabled.
2. Remove unused board function.
Signed-off-by: Dino Li <dino.li@ite.com.tw>
BRANCH=none
BUG=none
TEST=1-1. Console 'sysjump RW' and fan keeps off.
1-2. Console 'fanset 4000' or 'fanset 0' and 'sysjump',
it dose maintain the fan RPM.
Change-Id: I531d49c2a8a9fea68af4507339c7be97367c504c
Reviewed-on: https://chromium-review.googlesource.com/299650
Commit-Ready: Dino Li <dino.li@ite.com.tw>
Tested-by: Dino Li <dino.li@ite.com.tw>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
1. add lpc_keyboard_clear_buffer() function.
2. Enable P80L function, that LPC I/O port 80h data can be mapped
to BRAM bank1 (offset 0x80 ~ 0xBF).
Signed-off-by: Dino Li <dino.li@ite.com.tw>
BRANCH=none
BUG=none
TEST=1. The lpc_keyboard_clear_buffer() function can clear OBF.
2. 80h port, console command port80.
3. 62h/66h port.
3-a. out 66h 80h, out 62h 00h, in 62h 02h
3-b. out 66h 81h, out 62h 01h, out 62h 55h
3-c. out 66h 80h, out 62h 01h, in 62h 55h
3-d. out 66h 80h, out 62h 02h, in 62h aah
4. Host command "version".
Change-Id: Id2b5a5813cbe8edfc4ecc7b153874b819d460f43
Reviewed-on: https://chromium-review.googlesource.com/298421
Commit-Ready: Dino Li <dino.li@ite.com.tw>
Tested-by: Dino Li <dino.li@ite.com.tw>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Update TCPCI to match specification version RC3.
BUG=none
BRANCH=none
TEST=tested on glados and samus by plugging in a zinger with
both polarities and verifying we make a power contract.
Change-Id: I9cd6d8db7b7149995847ec1b071fba1f4d4cd5a3
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/299713
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Instead of mocking i2c_read8/16/32, mock i2c_xfer.
We can now test code that call i2c_xfer directly and
test common/i2c.c
BRANCH=samus, ryu
BUG=chrome-os-partner:45223
TEST=Unit tests pass.
Change-Id: Iaa772515c40cf55d2050d0019e2062d63278adc0
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/299768
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Since there is no more concept of a flash region belonging only to the
EC, we only need one FLASH_SIZE config, which represents the actual
physical size of flash.
BRANCH=None
BUG=chrome-os-partner:23796
TEST=With entire patch series, on both Samus and Glados:
- Verify 'version' EC console command is correct
- Verify 'flashrom -p ec -r read.bin' reads back EC image
- Verify software sync correctly flashes both EC and PD RW images
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: I18a34a943e02c8a029f330f213a8634a2ca418b6
Reviewed-on: https://chromium-review.googlesource.com/297824
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
In order to support architectures with non-contiguous writable and
protected regions, change storage offsets to be relative to writable and
protected regions, rather than relative to "the start of the region of
storage belonging to the EC".
Spec doc available at https://goo.gl/fnzTvr.
BRANCH=None
BUG=chrome-os-partner:23796
TEST=With entire patch series, on both Samus and Glados:
- Verify 'version' EC console command is correct
- Verify 'flashrom -p ec -r read.bin' reads back EC image
- Verify software sync correctly flashes both EC and PD RW images
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: I796f8e7305a6336495bd256a78774595cb16a2e4
Reviewed-on: https://chromium-review.googlesource.com/297823
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
CDRAM / CODERAM configs were previously used for chips which copied code
from external SPI to program memory prior to execution, and were used
inconsistently between npcx and mec1322.
These CONFIGs are now completely redundant given new configs like
CONFIG_MAPPED_STORAGE_BASE and CONFIG_EXTERNAL_STORAGE.
BRANCH=None
BUG=chrome-os-partner:23796
TEST=With entire patch series, on both Samus and Glados:
- Verify 'version' EC console command is correct
- Verify 'flashrom -p ec -r read.bin' reads back EC image
- Verify software sync correctly flashes both EC and PD RW images
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: I0e054ab4c939f9dcf54abee8e5ebd9b2e42fe9c4
Reviewed-on: https://chromium-review.googlesource.com/297804
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
This commit fixes two issues:
- When we transition from S3 to S0, we enable the sensor rail. Very
shortly thereafter, we attempt to initialize the motion sensors.
They fail on the very first i2c transaction due to the fact that the
senors are not ready. Therefore, this commit adds a small 3ms delay
to the end of the board_chipset_resume() hook. This allows both the
motion sensors to initialize successfully when the motion sense hook
is called.
- In order for the delay to be effective, it must be called prior to
the motion sense hook. Therefore, the priority of
board_chipset_resume() is increased.
BUG=chrome-os-partner:43494
BRANCH=None
TEST=Build and flash GLaDOS EC, reboot several times verifying that both
sensors are initialized.
TEST=make buildall tests
Change-Id: I86ee87955f0750cac1960be147c2b39c7d922f0a
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/299769
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Kick the PD task when the dual role toggling is enabled to ensure we
start toggling immediatly and detect a UFP (USB device).
The issue was visible with the CONFIG_USB_PD_LOW_POWER change where the
task was waking up only every minute when the toggling was disabled,
the whole system would take up to a minute after resume to detect a peripheral
connected while in S3.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=smaug
BUG=chrome-os-partner:45347
TEST=On Smaug, put the system into S3, plug a USB device (e.g. a USB
key), transition to S0 and verify that the kernel is receiving
immediatly the "host mode" notification.
Change-Id: I12d10941f9d2cefdfe711847ba0aec9f269e9bcd
Reviewed-on: https://chromium-review.googlesource.com/299796
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
(cherry picked from commit 6a0e8ec3b9b1a7a0eb222a9e6c132d88d33f60e2)
Reviewed-on: https://chromium-review.googlesource.com/299807
Commit-Ready: Vincent Palatin <vpalatin@chromium.org>
This commit adds a new basic driver for the Kionix KX022 Accelerometer.
Currently, the driver is capable of reading the sensor data and
manipulating its ODR, resolution, and range.
This sensor also has integrated support for Directional
Tap/Double-Tap(TM), however that functionality is not yet implemented in
the driver.
Lastly, since this accelerometer is very similar to the previous KXCJ9,
this commit tries to combine the drivers.
Note, the variant of the Kionix accelerometer MUST be specified in the
private data structure.
BUG=chrome-os-partner:43494
BRANCH=None
TEST=Build GLaDOS EC with driver enabled and verify that valid
accelerometer data is read, and that range, resolution, and odr can all
be modified.
TEST=Build samus EC image and verify that the lid still
works. Additionally, verify that I can change the odr, rate, and
resolution.
TEST=make buildall tests
Change-Id: I238ff1dc13f5342a93f8f701a0da85c52f25d214
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/299013
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Gwendal Grignou <gwendal@chromium.org>
Given it is in the chip as the accelerometer, it is on all the time.
Put it in suspend by setting its ODR to 0 is S3 and S5.
BRANCH=smaug
BUG=none
TEST=gyro still works in S0 and after S3/S5 transitions.
Change-Id: Ibbf51eb555e2c513a6561a1d22e231796b3da4b4
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/299542
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Since the STM32 flash write protection was re-factored between STM32F0
and STM32F/F3, the common STM32 flash code checks whether the chip needs
a reboot to synchronize its write protection state (as this can be done
only with an OBL_LAUNCH triggered reset on STM32F0)
but for platforms able to set immediatly the full write-protection
(STM32F/STM32F3 with Cortex-M3 core using the bus fault interception
code) where there is no EC_FLASH_PROTECT_ALL_AT_BOOT flag, this might
trigger a reset loop in the RO code when the flash is write-protected.
Make the check conditional to the existence of EC_FLASH_PROTECT_ALL_AT_BOOT.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=smaug
BUG=chrome-os-partner:45288
TEST=On a smaug board with hardware write protect enable,
enable software write protect from the AP command line:
flashrom -p ec --wp-range 0 0x20000
flashrom -p ec --wp-enable
ectool reboot_ec RO
reboot -p
then, go to fastboot mode :
adb reboot-bootloader
and see the machine booting properly.
Change-Id: I93f78cb8e9e918c8efe374bd757b79bc87243e2c
Reviewed-on: https://chromium-review.googlesource.com/299555
Trybot-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
(cherry picked from commit 39a0feb45b0c14ea5eb008329f2b8ea7a9b17c8a)
Reviewed-on: https://chromium-review.googlesource.com/299762
Commit-Ready: Vincent Palatin <vpalatin@chromium.org>
This change picks CL:298067 into oak. Removes workaround for initial
board version. Also cleanup unnecessary TODO in usb_pd_policy.
BUG=none
BRANCH=none
TEST=tested on oak, plug low power charge to one port, then plug in
zinger. check charge port becomes the high power one.
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Signed-off-by: Rong Chang <rongchang@chromium.org>
Change-Id: I134be07d89fefad124eb6cceebf862a83e8bd3b4
Reviewed-on: https://chromium-review.googlesource.com/299150
Oak board relies on TCPCI power status. When board init, PD should
update it's VBUS status and TCPM needs to get power status after enable
TCPC power status mask.
BRANCH=none
BUG=chrome-os-partner:44952
TEST=manual
build and load on oak, disconnect battery.
power on system with zinger, and check PD state.
Signed-off-by: Rong Chang <rongchang@chromium.org>
Change-Id: Ic0d4b50d38ac39ff31b3a257c4b3b5dde0ebda4b
Reviewed-on: https://chromium-review.googlesource.com/297871
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Add all swap commands to USB_PD_CONTROL host command: data,
power, and vconn swap.
BUG=none
BRANCH=smaug
TEST=tested on both samus and ryu while connected to each other.
Change-Id: I280a0da2d3c5a5436243134ab3f2ec353ebf6ab8
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/299290
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Gesture recognition can be done in software (by the EC) or in
hardware, by the sensor itself.
Add variable to compile gesture.c only in the software case.
BRANCH=smaug
TEST=compile.
BUG=b:23570481
Change-Id: I22bef0bf744516df267020d9458e0299a4da3d72
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/296211
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Allow accelrate to suspend a sensor, even if the AP is using it.
For debugging only.
BRANCH=smaug
TEST=before accelrate 0 0 would not suspend the accelerometer in SO,
the AP is using it.
BUG=b:23570481
Change-Id: Iea4f616d0a0d1b4a0b0fa2bc942d05b2a2425926
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/296210
Reviewed-by: Alec Berg <alecaberg@chromium.org>
