Change the IRQ interface to allow adding events.
Move code to send the lightbar sequence from gesture.c to motion task.
TEST=compile, works on Ryu.
BRANCH=smaug
BUG=chrome-os-partner:44754
Change-Id: I981ea123ebef0e8e3d6aa320eade89f10e83b6fc
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/296822
Reviewed-by: Alec Berg <alecaberg@chromium.org>
1. Host access to the PNPCFG registers is disabled.
2. UART2 for host if necessary.
Signed-off-by: Dino Li <dino.li@ite.com.tw>
BRANCH=none
BUG=none
TEST=1. host can't access the PNPCFG registers.
2. out I/O port 0x2f8 '0x30, 0x31, 0x32, 0x33, and 0x34'
will have console message '01234'.
Change-Id: If07bdc129105f5248661d929e6858d4063c452ee
Reviewed-on: https://chromium-review.googlesource.com/300266
Commit-Ready: Dino Li <dino.li@ite.com.tw>
Tested-by: Dino Li <dino.li@ite.com.tw>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Add config option to use the old accelerometer reference frame,
which is used on samus and products using 3.14 or earlier kernel.
This fixes samus so that the lid angle calculation is correct
again.
This also moves the accel_orientation structure out of the board
directory and into common code, since it purely is a function of
the reference frame being used.
BUG=chrome-os-partner:43494
BRANCH=none
TEST=test on samus, verify lid angle calculation is correct once
again. also, enable the motion_lid test and verify that it passes.
Change-Id: I948a74a71964b54c68be66e828a030ddd0418947
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/300510
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Gwendal Grignou <gwendal@chromium.org>
Instead of mocking i2c_read8/16/32, mock i2c_xfer.
We can now test code that call i2c_xfer directly and
test common/i2c.c
BRANCH=samus, ryu
BUG=chrome-os-partner:45223
TEST=Unit tests pass.
Change-Id: Iaa772515c40cf55d2050d0019e2062d63278adc0
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/299768
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Since there is no more concept of a flash region belonging only to the
EC, we only need one FLASH_SIZE config, which represents the actual
physical size of flash.
BRANCH=None
BUG=chrome-os-partner:23796
TEST=With entire patch series, on both Samus and Glados:
- Verify 'version' EC console command is correct
- Verify 'flashrom -p ec -r read.bin' reads back EC image
- Verify software sync correctly flashes both EC and PD RW images
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: I18a34a943e02c8a029f330f213a8634a2ca418b6
Reviewed-on: https://chromium-review.googlesource.com/297824
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
In order to support architectures with non-contiguous writable and
protected regions, change storage offsets to be relative to writable and
protected regions, rather than relative to "the start of the region of
storage belonging to the EC".
Spec doc available at https://goo.gl/fnzTvr.
BRANCH=None
BUG=chrome-os-partner:23796
TEST=With entire patch series, on both Samus and Glados:
- Verify 'version' EC console command is correct
- Verify 'flashrom -p ec -r read.bin' reads back EC image
- Verify software sync correctly flashes both EC and PD RW images
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: I796f8e7305a6336495bd256a78774595cb16a2e4
Reviewed-on: https://chromium-review.googlesource.com/297823
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
CDRAM / CODERAM configs were previously used for chips which copied code
from external SPI to program memory prior to execution, and were used
inconsistently between npcx and mec1322.
These CONFIGs are now completely redundant given new configs like
CONFIG_MAPPED_STORAGE_BASE and CONFIG_EXTERNAL_STORAGE.
BRANCH=None
BUG=chrome-os-partner:23796
TEST=With entire patch series, on both Samus and Glados:
- Verify 'version' EC console command is correct
- Verify 'flashrom -p ec -r read.bin' reads back EC image
- Verify software sync correctly flashes both EC and PD RW images
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: I0e054ab4c939f9dcf54abee8e5ebd9b2e42fe9c4
Reviewed-on: https://chromium-review.googlesource.com/297804
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
This commit adds a new basic driver for the Kionix KX022 Accelerometer.
Currently, the driver is capable of reading the sensor data and
manipulating its ODR, resolution, and range.
This sensor also has integrated support for Directional
Tap/Double-Tap(TM), however that functionality is not yet implemented in
the driver.
Lastly, since this accelerometer is very similar to the previous KXCJ9,
this commit tries to combine the drivers.
Note, the variant of the Kionix accelerometer MUST be specified in the
private data structure.
BUG=chrome-os-partner:43494
BRANCH=None
TEST=Build GLaDOS EC with driver enabled and verify that valid
accelerometer data is read, and that range, resolution, and odr can all
be modified.
TEST=Build samus EC image and verify that the lid still
works. Additionally, verify that I can change the odr, rate, and
resolution.
TEST=make buildall tests
Change-Id: I238ff1dc13f5342a93f8f701a0da85c52f25d214
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/299013
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Gwendal Grignou <gwendal@chromium.org>
Add all swap commands to USB_PD_CONTROL host command: data,
power, and vconn swap.
BUG=none
BRANCH=smaug
TEST=tested on both samus and ryu while connected to each other.
Change-Id: I280a0da2d3c5a5436243134ab3f2ec353ebf6ab8
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/299290
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Gesture recognition can be done in software (by the EC) or in
hardware, by the sensor itself.
Add variable to compile gesture.c only in the software case.
BRANCH=smaug
TEST=compile.
BUG=b:23570481
Change-Id: I22bef0bf744516df267020d9458e0299a4da3d72
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/296211
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Add support for ADC / thermistor reads on the EC's ADC
This will support now only ncp15wb but we can expand it
at future time.
BUG=chrome-os-partner:44764
TEST=make buildall -j
Manual on celes with subsequent commit. Boot to S0, run "temps".
Verify that temperatures are. See temperature is changing
BRANCH=None
Change-Id: If26d24b803dcff00c4c24e4e1f71d3b0de8e6738
Signed-off-by: Wonjoon Lee <woojoo.lee@samsung.com>
Reviewed-on: https://chromium-review.googlesource.com/296872
Reviewed-by: Shawn N <shawnn@chromium.org>
Separate the bd99992gw ADC interface from the NCP15WB thermistor
adc-to-temp maths so that the thermistor can be used with various
other interfaces.
BUG=chrome-os-partner:44764
TEST=make buildall -j
Manual on Glados. Boot to S0, run "temps".
Verify that temperatures start around 28C and begin to increase after
system is powered-on for a long duration.
BRANCH=None
Change-Id: I3e72e9f390feebaac2440dbe722485f8d1cf8c56
Signed-off-by: Wonjoon Lee <woojoo.lee@samsung.com>
Reviewed-on: https://chromium-review.googlesource.com/296871
Reviewed-by: Shawn N <shawnn@chromium.org>
Enabled the trickle charging mode by setting the MinSystemVoltage
register[0x3EH] to board specific battery voltage minimum value.
When the battery voltage drops below the battery voltage minimum
value, trickle charging enabled.
BUG=none
TEST=Manually tested on Kunimitsu FAB4 prototype.
Drained the battery below voltage minimum value. Using the
i2cxfer command observed Trickle charging mode is active in
the information register[0x3AH].
BRANCH=none
Change-Id: Id6416f2b0b74fda8cf3eafb95e044586f90b8a8e
Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/298143
Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Rong Chang <rongchang@chromium.org>
If the ALS is not enabled in S3/S5 states then it will generate
errors when trying to read so should be gated.
This could be done with a check for chipset_state or adding a
new CONFIG_ALS_POWER_GPIO to check. However the ALS is also not
needed when the host is in S3/S5 yet the task continues to run
in the background every 1 second.
This commit adds a new task enable/disable hook to disable the
task when the system is suspended and enable the task when it
is resumed.
In order to fit this new task in glados the als console command
is guarded by a new config option. Since this is not a very
frequently used/needed console command it is disabled by default.
And finally the kunimitsu and strago boards try to enable ALS
but they never actually enabled the ALS task so this new code was
failing to build because TASK_ID_ALS did not exist. Also samus
was enabling it but as TASK_NOTEST so tests will fail, though
they are disabled globally on samus.
BUG=chrome-os-partner:43493
BRANCH=none
TEST=enable ALS on glados and successfully build and use it,
also successfully build EC and tests for kunimitsu, strago,
and samus which are the other boards that use the ALS task.
Change-Id: I192940d7f306a1663c7cb789c313151bbb5f2b90
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/298156
Reviewed-by: Shawn N <shawnn@chromium.org>
Add option to charge automatically from dual-role devices. This
also changes the charge override behavior such that any new
device attached will clear the override because any new source
is a potential device we might charge from.
BUG=chrome-os-partner:44958
BRANCH=smaug
TEST=tested charge_manager unittests with
CONFIG_CHARGE_MANAGER_DRP_CHARGING both defined and undefined
Change-Id: Iac77ff0c501826d5fb5a9d50f88399ebc3955b87
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/297789
Reviewed-by: Shawn N <shawnn@chromium.org>
When a debug accessory is connected to the type-C port while the write
protection is enabled, put the case closed debugging in "partial" mode
rather than "full".
Update the "partial" mode to provide read-only access to the AP and EC
consoles.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=smaug
BUG=chrome-os-partner:44700
TEST=check the EC console input/output over USB is still working with SuzyQ
on a write-protected system, verify that the console input is disabled.
Change-Id: I5baa03d6e738d06437c45469f46b286e76a755a4
Reviewed-on: https://chromium-review.googlesource.com/297141
Commit-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Anton Staaf <robotboy@chromium.org>
Reviewed-by: Alec Berg <alecaberg@chromium.org>
When all BMI160 sensors are suspended, FIFO is invalid.
Put the test to check if all sensors are disable within the processing
loop: otherwise, the FIFO can become invalid while we are processing it.
Add printf to be sure we are not processing invalid FIFO.
Add a macro around ODR to really check the ODR rate, excluding the
roundup flag.
BRANCH=smaug
BUG=chrome-os-partner:44381
TEST=Using a special patch (see 44381#14) add delay
to simulate a loaded EC (like at resume).
Using a script flip-flop sensors frequency (to simulate suspend/resume).
Check that:
- we are not crashing anymore (we were before this patch)
- the driver is not hitting invalid FIFO content.
Change-Id: I7c9e86f5dcfc231ab89472a6ea03af22e2c2ac32
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/297178
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Before oak rev4, BC 1.2 status change was polled on VBUS change. The
designed is changed to use a single interrupt pin for both ports.
BRANCH=none
BUG=chrome-os-partner:42610
TEST=manual
make EXTRA_CFLAGS=-DBOARD_REV=3 BOARD=oak -j
emerge-oak chromeos-ec
load on oak rev3 and check BC 1.2 charging current
Change-Id: I9e6cdbb83468b5e4086cc86caadf7f2e3cbe6e48
Signed-off-by: Rong Chang <rongchang@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/294442
Based on feedback from programmers, it's not clear when
config_std_internal_flash should be used, and when non-standard
chip-specific layouts need to be defined. Add clarity here with the
following changes:
- Explain in-depth the one config that config_std_internal_flash should
be used for.
- Move non-standard chip-level flash layout CONFIGs to their own new
chip-level file, config_flash_layout. All chips should either include
config_std_internal_flash.h OR define their own layout in their own
config_flash_layout.
Functionally, this change is a NOP.
BUG=chrome-os-partner:23796
TEST=`make buildall -j`
BRANCH=None
Change-Id: I6037b68db9048d90fa2a2da4c9c9e09d1143fa68
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/296527
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
Send soft reset to all connected USB PD ports before a user
initiated reset (via console or host command). This fixes a problem
where EC will send PD hard reset to a charger after an EC reboot, which
will cause another reboot if battery is not present.
BUG=chrome-os-partner:44085
BRANCH=none
TEST=tested on glados without a battery. with zinger attached, issue
'reboot' from console and verify that we only reboot once.
Change-Id: Id6c56cda33c289e3425cb433f7fcbe76669d2dff
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/295889
Reviewed-by: Shawn N <shawnn@chromium.org>
Add config settings for ODR and EC rate per requestor and
per power state (1 for the AP, 3 for the EC).
This way we can finely set ec rate and ODR depending on usage.
On chromeos, AP is not setting frequency, so EC sets for different power
state. On some platform, sensors can now be suspended in S3/S5.
Allow EC oversampling when AP is only looking for a few samples.
It is useful for double tap detection where high accelerator ODR is
required.
BRANCH=ryu
TEST=Tested on Ryu
BUG=chromium:513458
Change-Id: Ic3888a749699f07b10c5da3bc07204afd4de70da
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/295637
Simplify sensor get_data_rate, get_range and get_resolution.
Error code was not checked and these functions as currently implemented
have no reason to fail.
BRANCH=ryu,samus,cyan,strago
BUG=chromium:513458
TEST=Check on ryu, compile
Change-Id: I40dca41cee29a19f65b2f84d434b4c19eb6cbf3c
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/295635
Reviewed-by: Sheng-liang Song <ssl@chromium.org>
The format of an ep packet header (8 bytes) :
Packets for cc1: [sample_tstamp, sample_seq, vbus_voltage, tstamp_offset]
Packets for cc2: [sample_tstamp, sample_seq, vbus_current, tstamp_offset]
Updated: use array to implement a circular queue; when a forming a packet,
remove one element from the queue. In this way, we can capture more samples
of vbus information.
Updated: when sniffer task has not started sending packets, most recent vbus
info is always stored at the first position of the queue, making sure that
the first reported vbus info is the most recent one.
Updated: allow user to compile the original version or the new version of the
source code. In ec/board/twinkie/board.h
Use #define CONFIG_USBC_SNIFFER_HEADER_V1, if you do not want twinkie to
send out vbus info;
Use #define CONFIG_USBC_SNIFFER_HEADER_V2, if you want twinkie to send out
vbus info.
Signed-off-by: Dawei Li <daweili@google.com>
BUG=chrome-os-partner:42703
BRANCH=none
TEST=BEGIN
connect Twinkie to a waveform generator, record data using:
sudo sigrok-cli -d chromium-twinkie --continuous -o test.sr
then check the resulting waveforms on pulseview.
END
Change-Id: Ifdb6402eb7d998ffb25128c510d1780491b11872
Reviewed-on: https://chromium-review.googlesource.com/282388
Commit-Ready: Sheng-liang Song <ssl@chromium.org>
Tested-by: Dawei Li <daweili@google.com>
Reviewed-by: Sheng-liang Song <ssl@chromium.org>
Certain boards may need to handle fixing up the RESET_FLAG_s
because of the boards' designs. Provide an optional per-chip
implementation to save the reset flags. Note that this
function is not protected by a CONFIG_ option as it can just
be implemented by the chip if a board requires it. Lastly,
implement chip_save_reset_flags() for mec1322 for future use.
BUG=chrome-os-partner:44527
BRANCH=None
TEST=Built and booted on glados.
Change-Id: I604fe4e6a069f31727bab52288595a349e3dbe72
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/295115
Reviewed-by: Robbie Zhang <robbie.zhang@intel.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
AMONBMON is a charger feature to measure input current and battery output
current. ISL9237 output analog value of voltage diff across sense
resistor to EC's ADC channel. This change also reorders oak's ADC channel
to fix a reading bug.
BRANCH=none
BUG=chrome-os-partner:42270
TEST=manual
in EC serial console, type command 'adc' and check AMON_BMON value.
type command 'amonbmon' and check AC current and BAT current.
Change-Id: I9db0a72be7c9a428a16d1609eb8c461c6928e548
Signed-off-by: Rong Chang <rongchang@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/283665
Reviewed-by: Shawn N <shawnn@chromium.org>
Add a slow inverse matrix calculation function.
It is needed to apply factory offset properly.
Also consider the NULL matrix the identity matrix.
BRANCH=smaug,cyan
TEST=Unit test
BUG=chromium:517675
Change-Id: Ifa11954992e6f2fab02b4e92684e7b01bbaafe94
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/294594
Reviewed-by: Sheng-liang Song <ssl@chromium.org>
Working on light sensor, sensor were read on every time,
SENSOR_EC_THRES was not taken into account.
Fix 64/32 conversions and add a function for dealing with rollover.
TEST=Set light sensor probe at 1s. Set accel sensor at 100Hz to fill
fifo often; verify that light sensor is queried every second only.
BRANCH=smaug
BUG=chrome-os-partner:39900
Change-Id: If1df53c1a9a304c992f8e517f5d516210118a437
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/291992
Reviewed-by: Sheng-liang Song <ssl@chromium.org>
Add the Silicon Image sensors, add it to the motion_sense module
to be used with the FIFO.
BRANCH=smaug
TEST=Check light and proxy on Smaug:
Check Light value in Lux are reasonable.
Check Proxy is detecting object, but value are in opposite of distance.
BUG=chrome-os-partner:32829
Change-Id: I11419a0f0613f0fae9323f99deedf5a1e6c6e29c
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/291335
Reviewed-by: Sheng-liang Song <ssl@chromium.org>
Add a mask of custom events reserved for IRQ based sensors.
Copy data from raw_xzy to xyz while filling the FIFO
when FIFO is enabled.
BRANCH=smaug
TEST=Test with si1141 driver, check irq works for both driver.
BUG=chrome-os-partner:32829
Change-Id: I5e106df0c121e3bf1385f635195717395235ccc3
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/291334
Reviewed-by: Sheng-liang Song <ssl@chromium.org>
Allow sending calibration information to the magnetometer.
BRANCH=smaug
TEST=Check from user space that calibration is taken into account.
BUG=chrome-os-partner:39900
Change-Id: Ic0f595bde1afdc0b6a79e3516a42b55d1f50c17c
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/291333
Reviewed-by: Sheng-liang Song <ssl@chromium.org>
PD charger voltage + current can now be limited with
EC_CMD_EXTERNAL_POWER_LIMIT. The limit is automatically cleared when the
AP transitions out of S0 into S3 / suspend.
BUG=chrome-os-partner:43285
TEST=Manual on Samus w/ zinger.
- Plug zinger, verify charging at 20V/3A.
- `ectool extpwrlimit 3000 12000 --dev=1`, verify charging at 12V/3A
- `ectool extpwrlimit 1000 5000 --dev=1`, verify charging at 5V/1A
- Plug zinger into other port, verify still charging at 5V/1A
- `powerd_dbus_suspend`, verify charging at 20V/3A
- `chglim 2000 12000`, verify charging at 12V/2A
- `ectool extpwrlimit 0xffff 0xffff --dev=1`, verify charging at 20V/3A
- `chglim 1000 20000`, verify charging at 20V/1A
- `chglim`, verify charging at 20V/3A
BRANCH=ryu
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: I6cd5377be91b3df75f99cb414fd3fa5a463b56cb
Reviewed-on: https://chromium-review.googlesource.com/293954
Reviewed-by: Todd Broch <tbroch@chromium.org>
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Some platforms might expect the header of the image to be a certain
platform specific blob. This patch adds an ability to insert an
arbitrary size header in the binary blob, if so desired, the intention
is to have the platform specific tools to postprocess the image and
replace the header with sensible data.
Ideally we should be able to produce an image which is mapped to start
at an offset to the FLASH_BASE, but the macros in ec.S.lds files are
way too smart for this.
BRANCH=none
BUG=chrome-os-partner:43025
TEST=with this and other changes the latest cr50 image gets signed and
booted properly.
Change-Id: Icabf00c6b90657b0ae3370ddad3567ccedf3ff49
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/295200
Reviewed-by: Shawn N <shawnn@chromium.org>
Oak board revisions are not global configs. Move them out of
include/config.h . This change also makes it easier to build EC
and PD image for different board revisions.
BRANCH=none
BUG=none
TEST=manual
build for board revision n and load on oak:
make BOARD=oak clean
make BOARD=oak_pd claen
make EXTRA_CFLAGS=-DBOARD_REV=n BOARD=oak -j
make EXTRA_CFLAGS=-DBOARD_REV=n BOARD=oak_pd -j
Change-Id: I331b4c5a1af94b179d7c6f7878a9c3939ea6025a
Signed-off-by: Rong Chang <rongchang@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/294441
Reviewed-by: Shawn N <shawnn@chromium.org>
Modified TCPC layer to utilize the Power_Status and Power_Status_Mask
registers. VBUS status is stored in Power_Status and when a change
is detected, it's communicated to the TCPM via the ALERT# line.
BUG=chrome-os-partner:43440
BRANCH=none
TEST=Tested the feature on Glados and Oak connecting to both Ziger
and Samus. Verfied that VBUS status is communicated via the TCPCI and
that PD contracts are established without using the VBUS_WAKE GPIO
lines on Glados and Oak.
Change-Id: Ie5aa32eecc887f3cb00880a285f1e710b7064384
Signed-off-by: Scott Collyer <scollyer@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/289931
Reviewed-by: Rong Chang <rongchang@chromium.org>
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Commit-Queue: Rong Chang <rongchang@chromium.org>
Tested-by: Rong Chang <rongchang@chromium.org>
BUG=none
TEST=Used "shutdown -h now" Kernel console command to test on Kunimitsu.
With only battery after 1 hour, device enters to Pseudo G3 and the
V3p3A is off. With AC connected, device is in G3.
BRANCH=none
Change-Id: I955662eb69ac608e9b2d12bdcfbc1258ca83f3a5
Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/292976
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Create a config to allow customization of a board's charger
termination current and add support to bq2589x charger.
Note, BQ2589X_TERM_CURRENT_LIMIT_DEFAULT, currently set to 64 to make
CL benign to ryu board. Future CL will change to 256 as thats the POR
value for that charger.
Signed-off-by: Todd Broch <tbroch@chromium.org>
BRANCH=smaug
BUG=chrome-os-partner:42848
TEST=manual, read charger IC register and see its termination current
set to 64mA
Change-Id: I79348ed62a077a6432c8d8db6ac90e1e4e92dbc7
Reviewed-on: https://chromium-review.googlesource.com/293095
Reviewed-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Todd Broch <tbroch@chromium.org>
Commit-Queue: Todd Broch <tbroch@chromium.org>
When there is an interrupt event, N8 CPU will save PSW register to IPSW
register and clear GIE then jump to interrupt service routine. N8 will
restore PSW from IPSW after "iret" instruction (the above are purely
hardware mechanism).
Nested interrupt will occur if we set GIE again in interrupt context.
symptom:
power button pressed while LID open -> exception or unknown reset.
Signed-off-by: Dino Li <dino.li@ite.com.tw>
BRANCH=none
BUG=none
TEST=1. Manually pressed power button x200.
2. Console "eflash" erase and write eflash OK.
Change-Id: Ic04a23d473ebc6417dffea814a27583cb8d63a1f
Reviewed-on: https://chromium-review.googlesource.com/289437
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Commit-Queue: Dino Li <dino.li@ite.com.tw>
Tested-by: Dino Li <dino.li@ite.com.tw>
