Switch it to a source-only PD device (as it is)
and add the voltage selection code.
For now, output 12V only for 20V request as the 5V->20V transition is
not monotonic, triggering disconnection detection.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=samus
BUG=chrome-os-partner:37078 chrome-os-partner:41860
TEST=connect to Samus and see it negotiate 5V then 20V,
then manually switch to 12V.
Change-Id: I4fc198245999ff9ce8fec929f305681043d72965
Reviewed-on: https://chromium-review.googlesource.com/259113
Trybot-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
mutex_lock() is called from MEC1322_IRQ_ACPIEC0_IBF
interrupt context, causing deadlock and assertion
in __wait_evt().
In the interrupt context it now checks for mutex lock first.
If the mutex is already locked,, it will disable ACPI
interrupts and defer the memmap mutex lock.
Added LPC interrupt disable/enable functions as needed.
Increased deferred function count where needed.
BRANCH=None
BUG=chrome-os-partner:40820
TEST=Test for suspend-resume, cold, warm reboots and
other general stability.
Change-Id: I3dda0d4635a6b6281faf200c8c7b6fcba8877254
Signed-off-by: Chiranjeevi Rapolu <chiranjeevi.rapolu@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/280418
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
Commit-Queue: Divya Jyothi <divya.jyothi@intel.com>
Tested-by: Divya Jyothi <divya.jyothi@intel.com>
This change enables tmp432 thermal sensor. Enter "tmp432"
or "temps" in ec console and get temperature information.
BRANCH=none
BUG=none
TEST=manual
Enter "tmp432" to get temperature information.
Connect the battery and enter "temps" to get temperature
information.
Change-Id: Ie7a9fb4541c5cb3cfa6a26e95f99fe4aacb3a3d3
Signed-off-by: YH Huang <yh.huang@mediatek.com>
Reviewed-on: https://chromium-review.googlesource.com/280956
Reviewed-by: Rong Chang <rongchang@chromium.org>
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Add the console command "power on/off" for AP power on/off.
BRANCH=none
BUG=none
TEST=manual
enter "power on/off" in the ec console to turn AP power on/off.
Change-Id: I16d2af72bc1bf045e7672acd9471dff0a672aff5
Signed-off-by: YH Huang <yh.huang@mediatek.com>
Reviewed-on: https://chromium-review.googlesource.com/280957
Reviewed-by: Alec Berg <alecaberg@chromium.org>
There were many CONFIG_* options that were not defined in
include/config.h. This commit fixes that by adding those config options
that were missing with a brief description of each.
BUG=chromium:496893
BRANCH=none
TEST=Verified that every mention of CONFIG_* is in include/config.h.
TEST=make -j buildall tests
Change-Id: Ie60756a8dd48d12b3e9b775639f409455dc5656f
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/281785
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Commit-Queue: Aseda Aboagye <aaboagye@chromium.org>
Trybot-Ready: Aseda Aboagye <aaboagye@chromium.org>
Create driver/tcpm/ folder to hold TCPM drivers. Currently the
two drivers are a stub driver which is used when TCPM and TCPC
are on the same MCU and can make direct calls between the two
and the TCPCI driver which implements the standard TCPCI protocol.
BUG=chrome-os-partner:41842
BRANCH=none
TEST=make -j buildall
Change-Id: Ie4d9b36eb33155254f8b87b83861f98a7a80693a
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/281630
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Set the resistance compensation for the charger IC according to the EE
team measurements :
- Resistance compensation = 60 mOhm
- Voltage clamping = 160 mV
- Thermal regulation = 120C
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=smaug
BUG=chrome-os-partner:38603
TEST=dump the BQ25892 registers by using the "bq25" command and see that
REG08 contains 0x77.
Change-Id: I90e9ea4569d77fd90ed0290ec78e66810d744648
Reviewed-on: https://chromium-review.googlesource.com/281660
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
Trybot-Ready: Vincent Palatin <vpalatin@chromium.org>
Send PD_EVENT_POWER_CHANGE events for all changes in the type-C/PD
configuration to ensure we are not missing any transition from the AP.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=smaug
BUG=chrome-os-partner:41676
TEST=On Ryu, plug and unplug type-C chargers, C-to-A receptacle
adapters and A-to-C cables and see the proper "extcon" traces in the
kernel log.
Change-Id: I918b9c42867f069852a2222b0f47ef0df8d124aa
Reviewed-on: https://chromium-review.googlesource.com/280870
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
Trybot-Ready: Vincent Palatin <vpalatin@chromium.org>
Since the reset cause was not recorded correctly
recovery mode(Esc+Refresh+Power) was not working.
With this change power-on reset state and VCC1_RST# only state
are distinguinshed.
BUG=chrome-os-partner:41479
BRANCH=none
TEST=Esc+Refresh+Power boots to recovery screen
Refresh+Power reboots the system
Change-Id: I63eff488c970302e7afe8a677a57ad27d4d9918e
Signed-off-by: Divya Jyothi <divya.jyothi@intel.com>
Signed-off-by: Freddy Paul <freddy.paul@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/280782
Reviewed-by: Shawn N <shawnn@chromium.org>
Base board configuration to evaluate USB PD interface chip by
connecting them a STM32F072 Discovery board.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=none
BUG=chrome-os-partner:41497
TEST=Flash the STM32F072 discovery using the following command:
make flash BOARD=pdeval-stm32f072
then connect to the EC console through the USB port.
Change-Id: Ie3f5dcd04c077be49fbacc020f7af4f298039e8a
Reviewed-on: https://chromium-review.googlesource.com/277713
Tested-by: Alec Berg <alecaberg@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Commit-Queue: Alec Berg <alecaberg@chromium.org>
Modify PDCMD task to allow for TCPCs that do not support host
commands.
CONFIG_HOSTCMD_PD is a new config option to be used by TCPCs
that implement our host command protocol such as the PD MCU on
glados and oak. Otherwise, the PDCMD task will not send host
commands and will be used simply to check TCPC interrupt status.
BUG=none
BRANCH=none
TEST=test on glados and samus and make sure we can send host
commands from the EC to the PD and that we can negotiate a PD
contract.
Change-Id: I618badb5db3f9e490ae4eedfdb2a0c54513496ff
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/278215
Reviewed-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Changed the alert function to hold the ec_int line until
all of the alert bits are cleared. Added support for the
alert_mask register. In addition, created ec_int_status
variable to distinguish which of 3 ec_int sources is
driving the pd_mcu_int line.
BUG=none
BRANCH=tot
TEST=Tested Zinger to Glados and Zinger to Samus and verified
that it established a power contract in both cases. Did not
test Oak, but put exact same changes in board.c as in glados.
Change-Id: I372e75b8fd5d66a0c01db18b46100b86fd9ac064
Signed-off-by: Scott Collyer <scollyer@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/278256
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Fix USB PD check power and data swap functions after those
functions have been refactored and the args changed.
BUG=chrome-os-partner:41739
BRANCH=none
TEST=make -j buildall
Change-Id: I746774563d475710dc23c7290328fab150eaac6a
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/280993
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
According to spec, RSMRST shouldn't be deasserted until 10ms after power
signals become active.
BUG=chrome-os-partner:41556
TEST=Manual on Glados. Verify that AP boots to S0 on power-on, goes to
G3 on apshutdown, and back to S0 on powerbtn.
BRANCH=None
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: I0acc897fff7c18ad83fc87734569ec7639ae5cf4
Reviewed-on: https://chromium-review.googlesource.com/280571
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
This unifies all the EC header files to use __CROS_EC_FILENAME_H
as the include guard. Well, except for test/ util/ and extra/
which use __TEST_ __UTIL_ and __EXTRA_ prefixes respectively.
BUG=chromium:496895
BRANCH=none
TEST=make buildall -j
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Change-Id: Iea71b3a08bdec94a11239de810a2b2e152b15029
Reviewed-on: https://chromium-review.googlesource.com/278121
Reviewed-by: Randall Spangler <rspangler@chromium.org>
There is no need for the usb flag, remove it.
There is no need for the unprotect flag, remove it.
BRANCH=none
BUG=chrome-os-partner:22990
TEST=run flash_ec before and after
Change-Id: I201bad7f5be63a90bb8168e21baef2c6fa8d85b4
Signed-off-by: Myles Watson <mylesgw@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/273904
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Update the recovery key combination to: power key + volume up when the
AP is off.
Add a fastboot key combination: power key + volume down when the AP is
off.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=smaug
BUG=chrome-os-partner:41629
TEST=on Ryu, shutdown the AP, press "power+volup" or "power+voldown" and
see the right trace.
Change-Id: I42cf368d42885717758fc4b494af5c8a16fc58b0
Reviewed-on: https://chromium-review.googlesource.com/278323
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
For the few platforms without gpio.inc, use this
enum gpio_signal {
GPIO_COUNT
};
instead of this
enum gpio_signal {
NULL
};
The only reason this worked at all is that the headers are
included in a particular order.
BUG=none
BRANCH=none
TEST=make buildall
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Change-Id: I81533f3614d0b4c7389f9edd42cd8ac018581f46
Reviewed-on: https://chromium-review.googlesource.com/278120
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Console command 'batter' reaches STM32F0's TASK_STACK_SIZE(488). Oak
needs a larger stack in development stage.
BRANCH=none
BUG=none
TEST=manual
load on oak and type 'battery' in console.
Change-Id: Iab3d0bd23837932acb873ecdeb194af74f10f29c
Signed-off-by: Rong Chang <rongchang@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/277979
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Use the right rounding function for the charging voltage selection.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=smaug
BUG=chrome-os-partner:41594
TEST=On Smaug EVT2, check that the battery is charging to 100% and
compare the voltage requested by the battery (using "battery" command)
to the voltage set by using "charger" command.
Change-Id: Ic5076f23242d1fac31ad34e0c8c9bfe0a868a91e
Reviewed-on: https://chromium-review.googlesource.com/278260
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Setup wakeup source and enable hibernate support.
BRANCH=none
BUG=chrome-os-partner:40752
TEST=manual
start servod:
sudo servod -b oak -c oak.xml
in EC console, type 'hibernate' to enter hibernate mode.
check ec 3.3v current and power consumption:
dut-control ec_3v3_ma ec_3v3_mw
check wakeup source:
open lid, press power button or plug in charger
Change-Id: Ic32c3879b0b9dac86c5e08ab9f3daba428c58720
Signed-off-by: Rong Chang <rongchang@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/277978
Reviewed-by: Alec Berg <alecaberg@chromium.org>
This just makes the LEDs blink continually, because I have a
development board sitting on my desk and I like to see it doing
something.
You can still force the GPIOs on and off using the tool in
extra/usb_gpio/.
BUG=none
BRANCH=none
TEST=make buildall
Try it:
sudo make BOARD=discovery-stm32f072 flash
The LEDs blink.
Force them on and off with:
cd extra/usb_gpio
make
./usb_gpio write -1 0
./usb_gpio write 0 -1
./usb_gpio write 2 0
./usb_gpio write 4 2
To resume blinking, use
./usb_gpio write 0 0
Change-Id: Iadbe7436c02de5b6eae81885d95bad154ca3692c
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/274131
Reviewed-by: Anton Staaf <robotboy@chromium.org>
This change enables USB3/DP superspeed mux. Oak's two type-C ports share
one DP hardware. When both ports connect to DP output device, only the
first DP signal will be routed to SoC. On exit dp mode, oak sends HPD
again if the other port's DP flag is on.
BRANCH=none
BUG=chrome-os-partner:41404
TEST=none
Change-Id: I7eebc0b2354f93d7421bf83796294a6b2acf4c3b
Signed-off-by: Rong Chang <rongchang@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/277000
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Add functions and associated test to read/write a 32 bit register
BRANCH=smaug
TEST=Test on smaug with bm160 driver
BUG=chromium:39900
Change-Id: Ieff24b65f1eb8610874fe13c4a8fadf583a218cb
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/277535
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Add TCPC support for USB VID register and use that register
from the TCPM side to know when the TCPC is ready. TCPC is
ready when phy layer is initialized and CC ADC channels have
been read.
BUG=chrome-os-partner:40920, chrome-os-partner:41258
BRANCH=none
TEST=load and run glados. verify that glados EC doesn't
start sending TCPC commands until it can successfully
read TCPC VID. verify that we can boot with zinger and no
battery.
Change-Id: Iafbab529a16ff904cdb817901baac5e72e3d7220
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/277710
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
BUG=chrome-os-partner:40526
TEST=Enable Software Sync in Coreboot and Depthcharge. Compile
EC followed by Coreboot and program Coreboot. Compile a new
version of EC and program it. Reboot and check EC version of
RW image when Login Screen appears. The version should not be
the latest.
BRANCH=none
Change-Id: Ib6f5aa57fdda607a5c1cf59c8786a4a3a46b575f
Signed-off-by: Shamile Khan <shamile.khan@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/276426
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Initialize CC termination variable based on the default PD role.
BUG=chrome-os-partner:40920
BRANCH=none
TEST=load on glados. test by rebooting PD from PD console with
nothing plugged into the type-C ports. Without this change, the
EC gets stuck in SNK_DISCONNECTED_DEBOUNCE, because the PD defaults
to using the wrong termination and so the PD thinks the CC ADC
readings represent Ra. At this point you have to reboot EC to get
back to normal functionality. With this change, rebooting PD does
not wedge the PD protocol state machine.
Change-Id: I4eb6d881d8fc995be4d6a99ffa69e484141343f2
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/277666
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
BUG=chrome-os-partner:41063
TEST=Enable Software Sync in Coreboot and Depthcharge.
Enable hash computation in EC. Compile EC followed by
Coreboot and program Coreboot followed by EC on a Cyan
system. System should boot to Chrome Login Screen.
BRANCH=none
Change-Id: I4b53e9e55e4da279366eb1283a11a010c52b865f
Signed-off-by: Shamile Khan <shamile.khan@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/276305
Reviewed-by: Shawn N <shawnn@chromium.org>
changes added to support flashrom are:
sysjump support to be able to copy the RO/RW image
and jump to it without causing AP to reboot while
its alreday ON.
LPC init should be reinitialized on sysjump
corrected gpio_set_flags_by_mask to make sure we
update the register only for GPIO_LOW condition and not
all else conditions.
BUG=chrome-os-partner:38103
TEST=commands : flashrom -p ec -w ec.bin
flashrom -p ec -r ec.bin
BRANCH=none
Change-Id: I23892f0378d756052030e73034c3acdd41477e34
Signed-off-by: Divya Jyothi <divya.jyothi@intel.com>
Signed-off-by: Shamile Khan <shamile.khan@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/272000
Reviewed-by: Shawn N <shawnn@chromium.org>
Without this change, after a while, the data from the accelerometer is
garbled, weaker than expected.
BUG=chromium:494270
TEST=Check that with this change, the accelerometer vector is always
around 1G.
BRANCH=smaug
Change-Id: I9bb4acd208e8fa4111fc91e35c4cb5636f9425f4
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/276666
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Move disabling the TX timer up to as soon as possible after
DMA transmit is complete to avoid potentially clocking another
bit, which could corrupt the end of the transaction.
BUG=none
BRANCH=smaug
TEST=load on glados and use a scope to verify the end of transmit
is clean.
Change-Id: If52ba2475eeb9752da0acc8efc957c1f472bc711
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/277298
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
If the AP is already shutdown, apshutdown would previously power the AP
up with a power press. Fix this by making sure we're not already in G3
before triggering the power press.
BUG=chrome-os-partner:40677
TEST=Run 'apshutdown' on glados while in G3, verify that AP does not
power up.
BRANCH=None
Change-Id: I8b898b034dcf40f0acef4fb6098af0aebba566c6
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/277400
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Change pd_tx_done() to wait specifically for the DMA complete
event using task_wait_event_mask().
This fixes a potential bug where if we get another event, for
example a TCPM event, while waiting for transmit to complete
we restore the pending event after we are done.
BUG=none
BRANCH=smaug
TEST=run on glados and make a bunch of contracts with zinger.
Change-Id: Ie28d97eba3edcc7a98fe842e8b7eb6b9d7707047
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/277297
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Change TCPC to not sample CC ADC channels immediately after transmit
because we are likely to get a response immediately after transmit
and this could cause us to sample while traffic is on the line and
cause us to record the wrong voltage.
BUG=none
BRANCH=smaug
TEST=test on glados. put a print when TCPM is notified of CC voltage
change. without this CL, we occasionally get a false CC voltage
change. with this change, CC status stays consistent.
Change-Id: I9199a0ed98632b1f26b2b5b98f34928e4de328bf
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/277296
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Disabling CC TX_DATA needs to be very fast to avoid clocking out
an extra garbage bit at the end of transmit. This change fixes
pd_tx_disable() to disable the TX_DATA line as fast as possible.
BUG=chrome-os-partner:40920
BRANCH=none
TEST=test on glados with scope attached to CC. note before this
change we occasionally get a garbage bit at the end of CC transmit.
With this change, it looks clean.
Change-Id: I86b47881e3846b2e3dd4fc2afcf2d28386a068a6
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/277295
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
