Enabled deep sleeping during S0. This was previously inhibited by
SLEEP_MASK_AP_RUN but the new config option (CONFIG_LOW_POWER_S0) will ignore it.
SPI needed a sleep mask, it essentially gets enabled and disabled whenever the
CS changes. Warning: waking up when the CS falls takes a little time, if the AP
sends fast data before the 48MHz clock is enabled characters will get corrupted;
leave about 30uS time for the clock to start.
CQ-DEPEND=CL:219997
CQ-DEPEND=CL:220243
CQ-DEPEND=CL:220461
BUG=chrome-os-partner:32223
BRANCH=none
TEST=load onto pinky, boot the AP(S0), use idlestats command to verify
that we are going into deep sleep (STOP mode). Verify that everything works
normally during S0(SPI, keyboard, anything that requires the EC to wakeup).
Change-Id: I81c4fa472332f1ad8ad93301089a99dcdb108948
Signed-off-by: Alexandru M Stan <amstan@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/219555
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Currently, when an assertion fails, the error message is like:
ASSERTION FAILURE '1 + 1 == 3' in command_apreset() at common/chipset.c:24
To save flash space, let's add an option to remove the failed
expression and function name. The error message becomes:
ASSERTION FAILURE at common/chipset.c:24
BUG=chrome-os-partner:32203
TEST=make buildall
TEST=Add an assertion and triggers it. Check error message.
BRANCH=None
Change-Id: Ie323d5b43cbff2cd8f6cd5bb46c1f34ecd16bd5e
Signed-off-by: Vic Yang <victoryang@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/219670
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Sometimes I2C1 is wedging and this can cause the ALS task to
overflow its stack.
As a temporary measure to stop the random reboots increase the
ALS task size.
BUG=chrome-os-partner:32471
BRANCH=samus
TEST=build and boot on samus with stuck I2C1
taskinfo before (after fresh reboot):
2 ALS 00000000 0.001012 364/384
taskinfo after (notice it is >384 after some time):
2 ALS 00000000 0.031586 400/512
Change-Id: I04e9b93d3cc60afd3303eb4610c81952f365b992
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/220442
Reviewed-by: Alec Berg <alecaberg@chromium.org>
This pin is already set to out+low so it should be fine to rename
it on EVT1 boards.
BUG=chrome-os-partner:32031,chrome-os-partner:32359
BRANCH=samus
TEST=make buildall
Change-Id: I0d904b0301b793bbfa1d829b4fce60e0b1154b00
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/220259
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Add low power mode for zinger. This uses stop mode in task_wait_event(),
the non-runtime equivalent of the idle task.
BUG=chrome-os-partner:28335
BRANCH=samus
TEST=load onto zinger and plug and unplug into samus a bunch of times
to make sure it negotiates to 20V every time. also send custom vdm's
from samus_pd and make sure those always succeed.
Change-Id: I626365e7d22e030792d28dbf7eafaeb8f54f8a74
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/219933
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Enable flash prefetch buffer for stm32f0 chips to make for
faster CPU execution.
BUG=none
BRANCH=none
TEST=load onto samus_pd and zinger. let run for a while.
connect/disconnect AC a few times. boot samus.
Change-Id: I88c0ae67a3205987344552f5b44952f9890c8177
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/219921
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Alexandru Stan <amstan@chromium.org>
Enable low power idle for veyron (with uart wakeup as well).
Low power idle is only active in S5/S3.
Also sorted options from board.h
BUG=chrome-os-partner:31226
BRANCH=none
TEST=load onto pinky-proto1, use idlestats command to verify that we are going
into deep sleep (STOP mode). Run 30 min. and verify no watchdog reboots or
anything out of ordinary.
Change-Id: Id14b04f33ea46b1e6cca1c8e812b5875e9ee0446
Signed-off-by: Alexandru M Stan <amstan@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/219044
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Fix potential bug in ADC initialization. After setting ADEN bit to
enable ADC module, we must wait for ADRDY (ADC ready) bit before
continuing. This bug only affects a few chips, and only some of
the time.
BUG=chrome-os-partner:31978
BRANCH=none
TEST=Used a samus board where the PD MCU fails ADC initialization
quite often. Without this fix, if you reboot the PD MCU, it will
sometimes come up with all ADC's reading 0 and ADEN reading 0.
With this fix, it always boots with the ADC's working
Change-Id: Iba1d0e56006ba1ad6d9f0eee964a70ef2d0f8dcf
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/219522
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Vic Yang <victoryang@chromium.org>
This code is used to find the orientation of the sensor.
Given sensor are aligned with the edges of the device,
it is not too dificult to find manually.
BRANCH=ToT
BUG=None
TEST=Check ACCEL_CALIBRATE is not used anymore.
Check 'make buildall -j' works.
Change-Id: I81ffcb4f6b01c530ef16baf13113a5942f615092
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/219527
Reviewed-by: Alec Berg <alecaberg@chromium.org>
This task echo's all bytes from any console stream back to all
other console streams. It is a test case for the new
multi-USART and USB stream drivers.
Signed-off-by: Anton Staaf <robotboy@chromium.org>
BRANCH=None
BUG=None
TEST=make buildall -j
Manual testing of cutting and pasting large blocks of text
into the echo'ed usarts, and verifying no dropped characters.
Change-Id: I408c77e40931d3a473657326f9772e71a7ae8a60
Reviewed-on: https://chromium-review.googlesource.com/213178
Reviewed-by: Vic Yang <victoryang@chromium.org>
Commit-Queue: Anton Staaf <robotboy@chromium.org>
Tested-by: Anton Staaf <robotboy@chromium.org>
'powerindebug' is only used when there is a problem with power
sequencing. 'taskready' is rarely used and the same info can be
retrieved by 'taskinfo'.
Put both behind config flags and disable 'taskready' by default. Also
disable 'powerindebug' for Ryu.
BUG=chrome-os-partner:32203
TEST=Build Ryu and check flash space used.
BRANCH=None
Change-Id: I753a1f5411d6e840a80aba03afc94f9640d381a8
Signed-off-by: Vic Yang <victoryang@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/219490
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
When a cable is connected, set USBC_POLARITY to the right polarity. This
is done in a different way than how we do this on other boards because
we only want to control polarity automatically on cable connection.
BUG=chrome-os-partner:32163
TEST=Flip the cable, check USBC_POLARITY changes.
BRANCH=None
Change-Id: I903123b8fd729e8c913014b83812d20328600f8e
Signed-off-by: Vic Yang <victoryang@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/219291
Reviewed-by: Alec Berg <alecaberg@chromium.org>
When 5v/12v/20v buttons are pressed, plankton first switchs to source
role, set the requested source cap, and then perform a soft reset.
However, if plankton was sink and just switched to source, the port
partner might not have switched to sink and this leaves the CC line in a
state where communication is not possible. The subsequent soft reset
then fails. If we are not already sourcing power, we actually don't need
a soft reset after changing source cap.
BUG=chrome-os-partner:32163
TEST=Switch from sink to source. Doesn't see "soft reset" in console.
TEST=Switch from 5V to 12V. See "soft reset".
BRANCH=None
Change-Id: Ia4b834c2e7dc1324b9143c46a72938845499e2fb
Signed-off-by: Vic Yang <victoryang@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/219004
Reviewed-by: Alec Berg <alecaberg@chromium.org>
On power-on reset, the USB hub might get stuck in a locked state due to
a race condition in hardware. Let's reset the hub after 0.5 seconds to
make sure this doesn't happen.
BUG=chrome-os-partner:32163
TEST=Power on the board. Measure the reset signal.
BRANCH=None
Change-Id: I0f89883c5db7c5376f3612da1615ba4f86b5efa6
Signed-off-by: Vic Yang <victoryang@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/219199
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Enable low power idle for samus_pd. Low power idle is only
entered when no USB PD device is connected.
BUG=chrome-os-partner:31226
BRANCH=none
TEST=load onto samus_pd, use idlestats command to verify
that we are going into deep sleep (STOP mode). Run 30 min.
and verify no watchdog reboots or anything out of ordinary.
Also, verify that host commands from EC work when going into
deep sleep by sending host commands on the EC console with
pdcmd 0 0.
Change-Id: I3e2e04e6c4c0a84e291286dbed90945847e0dfdd
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/218957
Reviewed-by: Todd Broch <tbroch@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
OSPEEDR cfg for PB15 was inadvertently set to '01' for PB15 (should be
'00'). Not sure it causes any harm but shouldn't be set according to
comment which is speeding up output pins on SPI interface PB12-14
only.
BRANCH=none
BUG=none
TEST=manual, compiles, boots, talks PD w/ samus_pd.
Change-Id: Ibc2ec1c427a2c3c92ffdf424b668752b1c0b0032
Signed-off-by: Todd Broch <tbroch@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/217963
Reviewed-by: Vic Yang <victoryang@chromium.org>
The PWRON signal is actually a pulse that's only supposed to happen at the S0->S5
transition. We can release it when we see POWER_ON.
BUG=None
TEST=Power on and power off normally. "halt" makes the system go to S5 instead
of rebooting.
BRANCH=None
Change-Id: I14f1cc83c8a4a89226574cf605823d247ce9508a
Signed-off-by: Chris Zhong <zyw@rock-chips.com>
Signed-off-by: Alexandru M Stan <amstan@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/217690
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Increase task stack size for PD host command task to 512. The nominal
stack size is 328 / 384, which is pretty close to the edge.
BUG=none
BRANCH=none
TEST=make -j buildall
Change-Id: Ifdf04923b817c832cbb77ba7f61c06a560aec97d
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/217452
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
PD accessories that are RW update-able will broadcast their rw_hash
SHA1 digest upon connection to the PD MCU which will store it.
For update purposes, the host needs that accessories device id and
rw_hash to determine its proper firmware update payload.
This CL creates a host command that requests the type-C accessory info
attached to a particular port. It also implements an ectool command
to expose the host command.
BRANCH=none
BUG=chrome-os-partner:31361
TEST=manual,
# connect zinger to port 1 on samus
ectool --dev=1 --interface=lpc infopddev 1
Port:0 Device:1 Hash: 0x7f4d7a13 0xf07b65b9 0x41181e10 0xb99b3d5f 0x9dee1206
ectool --dev=1 --interface=lpc infopddev 0
Port:0 has no valid device
Also do the same on port 0 with similar results.
Change-Id: Id63c7edad77a43d43c14d8cd6bd96e08d0d9b501
Signed-off-by: Todd Broch <tbroch@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/216814
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Fix for plankton v2 so that the VBUS voltage selection buttons
work properly (5V, 12V, and 20V).
BUG=none
BRANCH=none
TEST=load onto plankton v2, connect type-C to samus, and press
5V, 12V, and 20V buttons. read adc on samus side to verify it
is getting the proper voltage.
Change-Id: I5004675bf658834219c295292c669182af7d8393
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/217258
Reviewed-by: Vic Yang <victoryang@chromium.org>
This ensures that nothing previously flashed to the baord can
interfere with the flashing operation (by wedging the MCU or
putting it into a state that the falshing code can't handle).
This also adds a dependency on ec.bin to the flash
target, ensuring that the firmware image is up to date
when flashing.
Signed-off-by: Anton Staaf <robotboy@chromium.org>
BRANCH=none
TEST=make buildall -j
Change-Id: I8cdfa6f5c84ed84d6b6e6b30d6683a23087f2c63
Reviewed-on: https://chromium-review.googlesource.com/215991
Tested-by: Anton Staaf <robotboy@chromium.org>
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
Commit-Queue: Anton Staaf <robotboy@chromium.org>
Change USB_MCU_RST gpio used to reset PD MCU to push-pull instead
of open drain.
BUG=none
BRANCH=none
TEST=tested on EVT samus by using gpioget/gpioset to make sure
we can actually reset the PD MCU from the EC.
Change-Id: Id8460fdb32bc32d0dd4c236f3050d241312dce23
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/216607
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
We switched which spi bus we were using for each type-C port EVT,
but missed one place where the busses should have been switched.
Note, this bug wasn't actually causing any problems because
we enable both spi busses at init time and they remain enabled.
BUG=none
BRANCH=none
TEST=load on EVT samus, make sure PD negotiation works on both
ports
Change-Id: I7b4fbee01b58be41521745d7bef6d9357e50be57
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/216606
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
This was inverted in the schematic, but is also connected to a FET
and is expected to be driven. However it is not working properly so
for now leave the GPIO as an input.
BUG=chrome-os-partner:31833
BRANCH=None
TEST=build and boot on samus EVT
Change-Id: I10d6a40b1102df866a9d32c52a9f67eb24c3ce7a
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/216942
Reviewed-by: Alec Berg <alecaberg@chromium.org>
When RTCRST is asserted the PCH is not able to sequence properly
right away. In testing 5ms was usually suitable but to be safe a
10ms delay is added.
BUG=chrome-os-partner:31833
BRANCH=None
TEST=esc+refresh+power on samus EVT boots to recovery
Change-Id: I10045fe56e107e853ff297bd83ea5369c44a2020
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/216941
Reviewed-by: Alec Berg <alecaberg@chromium.org>
This GPIO was reassigned and needs to be reflected properly. Since
it no longer exists we must also disable CONFIG_SWITCH_DEDICATED_RECOVERY
so it is not sampled to determine recovery state.
BUG=chrome-os-partner:31833
BRANCH=None
TEST=boot on samus EVT in non-recovery mode
Change-Id: I6e3b19956e4c8075a3f5cd4ec7e16bea934b1e98
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/216940
Reviewed-by: Alec Berg <alecaberg@chromium.org>
- Added LID_CLOSED_L and BASE_PRESET_L to PA2/PA3.
- Moved UART_TX/RX to PA9/PA10 (UART 1)
- Change DMA mapping to keep using DMA 4,5 for UART
BUG=chrome-os-partner:31527
TEST=None
BRANCH=ToT
Change-Id: Ie6138075bd901225b4fee48fc4ab4fa2add24b45
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/215131
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
There was a way to brick the PMIC by programming its registers with a bad
configuration, this could prevent the AP from powering up properly (thus not
being able to unbrick it). The PMIC retains register state through S5 (presumably
due to RTC business) and they do not get reset at bootup unless the OTP reset is
asserted.
The OTP reset actually has to be asserted in a special(rather long as well)
sequence.
A bug was discovered while making this change(crosbug.com/p/31635): usleep does
not work for long delays. Since I needed at least 300ms on one of the delays I
used a workaround with a loop.
I also cleaned up some old tegra stuff and renamed things to be more semantic.
BUG=None
BRANCH=None
TEST=From the AP set a PMIC register from the default value of 0x7d to 0xfd:
user@ap~$ modprobe i2c-dev
user@ap~$ i2cget -f -y 0 0x1b 0x24
Check what the default state is, mine was 0x7d
user@ap~$ i2cset -f -y 0 0x1b 0x24 0xfd #or change 0xfd to something!=default
Cold reboot the dut("apreset" or "power on\npower off" will work) then check if
the PMIC registers got reset:
user@ap~$ modprobe i2c-dev
user@ap~$ i2cget -f -y 0 0x1b 0x24
0x7d(or whatever your default state was) #good
0xfd #bad, did not reset properly
Using "user@ap~$ i2cset -f -y 0 0x1b 0x24 0x00" instead will prove the bricking
of the PMIC/AP.
Change-Id: Iad96781ffde085befe6dea20edd255ca3e7e1357
Signed-off-by: Alexandru M Stan <amstan@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/214360
Reviewed-by: Doug Anderson <dianders@chromium.org>
Change lid accel rotation matrix to orient lid accel to the base
accel.
BUG=none
BRANCH=none
TEST=Load onto samus, use accelread 0 and accelread 1 to make
sure lid and base accels match at a variety of locations.
Change-Id: I7a27f8e702c6c26ed671325183a87b52e5b3d06a
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/215944
Reviewed-by: Sheng-liang Song <ssl@chromium.org>
*** This breaks Plankton V1 support ***
This CL updates GPIO and PD configuration.
BUG=chrome-os-partner:31633
TEST=Build successfully. No board to test.
BRANCH=None
Change-Id: I9bbcde8aed15aa488e659a69dc87978532f33f13
Signed-off-by: Vic Yang <victoryang@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/214823
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Define SCL and SDA for I2C port 0 so that it is automatically unwedged
when it detects the bus has been wedged. Note, we can currently only
use this on one I2C port.
BUG=chrome-os-partner:31581
BRANCH=samus
TEST=load onto samus p2b that is having i2c port 0 problems and
wait for the bus to wedge, then verify it automatically unwedges:
[868.755442 I2C0 Addr:16 bad status 0x41, SCL=1, SDA=0]
[868.756013 I2C unwedge called with SDA held low]
Change-Id: I0ffb6a725af97155f734e2570574144ba4044f22
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/215396
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Hibernate is not supported on STM32F0. Disable system hibernate so that
the system doesn't auto-reboot after an hour in G3. This also benefits
us in terms of firmware size.
BUG=chrome-os-partner:31665
TEST=Boot on Ryu. Check 'hibdelay' and 'hibernate' commands are absent.
TEST=Boot Ryu from G3.
TEST=Change default hibernation delay to 1 second. Put system in G3.
Check it does not reboot.
BRANCH=None
Change-Id: Ia01d2d74bc5c22c01e29e5877bd4bd38ee7dddc8
Signed-off-by: Vic Yang <victoryang@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/214834
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Change the zinger software version returned by VDO_CMD_READ_INFO
to report the commit count portion of the version string to make
the software version automatically change. This software version
is important for debugging and is printed to PD console every time
a zinger is attached.
BUG=none
BRANCH=none
TEST=load onto zinger and samus, plug in zinger and see:
Dev:1 SW:2147 RW:0
compare to the version string in zinger binary and we see:
zinger_v1.1.2147-...
Change-Id: Ieafe89b4b16cee076be17bcbc6774bbd7fc24f8e
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/214428
Reviewed-by: Todd Broch <tbroch@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Every time a type-C source is plugged in, send a special VDM to
read device info. Device info will contain RW Hash (sha1), a
unique hardware descriptor (USB_PD_HARDWARE_DEVICE_ID), a
software version number just for debugging (USB_PD_DBG_SW_VERSION),
and a flag for if the device is in RW. This feature is off by
default and can be turned on by defining
CONFIG_USB_PD_READ_INFO_ON_CONNECT, currently defined for samus
and ryu only.
Renamed the read RW_HASH VDM to READ_INFO since it now returns
more than just the hash.
When device info is received, we store the RW hash. In the future
we will use this to check if device needs an update.
BUG=chrome-os-partner:31361
BRANCH=none
TEST=load onto a samus and a zinger. test when you attach zinger
we send a VDM, and we get device info printed to console. also
use "pd 0 hash" to query last hash received.
Change-Id: I0ca57651cf8506ea738b080a6cf8e7b020ef8724
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/213832
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Todd Broch <tbroch@chromium.org>
Add host event for PD up to AP. The PD toggles a gpio line to
EC causing an interrupt on EC. The EC then sends host command
down to PD MCU to get its status. There is a new status bit for
PD host event, so when EC see's the PD host event status bit,
it sends a PD host event to the AP.
There is currently only one host event for PD to AP.
BUG=chrome-os-partner:31361
BRANCH=none
TEST=added PD console command pdevent, which initiates the host
event. when sent, verified on EC that it sets the correct host
event bit using hostevent console command
Change-Id: If1a59a3232e2f9a49f272c6dee5319254d87b9a9
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/213371
Reviewed-by: Randall Spangler <rspangler@chromium.org>
As a short term workaround for the I2C problem of PI3USB9281, we're
gating its SCL input when it's not addressed. This workaround will be
removed once we have the silicon fix.
BUG=chrome-os-partner:31526
TEST=Sanity check on P0 boards.
BRANCH=None
Change-Id: I57daf25f2ad2d94ac7e4192050b4d6bbdae9d51d
Signed-off-by: Vic Yang <victoryang@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/214064
Reviewed-by: Randall Spangler <rspangler@chromium.org>
The servo and the EC both output on the WARM_RESET line. Servo is open drain but
the EC was not. This caused a short whenever the servo tried to assert the
reset. The button still worked because the button is a lot stronger at pulling
down than the servo gpio.
Changing the WARM_RESET EC pin to open drain is an easy fix to this problem
without changing the hardware.
BRANCH=None
BUG=None
TEST=Warm reset via servo command should work. Warm reset button on servo always worked.
Change-Id: Ib615bc438a5726e40b0b502a197a57dbea6ee780
Signed-off-by: Alexandru M Stan <amstan@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/213666
Reviewed-by: Dexter Yeh <dyeh@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Changed accelerometer orientation data to calculate correct
lid angle.
BUG=chrome-os-partner:27313
BRANCH=none
TEST=used "lidangle on" from ec console to print lid angle
and verified correct lid angle as I opened and closed lid.
Change-Id: If5f26ebe1b81449fe09741894a342a4a29e177e3
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/214101
Reviewed-by: Sheng-liang Song <ssl@chromium.org>
