The ANX7447 has a sink/source control lines which can be connected to
a PPC. The NX20P3483 PPC requires this control to set it's sink/source
switch control. The ANX7447 contols these lines via the tcpci COMMAND
register. This CL adds new tcpm_set functions to set either SNK or SRC
control via the COMMAND register.
BUG=b:77583452
BRANCH=NONE
TEST=Tested on port 0 of Yorp with an external charger. Prior to this
CL the PPC would remain in standby state because both snk/src control
remained low. With these changes, verifed that snk_ctrl is driven high
and vbus_sink_enable() function no longer returns an error.
Change-Id: Icbea0d3edb63ad19f3d2c76636208497b6939a72
Signed-off-by: Scott Collyer <scollyer@google.com>
Reviewed-on: https://chromium-review.googlesource.com/996239
Commit-Ready: Scott Collyer <scollyer@chromium.org>
Tested-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Jett Rink <jettrink@chromium.org>
It is important for the OS to be able to find out the state of CCD and
current capabilities settings of the device.
This patch defines a structure to use to report information about CCD
state from Cr50 to the host and adds a CCD vendor subcommand to allow
to retrieve the information from Cr50.
Some structure and variable definitions had to be moved into the .h
file to make it possible to share them between Cr50 and gsctool.
BRANCH=cr50, cr50-mp
BUG=b:72718383
TEST=with the following patch applied verified that CCD info is
properly reported. Also verified that other CCD subcommands still
work as advertised.
Change-Id: I4a783e6817ed364b9e64522ebbe968d4a657a84c
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/999825
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Port 0 uses the Anx7447. This CL updates the tcpc config to use the
Anx7447 driver instead of the Anx74xx driver.
BUG=b:74127309
BRANCH=NONE
TEST=make -j BOARD=yorp and verified that when connected external type
C charger to port 0 it reaches SNK_READY
Change-Id: I96967a1d272fcda079280ba6d2f0eb5ed8e3dd7f
Signed-off-by: Scott Collyer <scollyer@google.com>
Reviewed-on: https://chromium-review.googlesource.com/982894
Commit-Ready: Scott Collyer <scollyer@chromium.org>
Tested-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Jett Rink <jettrink@chromium.org>
This patch adds execution-in-ram, opposite of XIP: execution-in-place
(a.k.a. XIP) to the EC features. It can be currently implied by
CONFIG_EXTERNAL_STORAGE.
BUG=b:77306460
BRANCH=none
TEST=Verify ectool prints EXEC_IN_RAM on Fizz.
Change-Id: I4a7fb3b267864debe59fd211956371eceac57613
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/995968
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Use RMA public key definition generated based on the binary blob
containing the key and key ID.
Key generation is controlled by the make file in common/, but actual
key blob comes from the board directory.
The structure holding the key and key ID is being modified to allow
initialization using a flat array.
No more need in defining CONFIG_RMA_AUTH_SERVER_PUBLIC_KEY and
CONFIG_RMA_AUTH_SERVER_KEY_ID.
BRANCH=cr50, cr50-mp
BUG=b:73296144, b:74100307
TEST='make buildall' still succeeds.
test RMA server generated authentication codes are accepted when
unlocking RMA.
Change-Id: I8ade94de6eb69b3e49bc5b948dbac20e59962acf
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/990783
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
The semantics in the EC code base are that CONFIG_INTERNAL_STORAGE
implies eXecute-In-Place semantics (XIP). Add a comment to make that
abundantly clear.
BUG=none
BRANCH=none
TEST=none
Change-Id: I80152eeb41dd35716f4c09ffd1753ae128aa7d2d
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/995956
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Majority of the chipsets do not have a dedicated GPIO to trigger
AP cold reset. Current code either ignores cold reset or does a warm
reset instead or have a work around to put AP in S5 and then bring
back to S0. In order to avoid the confusion, removed the cold reset
logic and only apreset is used hence forth.
BUG=b:72426192
BRANCH=none
TEST=make buildall -j
Manually tested on GLKRVP, apreset EC command can reset AP.
Change-Id: Ie32d34f2f327ff1b61b32a4d874250dce024cf35
Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/991052
Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Jett Rink <jettrink@chromium.org>
This is a specific option for it83xx chip and is used to
include EC2I module.
And we won't need it without LPC module enabled, so just
depend on CONFIG_LPC.
BUG=none
BRANCH=none
TEST=make buildall -j, boot to kernel on reef_it8320.
Change-Id: I1aa4a182e94d802dbf9ca19cc4a47ef9542d74a7
Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
Reviewed-on: https://chromium-review.googlesource.com/987674
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Tell the base to hibernate when we are in S5, and no AC is connected.
Also, wake the base when AC status changes (S5), and when the system
transistions out of S5.
BRANCH=none
BUG=b:71874971
TEST=1. Lid EC console: apshutdown => Check that Base EC hibernates
2.a. Lid EC console: powerb; => Check that base reconnects
2.b. Connect/disconnect adapter: check that base disconnects
and reconnects
Change-Id: I5e9a4afc64a07ad92f37d171a78a914d26f07c8e
Signed-off-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/958814
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Allows the lid to hibernate the base.
BRANCH=none
BUG=b:71874971
TEST=With following change, lid hibernates the base when in S5,
and no AC is connected.
Change-Id: I8c8017d638442ba8b17c8117d0b1b31f3538925f
Signed-off-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/981914
Reviewed-by: Randall Spangler <rspangler@chromium.org>
No one is using this method and it implies that all chipset should
support the RCIN# Virtual Wire if using eSPI. Only large core chips
use RCIN#; small core chips don't.
This method was introduced for skylake and has since been replaced
since CL:575947 was merged.
BRANCH=none
BUG=none
TEST=build all
Change-Id: Ic541e3d61d1e0ecc64a0bb12385bdada40f0acf2
Signed-off-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/975904
We have a growing list of boards in chip/npcx/system.c that are
unable to distinguish a reset from a power-on or a reset-pin type.
Instead of being a temporary issue this is now solidified in the
design on some kabylake boards.
Instead of defining board-specific checks in the chip code this
change adds a config option that the relevant boards can define.
BUG=b:76232539
BRANCH=none
TEST=make -j buildall passes
Change-Id: I76e0f011d70ce6f778b1fb6a56c2779c39c3cbd6
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://chromium-review.googlesource.com/979575
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
The keyboards that have an assistant key also move the row that
the refresh key is on from 2 to 3. The row is hardcoded and
used by the early boot key detection code to determine if
boot keys should be honored.
The fallout from not having the right refresh row defined was
not seen on Eve because that board has a different quirk where
it does not distinguish reset-pin vs power-on reset types so
the test in check_boot_keys() was not failing.
BUG=b:76232955
BRANCH=none
TEST=manual testing on Eve board
Change-Id: I5b94b4e32024afa1768bdf371a7eb951753014e8
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://chromium-review.googlesource.com/979574
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Since all of the uses of CONFIG_USB_PD_TCPM_ANX74XX are actually for
ANX3429, rename the option especially since the ANX7447
driver will not reuse the ANX74XX driver which is being introduced
in CL:956790.
Also adding the CONFIG_USB_PD_TCPM_ANX740X and
CONFIG_USB_PD_TCPM_ANX741X options to advertise which versions of the
ANX chip the anx74xx.c driver applies to.
BRANCH=none
BUG=chromium:824208
TEST=build all
Change-Id: Ib47f4661466e54ff2a0c52d517eb318d3bfd25a2
Signed-off-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/973558
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
The NX20P3483 is a USB PD and Type C high voltage sink/source combo
switch. This CL adds support for this PPC variant. Unlike the TI
SN5S330, the NX20P3483 does not support VCONN and does not need to be
informed of CC polarity by the TCPM. To account for these differences,
2 new PPC config options are added and the driver for the TI SN5S330
was modified to include these new options.
The SNK/SRC switch mode for the NX20P3483 is controlled by 2 GPIO
signals which may be connected the EC or directly to the TCPC. To
handle both cases, the ppc_chips structure was modified with a flags,
snk_gpio, and src_gpio elements.
BUG=b:74206647
BRANCH=none
TEST=make -j buildall and verified there are no build errors.
Change-Id: Ic4415ab7571b80e7661ea673434eaf4cf1f1fd2d
Signed-off-by: Scott Collyer <scollyer@google.com>
Reviewed-on: https://chromium-review.googlesource.com/966926
Commit-Ready: Scott Collyer <scollyer@chromium.org>
Tested-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
This change adds a new config option CONFIG_I2C_XFER_CALLBACK that
makes i2c_xfer callback into board-provided functions before the start
and after the end of every I2C transaction. This can be used by boards
to implement any I2C device-specific quirks e.g. requiring minimum
bus-free time between every I2C transaction when the slave device
cannot actually do clock stretching.
BUG=b:73147310
BRANCH=None
TEST=make -j buildall
Change-Id: I452de4f22a81ffd97ca4944e1b940a3537637df9
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://chromium-review.googlesource.com/956934
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Geminilake uses the same power sequencing code as Apollolake. Instead
of the board specifying the wrong chipset, we will make the correct
chipset reuse the existing power code.
This also gives us flexibility in the future if GLK needs to vary from
ALK in any of shared code.
BRANCH=none
BUG=b:74020444
TEST=build all
Change-Id: Icd00286ac4f0612d1bda56677c4141957480c6bf
Signed-off-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/969613
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Add the state machine and the interfacing to the enrollment and matching
algorithm providing by the private driver part.
Implement the host commands interface for it (based on MKBP event) along
with the console debug commands to exercise it.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=none
BUG=b:72360575
TEST=On ZerbleBarn console, use 'fpenroll' then 'fpmatch' for several
fingers.
TEST=With ZerbleBarn and a servo-v2, retrieve and upload templates with
'ectool_servo fptemplate'.
TEST=On Meowth, exercise with the prototype of biod
CrosFpBiometricsManager.
CQ-DEPEND=CL:*555078
Change-Id: I10b0d76d3faa898a682cf9a2eb7fc7e212b0c20c
Reviewed-on: https://chromium-review.googlesource.com/886401
Commit-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
Add error code to indicate a piece of hardware is not working properly.
BUG=none
TEST=compile
BRANCH=none
Change-Id: I34eca8073a359aec1c559241654a1d0a7075cd44
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/753968
This CL introduces /baseboard to the EC project which can contain
config options and code which is specific to certain family, but can
be shared among the board derivatives of that family. Only the
infrastructure changes are included with an empty baseboard.c/.h for
octopus.
BRANCH=none
BUG=b:74358864
TEST='make buildall' and ensure that all boards build successfully. In
addition, temporarily moved config options for USB-C and charger to
baseboard.h and tested that 'make BOARD=yorp' is successful.
Change-Id: I16656574f835c56598a9d2bf49bc1e946d71fe76
Signed-off-by: Scott Collyer <scollyer@google.com>
Reviewed-on: https://chromium-review.googlesource.com/954444
Commit-Ready: Scott Collyer <scollyer@chromium.org>
Tested-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Instead getting the time for each sample in the task code, we should be
getting it as soon as the sensor reported it added it to its fifo (so
sensor just finished integration).
Because of that each sensor should provide the time when it provides a
sample, ideally from an accurate spot like an interrupt.
Deprecate motion_sense_fifo_add_unit (without a timestamp) in favour of
motion_sense_fifo_add_data (which adds the timestamps). Update all
relevant sensors to use the new api.
Note: for now I focused on the BMI160, where I actually made it get the
time in the interrupt. The other sensors were made to use the new api,
but still don't record the time in the right place (though it's not any
worse than before).
BUG=b:67743747
TEST=In the kernel, fifo_info->info.timestamp still has sane values.
TEST=CTS should still pass
BRANCH=master
Change-Id: I9829343f8702e00cc19f9c88134fa1f258c9e1e9
Signed-off-by: Alexandru M Stan <amstan@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/807331
Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com>
Reviewed-by: Gwendal Grignou <gwendal@chromium.org>
yorp measures each port's vbus separately on a deticated ADC.
Also, add config to take care of ADV_VBUS -1 case too.
BRANCH=none
BUG=b:74127309
TEST=none
Change-Id: I6f4df96caffc3b527b69e67358631dd448172cde
Signed-off-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/956555
Reviewed-by: Edward Hill <ecgh@chromium.org>
To prevent invalid timestamping, call load_fifo only when we get a FIFO
interrupt.
In consequence, remove load_fifo entry point and only process fifo
inside the IRQ.
Add helper function to know when we are in forced mode (the EC needs to
periodically read sensor data or interrupt driven).
BUG=b:73557414
BRANCH=master
TEST=compile
Change-Id: I959e476f3f7215be95424c07223f7421e8b13da1
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/938146
Commit-Ready: Alexandru M Stan <amstan@chromium.org>
Tested-by: Alexandru M Stan <amstan@chromium.org>
Reviewed-by: Alexandru M Stan <amstan@chromium.org>
Without this patch, requesting 100mA or output current would be
rounded down to zero.
This would also cause other issues when doing base/lid and lid/base
power transfers on lux/wand, as the input current has a much finer
grain control, which could lead the input charger to brown out
the output charger.
BRANCH=none
BUG=b:67920792
TEST=Flash lux/wand, lux can provide as little as 100mA of current
successfully.
Change-Id: Ibf170a6ee3c2dfbdbbc03948c3b0e6ab878eee47
Signed-off-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/956660
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
list/add_activities should be include even when FIFO support is not
compiled it, when the host is not asking for them, as it is needed for
double tap support.
BUG=b:73546254
BRANCH=master
TEST=Compile when just CONFIG_GESTURE_DETECTION is defined.
Change-Id: Icec7ccec7fd8463ea40afbe05ce1e177ae7d609d
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/924404
Commit-Ready: Gwendal Grignou <gwendal@google.com>
Tested-by: Gwendal Grignou <gwendal@google.com>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Gwendal Grignou <gwendal@google.com>
This patch splits struct fan_t into two parts: base configuration
and RPM configuration. RPMs are expected to be different from
model to model while a base configuration is most likely shared.
BUG=b:73720175
BRANCH=none
TEST=make buildall
Change-Id: Iff17573f110e07e88d097dd848cf91ee98b83176
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/949382
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
When a chip has special/non-contiguous SRAM physical memory region,
rather than extending the generic linker file ad nauseam, define a
mechanism to declare a chip specific list of those regions.
To do so, a chip must declare the CONFIG_CHIP_MEMORY_REGIONS
configuration and have a memory_regions.inc with the list of regions.
The special-purpose preprocessed chip/<chip_name>/memory_regions.inc
file has one region declaration per line using the following macro:
REGION(name, attributes, start_address, size)
Each region will get a proper MEMORY entry and a section in the linker
file.
the __SECTION(region_name) helper is provided as a convenience to
declare variable in a specific region.
Note: those 'special' regions are NOT cleared at startup contrary to
.bss.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=none
BUG=b:67081508
TEST=on ZerbleBarn, along with the following CLs, run the firmware with
large arrays in special AHB memory regions.
Change-Id: I3f156ef6e5feb4a6a0b2ae2468bae8a20483f17c
Reviewed-on: https://chromium-review.googlesource.com/946368
Commit-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Make it clearer what the new key is about.
CONFIG_KEYBOARD_NEW_KEY to CONFIG_KEYBOARD_ASSISTANT_KEY.
BRANCH=none
BUG=none
TEST=make buildall -j
Change-Id: Ic2db425b40ff8bc612626b6f644463b1f8ec630e
Signed-off-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/950263
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Cr50 lacks native instructions for 64-bit integers and an ABI
function can be used by the compiler to take the place of the
needed instructions. This CL adds support for a right bitwise
shift of 64-bit integers.
BRANCH=none
BUG=chromium:794010
TEST=Set CONFIG_LLSR_TEST, build, update cr50, and run llsrtest
on the console.
Change-Id: Iae66c86720c531454ba29f15b3cc6a07959f5ef2
Signed-off-by: Allen Webb <allenwebb@google.com>
Reviewed-on: https://chromium-review.googlesource.com/931932
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Add a new module ID 'MODULE_FAST_CPU'.
When it is enabled with clock_enable_module(MODULE_FAST_CPU, 1), switch
the system clocking to the fast 400-Mhz PLL.
For now, I consider that a single task/user is calling
clock_enable_module(MODULE_FAST_CPU, x), so we don't need to count users
(in a complicated atomic fashion). It's good enough for the current
use-case and we can add the complexity later if we have a real need.
BRANCH=none
BUG=b:67081508
TEST=on ZerbleBarn, with follow-up CL setting
clock_enable_module(MODULE_FAST_CPU,x) around the computation block,
see that computations are fast and the clock goes back to HSI after.
Change-Id: I2aef3ad673ddbffd6fc64c591c54297e94896fa6
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/945688
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
The ARMv7-M ISA defines standard (and optional) mechanism to manage the
CPU caches through the SCB (System Control Block) registers.
So far, only the Cortex-M7 core implements such as a mechanism (e.g. the
Cortex-M4 with caches we have are using a proprietary mechanism for the
management).
Define the functions to use the I-Cache,
and enable them on STM32H7 which is our only supported Cortex-M7 core.
The D-Cache mechanism is still To Be Done, as it involves a bit more
support in the firmware for the DMA memory areas.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=none
BUG=b:67081508
TEST=on ZerbleBarn, verify manually that the 'IC' bit is set in the CCR
(e.g. 'rw 0xe000ed14' returns 0x60218), and runs some CPU workload
without crash and with a speed-up.
Change-Id: I6af1021d65048b787630387f7d95797db15d069c
Reviewed-on: https://chromium-review.googlesource.com/943445
Commit-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
This CL adds the driver support for the WoV module which inludes the
following files:
- wov.c
- wov_chip.h
- apm.c
- apm_chip.h
It also supports the console commad "wov" which can test different
configuration and audio quality by entering different parameters.
The detail description of WoV console command is listed below:
------------------------------------------------------------------------
[Note]: Before changing any of settings, please make sure the operation
mode is on the "OFF" state. (ie. run the command wov cfgmod off
first) .
> wov init
Initialize WoV interface, including pin mux and interrupt
registration etc.
> wov mute <enable / disable >
mute enable / disable.
> wov cfgsrc <mono | stereo | left | right>
set audio source, ex: wov cfgsrc left, means audio source from left
MIC.
> wov cfgbis <16|18|20|24>
set audio resolution, ex: wov cfgbit 16 means audio resolution are
16bits.
> wov cfgsfs <8000|12000|16000|24000|32000|48000>
set audio sampling frequency rate, ex: wov cfgsfs 48000 means audio
sampling rate are 48Khz.
> wov cfgbck <32fs|48fs|64fs|128fs|256fs>
set I2S bit clock rate, ex: wov cfgsfs 48000 and wov cfgbck 32fs
means audio sampling rate are 1536Khz (32*48000).
> wov cfgfmt <i2s|right|left|pcma|pcmb|tdm>
set I2S but format, ex: wov cfgfmt right means audio I2S format are
Right-Justify.
> wov cfgmod <off|vad|ram|i2s|rami2s>
set audio operation mode ,ex: wov cfgmod i2s means audio output via
I2S bus.
> wov cfgtdm <0~496 0~496 0~3>
set TDM time slot, the first values is left channel delay counter,
the second is right channel, and the 3rd is startup counting condition.
(chosen LRCK raising or falling edge) .
[Note: this command is just working on cfgmod equal to tdm]
> wov cfgget
retrieve above settings.
> wov vadsens
(currently not support, reserve for next version)
> wov gain (0~31)
set audio data gain value, ex: wov gain 10 means setting audio digital
gain are 10dB.
> wov cfgdck <1.0 | 2.4 | 3.0 >
set digital MIC PDM clock rate. ex: wov cfgdck 2.4 means PDM clock
are 2.4Mhz.
-----------------------------------------------------------------------
This CL also adds the chip ID (0x24) for npcx7m7w. So the console
command "version" can show the chip is npcx7m7w.
BRANCH=none
BUG=none
TEST=No build errors for make buildall.
TEST="BOARD=npcx7_evb make"; Flash the image on EVB; Test WoV function
with console commands described above.
Change-Id: Ief2b3e89edbd3e6d2a9d82d317a93c9f0b7a20cd
Signed-off-by: Dror Goldstein <dror.goldstein@nuvoton.com>
Signed-off-by: Simon Liang <CMLiang@nuvoton.com>
Signed-off-by: CHLin <CHLIN56@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/897314
Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com>
Tested-by: CH Lin <chlin56@nuvoton.com>
Reviewed-by: Scott Collyer <scollyer@chromium.org>
This patch makes EC firmware and cbi-util share the common code.
BUG=b:70294260
BRANCH=none
TEST=Set fields using ectool. Verify the contents by cbi command.
Verify cbi-util creates the same binary as before.
Verify emerge ec-utils ec-devutils pass.
Change-Id: If5e65e48dd03960e0adf23ef775f67aecf785d85
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/932001
When running the spihash command using gsctool (as opposed to the
running it from the Cr50 console), the operator needs to be prompted
when the PP button needs to be pressed.
This patch extends spihash command implementation by adding a new
subcommand for polling physical presence.
BRANCH=cr50, cr50-mp
BUG=b:73668125
TEST=with the appropriate gsctool changes the user is periodically
prompted to press the physical presence button, and eventually it
is possible to set up spi hash access to AP and EC.
Change-Id: I96aed1619d364c80a2f35ca8dc41241f1a444103
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/930568
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Various parts of Cr50 code and Cr50 related utilities duplicate
definition of __packed available in include/common.h. Let's use the
same definition everywhere.
BRANCH=cr50, cr50-mp
BUG=none
TEST=make buildall succeeds
verified that linker generated map files for Cr50 RW are the same
before and after this change.
built and used gsctoo and rma_reset
Change-Id: Ib91f9bbad1f6822b347f32b393630f592df80d60
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/931929
Reviewed-by: Randall Spangler <rspangler@chromium.org>
BUG=chromium:803955
BRANCH=none
TEST=Verify counters are printed every hour and before sysjump as follows:
[12.540051 HC Suppressed: 0x97=25 0x98=0 0x115=0]
Change-Id: I1c1aecf316d233f967f1d2f6ee6c9c16cc59bece
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/912150
Currently CBI data offset and size are fixed. This patch makes them
variable. Each data item consists of <tag><size><value> where <tag>
is a numeric value assigned to each data item, <size> is the number
of bytes used for <value>.
BUG=b:70294260
BRANCH=none
TEST=Use 'ectool cbi set' to set board version, oem, sku.
Verify the contents by cbi console command and ectool cbi get.
1. ectool cbi set 0 0x202 2 2 (Init CBI and write board ver. of size 2)
2. ectool cbi set 1 1 1 (write oem id of size 1)
3. ectool cbi set 2 2 1 (write sku id of size 1)
4. ectool cbi get 0
514 (0x202)
5. ectool cbi get 1
1 (0x1)
6. ectool cbi get 2
2 (0x2)
7. Run cbi console command:
CBI_VERSION: 0x0000
TOTAL_SIZE: 18
BOARD_VERSION: 514 (0x202)
OEM_ID: 1 (0x1)
SKU_ID: 2 (0x2)
43 42 49 8c 00 00 12 00 00 02 02 02 01 01 01 02
01 02
Change-Id: I5a30a4076e3eb448f4808d2af8ec4ef4c016ae5e
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/920905
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
