Relying on the AP sending a PCR read as an indication of the completed
boot process does not work on the resume path. Let's just enable
commits 3 s after they were stopped to process tpm reset.
BRANCH=none
BUG=chrome-os-partner:61795
TEST=observed the following on the cr50 console on a reef during reboot:
[0.018692 tpm_init]
tpm_manufactured: manufactured
[0.021180 tpm_reset_now: done]
.
.
[1.166496 Skipping commit]
[1.425888 Skipping commit]
[1.439112 Skipping commit]
.
.
[3.021892 Committing NVMEM changes.]
and verified that reef booted normally.
Change-Id: I5f64fe24b961a9d0366f8e4f40a0e44d4e7263fa
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/427328
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
These pins should be moved to AP in a later HW revision, keep them
always active for now. Also, leave CAM_PMIC_RST_L as input as
there is an internal pull-up in the PMIC, and driving it high
breaks WLAN+LTE.
BRANCH=none
BUG=chrome-os-partner:61098
TEST=ectool gpioget: Both signals are high
Change-Id: I66115daec57ca4d89c1c664e6b35825b20fa0c1a
Reviewed-on: https://chromium-review.googlesource.com/427743
Commit-Ready: Nicolas Boichat <drinkcat@chromium.org>
Tested-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Specifically, we are using a bit to disable the
SMI pulse on x86 systems so that we can use the
power button for menu selection.
BUG=chrome-os-partner:61275
BRANCH=None
TEST=Try running with depthcharge sending the host command
during detachable FW menus and making sure power
button select doesn't turn off device on reef.
Change-Id: I4a68cf514d514a4abe98beb99e7934d6fb0f44bd
Signed-off-by: Shelley Chen <shchen@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/427413
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
When the EC does a sysjump it redoes the PD negotiation. This changes
the voltage levels on the CC lines. Debounce the rdd disconnect signal
for 2 seconds so cr50 will ignore the negotiation and keep CCD enabled.
BUG=chrome-os-partner:60924
BRANCH=none
TEST=connect suzyq. Make sure usb does not drop out during a EC sysjump
or reboot.
Change-Id: I95b9bc81f736e3b7a65103817c140874b1ed34ec
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/426398
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
A valid charge port is always detected as VBUS supplier type, 'USB charger'
can detect the same port as BC1.2 DCP supplier type & also 'TCPC' can
detect the same port as TYPEC supplier type. Thus a valid port is detected
as 2 or 3 supplier types. Depending on the supplier's priority and the
power that the supplier can provide, charge manager choses the charge
supplier type of the port.
If the USB charger detected supplier is BC1.2 DCP and the TCPC detected
supplier is TYPEC then the supplier can provide stable current from TYPEC
supplier's advertised current hence start ramping from TYPEC supplier's
advertised current.
BUG=chrome-os-partner:61420
BRANCH=none
TEST=Manually tested on reef. Donette bottom port can switch
from 1.5A to 3A upon high load.
Change-Id: I871eca3ae4041f00bb3fd50e6aa939643f30a1f2
Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/427961
Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
Use the 'echo' command to suppress unwanted build output when V=0.
Signed-off-by: Simon Glass <sjg@chromium.org>
BUG=chromium:680243
BRANCH=none
TEST=V=0 emerge-reef chromeos-ec; See that the tpm output is gone
Change-Id: Ia742b0b5270b969ec4f51967810e616348e39dbd
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/427365
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Add a 'echo' command which can be called to generate output. If V=0 then
it is suppressed. This drops the unwanted output when V=0.
Signed-off-by: Simon Glass <sjg@chromium.org>
BUG=chromium:680243
BRANCH=none
TEST=V=0 emerge-reef chromeos-ec; See that the BUILD lines are gone
Change-Id: Ie4474024c84345d427f4d95a9ff194dc740f860f
Reviewed-on: https://chromium-review.googlesource.com/427364
Commit-Ready: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
At present the EC Makefile supports two levels of verbosity:
V unset: Show an abbreviated build log (operation and file only)
V=1: Show the full build log, including all commands
However, even the abbreviated build log includes a lot of output. It is
basically a long list of filenames and is of little use during
development. It is more useful to show just warnings and errors.
Add a new setting, V=0, which provides this.
BUG=chromium:680243
BRANCH=none
TEST=emerge-reef chromeos-ec; test each of V=, V=0, V=1 and see that the
Makefile does the correct thing.
Change-Id: I85c0423c5299fa3ab624ed9f7f7b6b7f73236611
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/427363
Reviewed-by: Randall Spangler <rspangler@chromium.org>
BRANCH=reef
BUG=chrome-os-partner:61849
TEST=1. DC mode, enter battery cutoff.
2. After system shutdown, wait 10sec.
3. Plug in AC to check system power on.
Change-Id: I5f4cf023fa70cff42c2d1cc888b1d2ee39226af4
Signed-off-by: David Huang <David.Huang@quantatw.com>
Reviewed-on: https://chromium-review.googlesource.com/427441
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Detachable devices need firmware help to process battery disconnect
requests promptly.
The request happens when the user keeps pressed both power and "volume
up" buttons and yanks the charger cable.
Once this condition is detected a 5 s timeout is started, and if the
charger cable is not plugged back in during this interval, the code
initiates a low polarity pulse on both EC_RST_L and BAT_EN outputs.
Lowering BAT_EN level will cause the battery cut off which is supposed
to cause an immediate system power down.
BRANCH=none
BUG=chrome-os-partner:59833
TEST=verified desired behavior on an H1 dev board with a H1B2-D chip.
Change-Id: Iecdcc93e228f4bc18734569bd896b0afa4bb752a
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/426345
Reviewed-by: Marius Schilder <mschilder@chromium.org>
There are three different H1 B2 chips SKUs in the wild now, one
version is for clamshell Chromebooks, one is for experimental build of
Poppy and one for detachable devices.
The SKUs differ by some fuse settings, as outlined by the comment in
the code.
This patch maps fuse settings into the chip revision string and also
makes sure that the revision is determined once and then used for all
following invocations of system_get_chip_revision().
BRANCH=none
BUG=chrome-os-partner:59833
TEST=verified that on dev boards with three different H1 B2 SKUs the
revision is reported as expected (B2-C, B2-D and B2-P).
Change-Id: I7d588d7326c28e9fa4921351254ad60a21c3f6b8
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/426344
Reviewed-by: Marius Schilder <mschilder@chromium.org>
Reviewed-by: Carl Hamilton <carlh@chromium.org>
Add CONFIG_CHARGER_PROFILE_OVERRIDE, and it can check battery state
to set charge or discharge between battery capacity 95-100%.
BUG=chrome-os-partner:61767,chrome-os-partner:57571
BRANCH=reef
TEST=check unit can charge to 100%, then discharge to 95%, then
swich to charge until 100%. Loop charge and discharge between
95-100%.
Change-Id: I4f68e5a2d51e26f62ed7f6bd6ae7af061225f8cb
Signed-off-by: Bruce.Wan <Bruce.Wan@quantatw.com>
Reviewed-on: https://chromium-review.googlesource.com/426444
Commit-Ready: Keith Tzeng <keith.tzeng@quantatw.com>
Tested-by: Keith Tzeng <keith.tzeng@quantatw.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Workaround to Pyro DVT system can not power on when system at G3 state.
Hardware has leakage with LID_OPEN pin to touch control board if system
turns off PP3300 power rail, so enable CONFIG_POWER_BUTTON_IGNORE_LID
on temporarily.
BRANCH=reef
BUG=chrome-os-partner:61707,chrome-os-partner:61696
TEST=Manual.
Verify power button can power on system on pyro DVT touch sku.
Change-Id: I23608ae508ca419cecc3642d36eeee089a870778
Signed-off-by: Devin Lu <Devin.Lu@quantatw.com>
Reviewed-on: https://chromium-review.googlesource.com/426309
Commit-Ready: Keith Tzeng <keith.tzeng@quantatw.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* Rename PRIVATE_HOST_COMMAND_VALUE to EC_PRIVATE_HOST_COMMAND_VALUE to
make it clear it is part of EC and reduce the likelihood of collisions.
* Move PRIVATE_HOST_COMMAND_VALUE macro to ec_commands.h. This reduces the
transitive dependencies required to determine the value of a private host
command. This is beneficial for code outside of the ChromiumOS build
environment that needs to send private commands to an EC.
* Define DECLARE_PRIVATE_HOST_COMMAND when there is no host command task.
This will prevent builds with private commands from failing when the host
command task is not configured.
BUG=chromium:570895
BRANCH=none
TEST=make -j buildall
Change-Id: Iad938cb6a1521b65e4f893439d592ef375caace9
Reviewed-on: https://chromium-review.googlesource.com/426737
Commit-Ready: Carl Hamilton <carlh@chromium.org>
Tested-by: Carl Hamilton <carlh@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
Very similar to CL:424846, enable sensor FIFO, accel interrupt.
BUG=chrome-os-partner:61098
TEST=Not test on actual hardware.
BRANCH=none
Change-Id: Ie5c7304fcc00919cce62ed47a548104e8d0ac454
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/426880
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
Fix cros_workon_make --board eve chromeos-ec --install
The test phase would fail at compilation because TASK_ID_MOTIONSENSE
is not defined.
BUG=chromium:61748
TEST=Check that with the change cros_workon_make pass.
BRANCH=none
Change-Id: Ib50aad492e9cfb38c56a3c6c8d4f2bb2b297ea85
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/426879
Tested-by: Todd Broch <tbroch@chromium.org>
Reviewed-by: Todd Broch <tbroch@chromium.org>
Callers may not need computation of the public key.
Making this optional speeds this routine up.
Cr50 never passes in NULL for any argument, so is not affected.
BUG=none
TEST=build
BRANCH=none
Change-Id: Ia0077a35064f53b53f51867254aaa51eac6c55d8
Reviewed-on: https://chromium-review.googlesource.com/427058
Reviewed-by: Marius Schilder <mschilder@chromium.org>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Tested-by: Marius Schilder <mschilder@chromium.org>
We don't need to loop and waiting ADC's data valid flag
after the change was made.
Signed-off-by: Dino Li <dino.li@ite.com.tw>
BRANCH=none
BUG=none
TEST=1. We build a EC binary for PD EVB (declared two ADC channels
for VBUS measurement of PD task and priority is highest)
2. Use console command "adc" continually to read ADC channels
and check if any error.
Change-Id: I1379e0b4c9ef721c29cb053d7d85e1a8ece9471b
Reviewed-on: https://chromium-review.googlesource.com/421307
Commit-Ready: Dino Li <Dino.Li@ite.com.tw>
Tested-by: Dino Li <Dino.Li@ite.com.tw>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
When depthcharge invokes a Host command that needs EC to access
flash, the response is delayed by approx 150 ms because EC is
busy with another flash operation to determine size of RW image
for computing hash. We can eliminate this delay and also speed up the
flash operation by using the same mechanism that is used for mec1322
based designs which also use external SPI flash.
The changes are:
a) We access 4 bytes from SPI flash at a time instead of a single byte
b) We split flash accesses into smaller parts which means that mutex lock
is acquired for a short duration.
BUG=chrome-os-partner:59875
BRANCH=none
TEST=make buildall -j
After sysjump to RW, in EC Log the "hash start" is printed approx
120 ms earlier.
Change-Id: Icb633379c992e795ba40eaf54fe9ec31747d4be6
Signed-off-by: Shamile Khan <shamile.khan@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/426016
Reviewed-by: Shawn N <shawnn@chromium.org>
We have hard timing requirements once we begin to output our host
command response, and most of the time is spent copying our response to
OBUF. Optimize our copy loops to remove needless increments and to avoid
needless struct dereference.
BUG=chrome-os-partner:61304
BRANCH=gru
TEST=Manual on kevin, verify the following performance metrics:
Time spent in shi_fill_out_status(): Was 40us, now 28us
Time spent in shi_write_half_obuf(): Was 60us, now 31us
Time spent in shi_write_first_pkg_outbuf:
Was 90us, now 37us (bad case)
Was 26us, now 16us (better case / less data copied)
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: I04075c92744eeefe8f2be009e6598718c45143c4
Reviewed-on: https://chromium-review.googlesource.com/425330
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
Follow reef setting.
This patch changes the entry/exit model for S0ix from a PCH
SLP_S0 signal based model to a hybrid host event/direct interrupt
model. The kernel will send host events on kernel freeze/thaw exit;
EC will initiate the S0ix entry based on host command and exit via
another host command from kernel.
The assertion of SLP_S0 comes later than HC(suspend) and deasserion
of SLP_S0 comes earlier than HC(resume).
________ ________
SLP_S0 |______________________|
_____ ________
HC |___________________________|
BUG=none
BRANCH=reef
TEST=make buildall
Change-Id: I1073b5cb2cbb8492cec0967f2a6004c5ce368ecb
Signed-off-by: Bruce.Wan <Bruce.Wan@quantatw.com>
Reviewed-on: https://chromium-review.googlesource.com/426558
Commit-Ready: Bruce Wan <Bruce.Wan@quantatw.com>
Tested-by: Bruce Wan <Bruce.Wan@quantatw.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Follow reef setting.
On the bd9995*, back boosting may occur when actual battery voltage
drops below VBAT register setting. Maintain the VBAT register at the
battery-requested charge voltage even when not charging to ensure the
bd9995* doesn't become a back boosted animal.
BUG=none
BRANCH=reef
TEST=make buildall
Change-Id: Ie7aaffc38fef65721886d00be3d6827e9e124efa
Signed-off-by: Bruce.Wan <Bruce.Wan@quantatw.com>
Reviewed-on: https://chromium-review.googlesource.com/426499
Commit-Ready: Bruce Wan <Bruce.Wan@quantatw.com>
Tested-by: Bruce Wan <Bruce.Wan@quantatw.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
When we switch to a state where the sensor is not powered,
we don't call set_data_rate(0), because we may trigger an i2c/spi access
to a sensor already powered off. It has the side effect to leave
data->odr to the last set sensor frequency.
When we init the BMI160, it starts in suspend mode. We will set it to
normal mode only if data->odr is 0. Therefore, we must set odr to 0 in
the init routine.
BUG=chrome-os-partner:61502
BRANCH=reef,kevin
TEST=On reef, without this change. When going to S5 (shutdown -h 0) and
power back up, sensor is stuck (on EC, accelread 1 reads old value).
With this fix, sensor is active and working.
This fix a regression due to CL:411964.
Check others driver do not check odr for setting suspend/normal mode.
Change-Id: Ibc7519d49e55a0b43b4c12ed545bd75ab0260766
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/426766
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
It is not proper to use SET_BIT macro to clear a "write 1 to clear" bit
in a register. It will also clear other bits if they are also set.
BRANCH=none
BUG=chrome-os-partner:34346
TEST=make buildall; boot up on gru, run ectool stress test for a while
without problem.
Change-Id: I0c5a850e85e41820515b1a8f15bb43d77397737f
Signed-off-by: CHLin <CHLIN56@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/425589
Commit-Ready: CH Lin <chlin56@nuvoton.com>
Tested-by: CH Lin <chlin56@nuvoton.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
HW change led power rail, so the battery led and logo led will
light in hibernate state. I modify battery led pin (gpio84,
gpioC4) and logo led pin (pwm3) setting in hibernate, let them
will not light in hibernate.
BUG=none
BRANCH=reef
TEST=make buildall
Change-Id: I6c75694cf92fe05b5afc0d2a399e15c5bff6b7f8
Signed-off-by: Bruce.Wan <Bruce.Wan@quantatw.com>
Reviewed-on: https://chromium-review.googlesource.com/425563
Commit-Ready: Bruce Wan <Bruce.Wan@quantatw.com>
Tested-by: Bruce Wan <Bruce.Wan@quantatw.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
- CHG port can connect as SNK at different voltage levels
- DUT port presents as SNK only
- DUT port uses fixed polarity since it has a fixed cable
- Not supporting ALT or ALT_DP modes in terms of svdm messages at
this point.
- No support yet for USB mux.
BUG=chromium:571476
BRANCH=None
TEST=Manual
CHG port: Tested with Zinger and Plankton and 5/12/20V VBUS levels.
DUT port: Tested against Reef and verified that port reached SNK_READY.
Change-Id: Ib645872790912f9e0a0d4adddc10345a59145d3e
Signed-off-by: Scott <scollyer@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/424413
Commit-Ready: Scott Collyer <scollyer@chromium.org>
Tested-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Nick Sanders <nsanders@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
change inline assembly for fsqrt and fabs
BUG=none
BRANCH=None
TEST=`make buildall -j`
1. Compare sqareroot(2) from calculator and from sqrtf(2.0f) by multiplying
1.0 x 10E8 for both values to convert int32_t and check the difference.
2. read timestampt before and after 'sqrtf()' and calculate execution
time.
Change-Id: I62694d8b084a3a74040dc298354b4fd685e77729
Signed-off-by: Kyoung Kim <kyoung.il.kim@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/404927
Commit-Ready: Kyoung Il Kim <kyoung.il.kim@intel.com>
Tested-by: Kyoung Il Kim <kyoung.il.kim@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Kyoung Il Kim <kyoung.il.kim@intel.com>
To avoid SRAM footprint, let's use dynamic memory allocation in
nvram_vars. No one is using this module yet, but the cr50 use case is
coming up.
BRANCH=none
BUG=chrome-os-partner:61107
TEST=make buildall -j passes
Change-Id: I21534430217ad387a3787fcc127da596a1b48e03
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/426088
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
Extracted Intel x86 power sequencing common code from skylake.c
and apollolake.c to implement common code for power sequencing.
BUG=chrome-os-partner:59141
BRANCH=none
TEST=make buildall -j
Reef can boot to OS. S3, S5, hibernate are working.
Change-Id: I73478fcabb24d6d98cd474bae3586ce5b02986fe
Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/406486
Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit adds a "spoof" mode feature to the motionsense stack. It
allows the user to arbitrarily set the outputs of the sensor in order to
"spoof" the readings of the sensor. This can be useful in emulating
tablet mode or device rotations. A command is available from the EC
console named `accelspoof` and there is a corresponding motionsense
command in ectool called `spoof`.
The usage is as follows:
- EC console
> accelspoof [id] [on/off] [X Y Z]
- ectool
# ectool motionsense spoof -- [id] [0/1] [X Y Z]
If on or off(or 0/1) is not specified, the current spoof mode status of
the sensor is returned. If on is specified, but no components are
provided, the sensor will lock the current values and provide those as
the spoofed values. If the components are provided, those will be used
as the spoofed values.
BUG=chromium:675263
BRANCH=cyan,glados,gru,oak
TEST=Flash a DUT with accels. From AP console, run `ectool motionsense
lid_angle` in a loop, use 'accelspoof' EC console command to set spoofed
values. Verify that the angle is fixed regardless of the actual angle
of the DUT.
TEST=Flash a DUT with accels. From AP console, use `ectool motionsense
spoof` to spoof values and verify that `ectool motionsense` reflects the
spoofed values. Test with both provided component values and no
component values.
Change-Id: Ie30688d22f38054e7243b1af493a3092b2cdfb72
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/421280
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Gwendal Grignou <gwendal@chromium.org>
AverageTimeToFull() and AverageTimeToEmpty() are the predicted time based
on the AverageCurrent(), these do not reflect the instant time of charging
or discharging. Hence we observe huge number of time (1092h because
register has 65535) to full time when battery starts accepting current
upon reaching 100%. To overcome this issue, explicitly checking if the
AverageTimeToFull() and AverageTimeToEmpty() register values are updated
with the valid data.
BUG=chrome-os-partner:60802
BRANCH=none
TEST=Manually tested on Reef. Charge the battery to 100%, once the
battery starts accepting current again observed time to full
is not huge number.
Change-Id: I6d6c21b72ab824dbe47e44e1e77f1c5319ac2720
Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/425324
Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Use binary search in host command lookup dispatcher
BUG=chromium:570895
TEST=manual testing on kevin
- Kevin boots
- ectool hello
make buildall -j
Verify *.smap hcmds section is sorted:
BOARD with host commands and private host commands
0004d0ec R __hcmds
0004d0ec R __host_cmd_0x00000x0000
0004d0f8 R __host_cmd_0x00000x0001
0004d104 R __host_cmd_0x00000x0002
0004d110 R __host_cmd_0x00000x0003
0004d11c R __host_cmd_0x00000x0004
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BOARD with host commands only
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BRANCH=none
Change-Id: I5d13d2a7fe7fa9a0fbeed43177cc612f572a58bb
Reviewed-on: https://chromium-review.googlesource.com/419702
Commit-Ready: Sam Hurst <shurst@google.com>
Tested-by: Sam Hurst <shurst@google.com>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
- Before the change was made, the "__ro_end" was at 00013520h.
We change to 00012760h.
- Rename "CONFIG_IT83XX_ILM_BLOCK_SIZE" to "IT83XX_ILM_BLOCK_SIZE"
this is because we don't support reconfiguration at board-level.
- Put some task functions into "__ram_code" section to
fill the gap and improving performance of code-fetch.
Signed-off-by: Dino Li <dino.li@ite.com.tw>
BRANCH=none
BUG=none
TEST=console commands: flasherase, flashwrite, and flashread.
Change-Id: I2f2906a2a0b6971aadd00120c282801161447808
Reviewed-on: https://chromium-review.googlesource.com/424248
Commit-Ready: Dino Li <Dino.Li@ite.com.tw>
Tested-by: Dino Li <Dino.Li@ite.com.tw>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Add HOST_LDFLAGS to cmd_c_to_host to allow for cross-compilation of
utils such as 'ectool'.
BRANCH=master
BUG=none
TEST=Cross compile using arm-oe-linux-gnueabi with corresponding
linkerflags and run resulting binary on armv7 device
Change-Id: Iebdfa92239eb5f245d4ad3623cbdceafd82d1675
Signed-off-by: Moritz Fischer <moritz.fischer@ettus.com>
Reviewed-on: https://chromium-review.googlesource.com/424855
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Martin Roth <martinroth@chromium.org>
TPM NVMEM commits are reenabled as soon as the system boots into
Chrome OS. However, sometimes the device does not boot into Chrome OS,
in which case it is necessary to be able to reinstate NVMEM commits
explicitly.
The new vendor command will provide this functionality.
BRANCH=none
BUG=chrome-os-partner:59873
TEST=added code to depthcharge to issue the new vendor command if the
system falls into recovery mode, verify that commits are
re-instated once the command is issued.
Change-Id: I3c06b27175751dc2c095911441935eee62ed9c50
Reviewed-on: https://chromium-review.googlesource.com/424064
Commit-Ready: Vadim Bendebury <vbendeb@chromium.org>
Tested-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This patch eliminates NVMEM commits at system startup, namely between
the moment the TPM is reset and the moment the AP is trying to read a
PCR (which is an indication of the AP having booted into OS).
To avoid losing NVMEM changes in case TPM is reset before PCR Read
command is issued, pending changes (if any) are saved before TPM reset
is processed.
For the same reason TPM reset invocation is being added to the hard
reboot path; this will kick in when there is a restart after cr50
firmware update.
BRANCH=none
BUG=chrome-os-partner:59873
TEST=with instrumented coreboot/depthcharge observed the following
execution times for various TPM command issued at startup
command 0x144, 15203 us
command 0x14e, 11814 us
command 0x182, 12461 us
command 0x182, 12456 us
command 0x138, 11503 us
command 0x138, 11512 us
command 0x14e, 14648 us
command 0x14e, 12597 us
command 0x121, 11353 us
which totals 113 ms and shaves more than 200 ms off the boot time.
Change-Id: Ic52309291fdb9c3ede96e0ad015ad9fc076bddc5
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/424063
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Andrey Pronin <apronin@chromium.org>
In preparation to adding new features, switch cr50 to using shared
memory allocator allowing concurrently allocated buffers.
BRANCH=none
BUG=chrome-os-partner:59873
TEST=verified that cr50 works fine and could be updated on a reef.
Change-Id: I87656cbd1f6d4928f25396dbcc59cc3f43984d85
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/424850
Reviewed-by: Randall Spangler <rspangler@chromium.org>
The new code allows to replace the existing one buffer at a time
shared memory facility with a malloc/free implementation. A new
configuration option is being provided (CONFIG_MALLOC).
The names of functions allocating and freeing memory are not being
changed to allow to switch between the two implementations seamlessly.
A double linked list of buffers is used to keep track of free and
allocated memory. During initialization the entire free memory block
is considered a single free buffer. No allocations/frees are allowed
from within interrupts. The control structures are protected by a
semaphore, so allocate and free invocation could be blocking.
A test is added which randomly allocates and frees memory, continuing
until all branches in the allocate and free functions are taken.
BUG=chrome-os-partner:
TEST=make buildall -j succeeds, which includes testing the new
malloc/free implementation.
Change-Id: I5e71c0190c6c247ec73bb459f66a6d7a06e3d248
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/420466
Reviewed-by: Randall Spangler <rspangler@chromium.org>
