This CL adds the config option CONFIG_DYNAMIC_MOTION_SENSOR_COUNT and
SKU table which contains the form factor for all known SKUs. Once the
SKU ID is known, the variable motion_sensor_count is set based on
CLAMSHELL or CONVERTIBLE designation in the SKU table. If there isn't
a matching SKU ID in the table then motion_sensor_count will be
initialized to the ARRAY_LENGTH of motion_sensors.
BUG=b:38271876
BRANCH=None
TEST=Manual
Tested with Robo360 (SKU ID 71) and verified the motion sensor count
and that the motion senors were initialized in the EC console log.
[0.088188 Motion Sensor Init: count = 3]
[0.346097 Lid Accel: MS Done Init type:0x0 range:2]
[0.370386 Base Accel: MS Done Init type:0x0 range:2]
[0.386790 Base Gyro: MS Done Init type:0x1 range:1000]
Tested with Santa EVT (SKU ID 3) and verified motion_sensor_count is 0 and
no EC console messages showing sensor initialization failures.
Change-Id: Ia3d60f8c8dd4435dd7cfb80a860f809de2fb931e
Signed-off-by: Scott Collyer <scollyer@google.com>
Reviewed-on: https://chromium-review.googlesource.com/711195
Commit-Ready: Aaron Durbin <adurbin@chromium.org>
Tested-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Fizz allocates 15W to the type-c port. This patch allows the port
to use it.
BUG=b:67682343
BRANCH=none
TEST=Verify 5V 3A PDO is offered.
Change-Id: I1560c0c7cb04379f5e4c9893753afe4a7f0cefe4
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/713583
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
The default RTCCLK comes from LSI, which can vary from 30kHz to 60kHz.
To use stm32 RTC for applications requiring accurate timing, let's setup
LSE (a more accurate clock source) as RTCCLK.
Also fix a typo in register.h as 'BCDR' should be 'BDCR' globally.
BUG=b:63908519
BRANCH=none
TEST=boot scarlet rev1 and wait for an hour,
confirm rtc time == kernel system time.
Change-Id: If4728bdd3b6384316e5337004a49c172eaec869d
Signed-off-by: Philip Chen <philipchen@google.com>
Reviewed-on: https://chromium-review.googlesource.com/679601
Commit-Ready: Philip Chen <philipchen@chromium.org>
Tested-by: Philip Chen <philipchen@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Shipped devices were found that batteries could enter ship mode
unexpectedly. Fail rate is about 5/700pcs per day. Failure happens
when battery is charged fully and eneters sleep(mem), and then AC is
plugged out.
Battery ship mode is entered because ec execute console command
"cutoff". Still do not know what causes that when no any device
connected to servo board connector (console TX and RX are floated).
Enable this config item will cut off route from RX input and fix
the issue.
BUG=b:67033247
BRANCH=none
TEST=with 50 DUTs, flash ec to DUTs and then lock the system, charge
the battery from about 80% capacity to 100% capacity, close the lid
for 20 minutes, unplug AC, boot the system, all DUTs boot, no DUT's
battery enter ship mode. The same test repeats 3 times.
Change-Id: I9939fed1467026bc2d85c645b6ecebae4b6796c6
Signed-off-by: Chao Ge <chao.ge@bitland.com.cn>
Reviewed-on: https://chromium-review.googlesource.com/693921
Commit-Ready: ge chao <chao.ge@bitland.com.cn>
Tested-by: ge chao <chao.ge@bitland.com.cn>
Reviewed-by: Rong Chang <rongchang@chromium.org>
The usb_updater utility has long been not just an updater, and has
long been using other interfaces in addition to USB. gsctool is a much
more suitable name.
CQ-DEPEND=CL:709776
BRANCH=cr50
BUG=b:67007500
TEST=verified that make -C ./extra/usb_updater generates
./extra/usb_updater/gsctool:
$ ./extra/usb_updater/gsctool --help
Usage: gsctool [options] <binary image>
This updates the Cr50 RW firmware over USB.
The required argument is the full RO+RW image.
Options:
[...]
$
Change-Id: I3ab70c28acf3664ddefaa923a87ba1fd5c3c437b
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/709738
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
The Nasher simplo battery uses the Reneas fuel gauge. The table entry
for this battery had TI fuel gauge assumption. This CL modifies the FET
info to use register 0x43 and bits 1|0.
In addition added console log entry for the FET register, mask, and
expected value. In normal cases this log message will appear only
once, but when recovering from battery cutoff, will have have one
entry per call until the battery is no reporting as disconnected.
BUG=b:64887361
BRANCH=None
TEST=Using nasher proto system connected the SMP-SDI3.72
battery. Tested normal start up and after doing a battery cutoff.
Normal caseL:
[0.038624 found batt:SMP-SDI3.72}
[0.046017 SW 0x01]
[0.068892 hash start 0x00040000 0x00020d08]
[0.075775 Battery FET: reg 0x001b mask 0x0003 disc 0x0000]
After battery cutoff:
[0.146889 Battery FET: reg 0x0008 mask 0x0003 disc 0x0000]
[0.161523 Battery FET: reg 0x0008 mask 0x0003 disc 0x0000]
.
.
[0.476275 Battery FET: reg 0x001b mask 0x0003 disc 0x0000]
Change-Id: Ie378e9a795f543763a02c6c062235b265be0f71c
Signed-off-by: Scott Collyer <scollyer@google.com>
Reviewed-on: https://chromium-review.googlesource.com/705260
Commit-Ready: Scott Collyer <scollyer@chromium.org>
Tested-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Implemented an led state table based implementation for LED control of
the battery LED. The states are the same as previous Coral/Reef single
LED control with the exception of allowing for 3 charging states based
on the current battery state of charge level. Now the desired state
is determined and that's used to access the correct LED behavior based
on the current tick count.
Changed from a one second tick to the NPCX 200 msec tick so the Robo
power button pattern can be supported as well.
The are currently two tables implemented, one for Robo devices, and
the default table. At init time, after the SKU ID is determined, the
correct table is assigned.
BUG=b:64192049
BRANCH=None
TEST=Manual
Tested both Coral proto and Robo EVT systems. Verifed operation in the
different states. During tested used modified charging level tables
so the 3 different charging states could be exercised. Also removed
battery to verify the error state.
Change-Id: Ifc6935f73d4fed1eeec9c5aab13f6346f61857ff
Signed-off-by: Scott Collyer <scollyer@google.com>
Reviewed-on: https://chromium-review.googlesource.com/693387
Commit-Ready: Scott Collyer <scollyer@chromium.org>
Tested-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The decision on whether to ramp (and how high) depends on the quirks of
charger identification, so move the decision out of board, into the
drivers that implement usb_charger.
Also, rename CONFIG_CHARGE_RAMP to CONFIG_CHARGE_RAMP_SW, to better
contrast with the existing CONFIG_CHARGE_RAMP_HW.
BUG=None
TEST=Manual on kevin, verify ramp occurs when port plugged into Z840
workstation.
BRANCH=None
Change-Id: I5b395274133837a18a4f4ac34b59b623287be175
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/702681
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Add a PERSO_AUTH appid to sign data passed through the
AUTH mn50.
Add a signer command to start and generate signatures.
Clean UART init to avoid spurious nonprinting characters
that will contaminate the siugnature.
BUG=b:36910757
BRANCH=None
TEST=generates signature for uart and spi
Signed-off-by: Nick Sanders <nsanders@chromium.org>
Change-Id: I5fc3c4ee34898421060b57b774a09734f6a1bae5
Reviewed-on: https://chromium-review.googlesource.com/670984
Reviewed-by: Marius Schilder <mschilder@chromium.org>
Turn on FORCE_CONSOLE_RESUME and also shuffle around
the context to ensure alphabetical order.
BUG=b:67379662
BRANCH=none
TEST=manually on Scarlet rev1: put AP in suspend mode,
verify EC console still works, and confirm EC goes into
low power idle mode by EC console command 'idlestats'.
Change-Id: I2563e6ed4fdb47123912932ad8ba9172b0c9c13c
Signed-off-by: Philip Chen <philipchen@google.com>
Reviewed-on: https://chromium-review.googlesource.com/702918
Commit-Ready: Philip Chen <philipchen@chromium.org>
Tested-by: Philip Chen <philipchen@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
The way AP resets ec rtc alarm is to set rtc alarm wake time in 0 sec.
In current implementation, this still sets host_rtc_alarm_set.
...So when rtc irq is triggered next time, it wakes up the host even if
the alarm is not set by the host.
Let's fix it.
BUG=b:66971951, b:67379662
BRANCH=none
TEST='powerd_dbus_suspend' and see the host stay in suspend mode
Change-Id: I1e14f669e3d887874548813c7c5b4d21d80bc62e
Signed-off-by: Philip Chen <philipchen@google.com>
Reviewed-on: https://chromium-review.googlesource.com/699657
Commit-Ready: Philip Chen <philipchen@chromium.org>
Tested-by: Philip Chen <philipchen@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
Boards that use charge_manager have identical implementations of
typec_set_input_current_limit() and pd_set_input_current_limit(), so
move these functions to charge_manager.
BUG=b:67413505
TEST=`make buildall -j`, also verify that fizz continues to power-on and
boot AP, in both protected and unprotected mode, with barrel jack power
and with zinger.
BRANCH=None
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: I99a5314d02c4696db944c0f8ac689405f4f1f707
Reviewed-on: https://chromium-review.googlesource.com/701412
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
CONFIG_CASE_CLOSED_DEBUG (CCD functionality implemented by EC) is no
longer used in conjunction with CONFIG_USB_POWER_DELIVERY, and the
common routines are only used by one board.
BUG=chromium:737755
BRANCH=None
TEST=`make buildall -j`
Change-Id: Idc3d2fccef6cbec2af786cef634d752a02a0e859
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/656315
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Nick Sanders <nsanders@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
This enables pull-down on F_DIO1 (SPI MISO), and F_DIO0 (SPI MOSI),
whenever the EC is not doing SPI flash transactions. This avoids
floating SPI buffer input (MISO), which causes power leakage.
BRANCH=none
BUG=b:64797021
TEST=Flash soraka, check output of rw .b 0x400C3029 is 0x80
Check that U58 (SN74LVC244ARWPR) leakage drops from 1.2 mA to 0.
TEST=1. flashrom from host to EC spi flash using servo
2. flashrom from host to EC spi flash using suzyq
3. flashrom from device to EC spi flash
4. EC SW sync
Change-Id: I5ac22142f6a1a5b1c31d6ae272ed7516a112f29e
Signed-off-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/701717
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
This patch undefines CONFIG_SYSTEM_UNLOCKED, which forces the system
to be unlocked, and defines CONFIG_USB_PD_COMM_LOCKED, which enables
PD only if EC is in RW. With this change, if SW write-protect is
enabled, the system will stay in G3 until 50W or more power is
supplied.
BUG=b:38462249
BRANCH=none
TEST=Lock Fizz and boot it on type-c adapter. Verify RW image is
successfully verified and executed.
Change-Id: Id8255c5c8e6af93bda3fd4de079008561f46e14c
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/558377
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
A couple of bugs have crept in with the latest series of patches:
- the board ID value endianness does not have to be changed
- the test RMA server public key value is wrong
BRANCH=cr50
BUG=b:67007905
TEST=the generated challenge is now accepted by the server, and the
generated auth code matches between the server and the Cr50.
Change-Id: I18f413ab0bcc14d9cc50b115ac3784fdfcd5851c
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/700798
Reviewed-by: Michael Tang <ntang@chromium.org>
Runtime S0ix results in SLP_S0 signal being toggled continuously
resulting in an interrupt storm on the EC. In order to avoid this,
enable SLP_S0 power signal only when host indicates intent to enter
S0ix and disable when host exits from S0ix.
BUG=b:65421825
BRANCH=None
TEST=Verified that runtime S0ix no longer results in interrupt storm
on EC. Normal S0ix works fine on soraka. Verified state of SLP_S0
using powerindebug.
Change-Id: I9ca62b8122afd8acedc2c353106407fdcc284925
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/679982
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
This patch uses the VENDOR_CC_RMA_CHALLENGE_RESPONSE vendor command to
request the Cr50 generate the RMA authentication challenge and to have
the Cr50 verify the authentication code received from the server.
The new command line option is -r/--rma_auth. Presently it works only
when Cr50 is accessed over the TPM interface (as opposed to USB), i.e.
command line options -s or -t are also present, and the utility is
running on the Chrome OS device.
CQ-DEPEND=CL:690992
BRANCH=none
BUG=b:37952913
TEST=on a Bob device ran the command with correct and incorrect
authentication codes, observed expected behavior (reported
success or error):
localhost ~ # /var/tmp/usb_updater -t -r
Challenge:
B9FPX D93GM JTJE7 ZNR74 E2GZF 94E8B TXBFX UJ4WZ
3ZQ98 XZ42D D4MVT RA2WG UDMKP A8FMH GXJQG BAKAS
Now enter response: 7996N3NW
RMA unlock succeeded.
localhost ~ # /var/tmp/usb_updater -t -r
error 4 <<=== this is the time throttle error
localhost ~ # /var/tmp/usb_updater -t -r
Challenge:
B9BLC F7B3D 7WY8V DKGQF 6CFP8 UCZRU UCZRW YKUG7
ZGNVC F4ZEH X75LE BANWE UDMKP A8FMH GXJQG BAKAS
Now enter response: 7996N3NW <<==== this is an incorrect code
rma unlock failed, code 6
localhost ~ #
Change-Id: Ifbf1a349e3d2655cea6c33f928d9cf58a6408531
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/690443
Reviewed-by: Randall Spangler <rspangler@chromium.org>
When the battery gets to returns the FULL flag, bd99956 charging is
disabled and battery learning is enabled. This state will remain until
the FULL flag is cleared by the battery. The original fix had this
level at 97%, but on the various batteries tested this appears to
happen at 95%. The CONFIG_BATTERY_LEVEL_NEAR_FULL allows an adjustment
for this level and is only used for LED states.
BUG=b:64192049
BRANCH=None
TEST=Manual Let system charge to 100% when FULL flag is set in the
battery, verified the LED was in correct state. Then let battery drain
until the FULL flag is clear and observe that the battery requests
charge current. The LED stays in the expected full charge state.
Change-Id: I74d26abd5d8021bcfacdc3a4c3d4baba6a978bca
Signed-off-by: Scott Collyer <scollyer@google.com>
Reviewed-on: https://chromium-review.googlesource.com/693386
Commit-Ready: Scott Collyer <scollyer@chromium.org>
Tested-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Any time the host sleep state is updated (including reset of host
sleep state), make a callback into
power_chipset_handle_host_sleep_event to allow mainboard and chipset
to take any necessary action.
BUG=b:65421825
BRANCH=None
TEST=make -j buildall
Change-Id: Ib4d35fa0b417500090361e4e26415feedb663e35
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/683797
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Replace structure member "level" in power_signal_info with "flags".
"level" has been used on all boards to indicate active-high or
active-low levels. Addition of "flags" allows easy extension of
power_signal_info structure to define various flags that might be
applicable to power signals (e.g. "level"). Going forward, additional
flag will be added in follow-up CLs.
Also, provide a helper function power_signal_is_asserted that checks
the actual level of a signal and compares it to the flags level to
identify if a power signal is asserted.
BUG=b:65421825
BRANCH=None
TEST=make -j buildall
Change-Id: Iacaabd1185b347c17b5159f05520731505b824b8
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/679979
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
When the host sets rtc alarm wake time = 0, it wants
to reset and disable the alarm.
Also, align the implementation in npcx with that in stm32
to check both delay_s and delay_us.
BUG=b:66971951, b:63908519
BRANCH=none
TEST='ectool rtcsetalarm 3'. After alarm goes off, run
'ectool rtcgetalarm' and then see 'Alarm not set'.
Change-Id: I693f1c72cba492e837891c716f79e2aa4da59b2a
Signed-off-by: Philip Chen <philipchen@google.com>
Reviewed-on: https://chromium-review.googlesource.com/691256
Commit-Ready: Philip Chen <philipchen@chromium.org>
Tested-by: Philip Chen <philipchen@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Brian Norris <briannorris@chromium.org>
Enable necessary flags for the Cr50 to start supporting RMA
authentication. This also requires that the RMA server public key
definition is split between the actual and test. Even though they are
the same at this time, the actual public key would be defined in the
new future and it would be different from the test key.
BRANCH=cr50
BUG=b:65253310
TEST=make buildall -j passes. More tests were conducted on the full
patchset.
Change-Id: I5a3f9d8c71374d78192e3f0a2752391b842da962
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/691554
Reviewed-by: Randall Spangler <rspangler@chromium.org>
The new vendor command operates in two modes: when received with a
zero size payload, it triggers the Cr50 to generate a new RMA
authentication challenge and the expected authentication code value.
When receive with the payload, it compares the received payload with
the pre-calculate authentication code, and returns to the host the
comparison result (passed/not passed).
A care is taken not to accept payload until at least there is a valid
calculated auth code present (to avoid reporting a match on a payload
of all zeros).
Test config needed to be modified to allow compiling of the ccprintf
wrapper.
BRANCH=cr50
BUG=b:37952913
TEST=with the rest of the patches applied observed expected behavior
of generating challenge/response and verifying the auth code.
Change-Id: I30638b0ceef68830565f222dd1f4af17cfc8d7ef
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/690992
Different devices could have different sized unique device IDs. Let's
just use the IDs as is if they are no larger than the
rma_challenge:device_id field, or the first 8 bytes of the HMAC_sha256
value of the unique device ID, where the unique device ID is used both
as the key and the payload.
The server expects the board ID field in big endian format, let's swap
it before calculating the RMA auth challenge.
The test's server side implementation needs to be also adjusted.
BRANCH=cr50
BUG=b:37952913
TEST=make buildall -j passes. With the rest of the patches applied RMA
authentication process generates sensible values.
Change-Id: Ia1fbf9161e01de30a2da8214258008f6e5f7d915
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/690991
Reviewed-by: Michael Tang <ntang@chromium.org>
On Cr50 the crypto library has a slightly different API, as indicated
by the presence of the CONFIG_DCRYPTO configuration option.
This patch provides a wrapper which allows to calculate a SHA256 HMAC
hash using either underlying crypto API.
BRANCH=cr50
BUG=b:37952913
TEST=make buildall -j
Change-Id: Ibb8c60e50139fd5506a4dd5f2ed19653c68af8cb
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/690440
Reviewed-by: Randall Spangler <rspangler@chromium.org>
With upcoming RMA authentication extensions the size of the vendor
command responses is going to increase. Let's allow 500 bytes per
response (the expected maximum is 80 bytes plus TPM header).
BRANCH=cr50
BUG=b:37952913
TEST=verified that gsctool (aka usb_updater) still allows to retrieve
Cr59 information and update Cr50 image.
Change-Id: Ic61b6b89ffe20e534029bd12fea4140882a9afc8
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/690442
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
The Board ID is stored in Cr50 in reversed byte order, make sure it is
used in the challenge calculation in the same form.
BRANCH=none
BUG=b:37952913
TEST=verified that the proper byte order is used when challenge source
is created.
Change-Id: I6c6b46431005ce9438a4be9aa43aafed30a645aa
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/693615
Reviewed-by: Michael Tang <ntang@chromium.org>
Hash command expects second parameter to be either
abort, RO, RW. If not then exit the function by
displaying error message instead of calculating hash.
BUG=NONE
BRANCH=NONE
TEST=On EC console 'hash help' should display error message
with usage info.
Change-Id: I4fcad97ce0da1cd48a458de1c659aa3c6b2a60b9
Signed-off-by: Jagadish Krishnamoorthy <jagadish.krishnamoorthy@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/691436
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
To aid with severe flash space shortage, let's enable
CRYPTO_TEST_SETUP only if CR50_DEV is set to a value exceeding 1.
board/mn50/board.h used to define CR50_DEV without any value assigned
to it, correct this so that the check in dcrypto.h works when mn50 is
built.
BRANCH=cr50
BUG=b:65253310
TEST=compiling with CR50-DEV=1 vs CR50_DEV=2 saves more than
17.5 Kbytes per RW image.
Change-Id: Ic77fa45b1a8f7631efa91c08e63438d412196eed
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/690993
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Adding a flag to print power numbers in milliwatts instead of
microwatts, to be the same as servo ina board. This will make it
easier for power team to keep track of power numbers in the
future.
BRANCH=None
BUG=b:35578707
TEST=./powerlog.py -b xxx.board -c xxx.scenario --mW
python -m unittest -v stats_manager_unittest
Change-Id: I397da26561324227682404e62ee025384e7624eb
Signed-off-by: Mengqi Guo <mqg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/688743
Reviewed-by: Nick Sanders <nsanders@chromium.org>
Reviewed-by: Puthikorn Voravootivat <puthik@chromium.org>
Currently, when CCD is opened, there is no way to disable the EC
and/or AP UARTs. But if there is some problem with the EC and/or AP,
and their UARTs are spamming interrupts, it can make debugging more
difficult.
If servo detection malfunctions, then CCD may drive the ports and
interfere with servo.
Add a new ccdblock command to disable the AP UART, EC UART, or any
ports shared with servo, until the next cr50 reboot.
BUG=b:65639347
BRANCH=cr50
TEST=manual with CR50_DEV=1 image, AP/EC powered on, suzyq connected
ccdblock --> (none)
ccdstate --> UARTAP+TX UARTEC+TX I2C SPI
ccdblock AP on
ccdstate --> UARTEC+TX I2C SPI
ccdblock EC on
ccdstate --> I2C SPI
ccdblock -> AP EC
ccdblock AP off
ccdstate --> UARTAP+TX I2C SPI
ccdblock EC off --> (none)
ccdstate --> UARTAP+TX UARTEC+TX I2C SPI
ccdblock SERVO on
ccdstate --> UARTAP UARTEC
ccd lock
ccdblock AP on --> access denied
Change-Id: I3dcc8314fc98a17af57f2fe0d150ecd1a19ccf52
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/693041
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
This CL provides the tool to calculate statistics for sweetberry
readings and present them in a clear & easy to read format. It
also provides the flag to store raw data and statistics
summary, should the need arise.
There are also some code cleanup for powerlog.py.
BRANCH=None
BUG=b:35578707
TEST=./powerlog.py -b xxx.board -c xxx.scenario --print_stats \
--save_stats --save_raw_data
python -m unittest -v stats_manager_unittest
Change-Id: I4aa732756fe6512f37acfcb59b11d950101887d7
Signed-off-by: Mengqi Guo <mqg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/667241
Reviewed-by: Nick Sanders <nsanders@chromium.org>
On proto3, PMIC isn't powered on POR, thus board_pmic_init fails.
With this change, EC waits until AP power is ready before it
notifies HOOK_CHIPSET_PRE_INIT where PMIC will be initialized.
When AP power is ready, PMIC should be ready as well.
BUG=b:65839247,b:64944394
BRANCH=none
TEST=Run reboot [/cold/ap-off] command on BJ and Type-C.
Change-Id: I7e7e07b5acf92167584966ded0a5f14fb6b04f0b
Reviewed-on: https://chromium-review.googlesource.com/672152
Commit-Ready: Daisuke Nojiri <dnojiri@chromium.org>
Tested-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Usage: rma_reset --key_id <arg> --board_id <arg> --device_id <arg>
--hw_id <arg> | --auth_code <arg>
These value are used for generating the challenge response and all are
mandatory.
-k,--key_id Index of the server private key
-b,--board_id BoardID type field
-d,--device_id Device-unique identifier
-w,--hw_id Hardware id
The -t parameter, not listed, will use the default values to generate
the challenge response
This value is the authorization code and any other parameters are ignored
-a,--auth_code Reset authorization code
BUG=b:37952913
BRANCH=none
TEST=make buildall
Signed-off-by: Sam Hurst <shurst@chromium.org>
Change-Id: Idc916b123928328a3425fa4eee22afc2ec179fc1
Reviewed-on: https://chromium-review.googlesource.com/665388
Commit-Ready: Sam Hurst <shurst@google.com>
Commit-Ready: Vadim Bendebury <vbendeb@chromium.org>
Tested-by: Sam Hurst <shurst@google.com>
Reviewed-by: Michael Tang <ntang@chromium.org>
Fizz EC verifies RW by itself and jumps to RW before AP boots.
If this fails, the system needs recovery. Since EC isn't
capable of showing any info on a display, we use the power
LED to inform the user.
BUG=b:66914368
BRANCH=none
TEST=Make Fizz fail RW verification. Observe LED illuminates
in red.
Change-Id: Ia07de60a316b40e74b1917903996d78750b4ae43
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/683218
This patch makes the LED blink to alert the user when there is
not enough power to boot the system.
This patch also changes minimum boot power to 50W. It's common
for all SKUs.
BUG=b:37646390
BRANCH=none
TEST=Power Fizz with 15W, 45W, 60W chargers. Verify LED blinks as
expected.
Change-Id: If269897f5022f6cba80f37ce03e2315cfb2cf504
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/682876
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
This prevents the files from showing in 'git status' output.
BRANCH=none
BUG=none
TEST=verify that the running the following does not show any generated
files:
make -C extra/rma_reset; git status
Change-Id: Ib3ff7772cf4a66e4a0d23ed859c30ac05c2e507d
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/691016
Reviewed-by: Michael Tang <ntang@chromium.org>
If we don't use IT8320's PD module, we should dis-connect resistor
to GND and disable CC related function to make sure these pins can
work as other function.
BRANCH=none
BUG=none
TEST=CCCSR register setting is 0xff after initialization if
we don't enable CONFIG_USB_PD_TCPM_ITE83XX.
Change-Id: I97e019ec1c9c852cd758b364a5e7913de1fc84f4
Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
Reviewed-on: https://chromium-review.googlesource.com/689435
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
We need to response EC ACPI device orientation command or
keyboard/trackpad didn't work on OS image version R58 and
after.
BRANCH=none
BUG=none
TEST=keyboard and trackpad work on R58 and after.
Change-Id: I49f9c90e73a5e529eb228169e4148f4dcd4a45e6
Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
Reviewed-on: https://chromium-review.googlesource.com/689715
Reviewed-by: Shawn N <shawnn@chromium.org>
In npcx7, we introduced a new bit, VWUPDW, in ESPISTS register to
indicate a Master-to-Slave VW signal was updated and the relevant WE
bit is 1. But there's no relevant IE bit in ESPIIE for VWUPDW, old
mechanism for clearing pending bits of ESPISTS will ignore this bit.
And ec cannot enter deep sleep anymore since this bit is set. This CL
fixed this bug by setting bit 17 of mask variable if ec is npcx7 series.
BRANCH=none
BUG=none
TEST=No build errors for npcx5/7 series.
Change-Id: I80c57d3c230e9d06ba134538ccdcd29f290bb7bf
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/672183
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Amit Maoz <Amit.Maoz@nuvoton.com>
In this CL, we introduced new bit fields of eSPI registers on npcx5/7
for the incoming patches. We also remove useless registers such as
VWGPMS, VWGPSM and PING in order to let the driver look more clearly.
This CL also includes:
1. Fixed typo from ESPIIWE to ESPIWE.
2. Introduce ESPIWE bits fields on npcx5/7.
3. Introduce new bit fields in ESPISTS of npcx7.
4. Remove useless VW1-4, VW1IE1-4 bits in ESPISTS and ESPIIE registes.
5. Introduce new bit field, WE, in VWEVMSn register of npcx7.
BRANCH=none
BUG=none
TEST=No build errors for npcx5/7 series. Using "suspend_stress_test -c
1000" to do stress test and no symptom occurred on poppy. Both warmboot
and coldboot stress test for 3 hours and no symptom occurred on poppy.
Change-Id: Ie8aa3dbd148588b0d9a756572d66604a6836a760
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/672026
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Amit Maoz <Amit.Maoz@nuvoton.com>
