Because N8 CPU doesn't have floating point unit,
so we implement an extra floating point engine
(single-precision addition, subtraction, multiplication,
and division) into it8320 to improve performance of
floating point operation.
To make CPU's instruction compatible, we use register (DLMB)
to switch ALU (Arithmetic Logic Unit). eg:
Instruction 'ADD45' adds the contents of two registers then
writes the result to the source register.
But if we switch ALU to floating point operation mode,
this instruction will do a floating-point addition instead.
For the other FPU that we don't support as far,
we have to use soft float library routines of nds32.
Signed-off-by: Dino Li <dino.li@ite.com.tw>
BRANCH=none
BUG=none
TEST=add the following console command and test different
scenarios by changing variable a and b.
#define PRINTF_FLOAT(x) ((int)((x) * 1000.0f))
static int it83xx_fpu_test(int argc, char **argv)
{
volatile float a = 1.23f;
volatile float b = 4.56f;
volatile float c;
c = a + b;
ccprintf("__addsf3: (%d)\n", PRINTF_FLOAT(c));
c = a - b;
ccprintf("__subsf3: (%d)\n", PRINTF_FLOAT(c));
c = a * b;
ccprintf("__mulsf3: (%d)\n", PRINTF_FLOAT(c));
c = a / b;
ccprintf("__divsf3: (%d)\n", PRINTF_FLOAT(c));
return EC_SUCCESS;
}
DECLARE_CONSOLE_COMMAND(fpu, it83xx_fpu_test, "", "");
Change-Id: I4fc1c08d8c2376156bec9f098491187675c4a88f
Reviewed-on: https://chromium-review.googlesource.com/427640
Commit-Ready: Dino Li <Dino.Li@ite.com.tw>
Tested-by: Dino Li <Dino.Li@ite.com.tw>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
The trimmed value of CC parameter setting registers
(port0: ff3760h ~ ff3763h, port1: ff3860h ~ ff3863h)
will be reset to default after a soft reset (system_reset()).
BRANCH=none
BUG=none
TEST=Console command 'reboot' and checking if the value of
cc parameter setting registers are correct (trimmed).
Change-Id: Ibf9c72e8aeef36701d72bcb64529735295295cdf
Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
Reviewed-on: https://chromium-review.googlesource.com/513744
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
1. Disable USB debug interface:
If we don't use GPIOH.5/6 pins for debugging,
we should disable it to prevent any chances of entering debug mode.
2. command_idle_stats() behind CONFIG_CMD_IDLE_STATS:
We can exclude this console command if we don't use it.
3. Remove 'dsleep' console command:
DEEP_SLEEP_ALLOWED macro is enough for us.
BRANCH=none
BUG=none
TEST=bit7 at 0xF02030(MCCR register) is cleared after initialization.
Change-Id: If34e9738351459891be8c9a6619384adbfe26335
Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
Reviewed-on: https://chromium-review.googlesource.com/487843
Reviewed-by: Randall Spangler <rspangler@chromium.org>
We can get the correct chip info after the change was made.
BRANCH=none
BUG=none
TEST=console message:
[0.013915 TCPC p1 VID:0x48d PID:0x8320 DID:0x1 FWV:0xec]
[0.018054 TCPC p0 VID:0x48d PID:0x8320 DID:0x1 FWV:0xec]
Change-Id: I4eb94967acb351559e745ed1c4e34a4c58f41e14
Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
Reviewed-on: https://chromium-review.googlesource.com/487767
Reviewed-by: Randall Spangler <rspangler@chromium.org>
This timeout is described in SMBus specification (25ms).
Some I2C devices may required longer clock stretch
(The I2C specification does not specify any timeout conditions
for clock stretching).
So we increase this timeout to maximum.
NOTE:
Because this codebase already handle timeout of an I2C transfer,
so maybe we can disable this mechanism.
But we don't have any register to execute this,
so we maximize the timeout.
BRANCH=none
BUG=none
TEST=console commands: i2cscan, battery, charger, and accelinfo.
Change-Id: I5025f640c027105152247212fc688388f645c5ba
Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
Reviewed-on: https://chromium-review.googlesource.com/485203
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Currently if an interrupt is pending before it is enabled the interrupt
will fire immediately. In most cases this is fine, but if we want to
use the interrupt to trigger something like waking the AP it should be
sure that it won't immediately fire once enabled.
For example: on the Eve board we have the trackpad interrupt run to the
AP and the EC in order to support wake from Deep S3 (magic AP state that
only the EC can wake it from). This interrupt is used in S0 by the AP
while ignored by the EC, and then enabled on the transition to S3 in
order to be able to wake. Since it has been active the interrupt may
be pending in the EC (depending on the chip), which can result in the
interrupt firing immediately and waking the AP.
BUG=chrome-os-partner:62224
BRANCH=none
TEST=This has been functionally tested on npcx only as that is what I
have a use case and system for, the others compile and look right but
have not been directly tested.
Change-Id: I9e0877d99e7f09f4c30bf9861fbad81c12c059ad
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://chromium-review.googlesource.com/446962
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Our previous idea to cut Rd for many reset cases cannot work if cr50
consistently resets the EC by asserting the reset pin shortly after
power-on. Therefore, make a decision based upon whether battery-backed
memory indicates we previously negotiated a PD power contract as a sink.
If we previously did not negotiate a contract, or if power was removed
from the device (causing battery-backed memory to wipe) then we can
assume that we don't have an active power contract.
BUG=chrome-os-partner:62952
BRANCH=reef
TEST=On reef, run "cutoff" on the console, reattach AC, and verify
device successfully wakes. Also verify Rp is dropped on console 'reboot'
and F3 + power from RW.
Change-Id: Ie300b9589cac6be7a69b77678bea6b1b6b25578c
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/443356
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Add generic routines to read or write a byte to battery-backed RAM, and
implement vbnvcontext get/set using these routines.
BUG=chrome-os-partner:62952
BRANCH=reef
TEST=On reef, with subsequent commit, run "cutoff" on the console,
reattach AC, and verify device successfully wakes. Also verify Rp is
dropped on console 'reboot' and F3 + power from RW.
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: I14691923f2e5198e901b6b5199e92c58c68cd18d
Reviewed-on: https://chromium-review.googlesource.com/444444
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
We don't need to loop and waiting ADC's data valid flag
after the change was made.
Signed-off-by: Dino Li <dino.li@ite.com.tw>
BRANCH=none
BUG=none
TEST=1. We build a EC binary for PD EVB (declared two ADC channels
for VBUS measurement of PD task and priority is highest)
2. Use console command "adc" continually to read ADC channels
and check if any error.
Change-Id: I1379e0b4c9ef721c29cb053d7d85e1a8ece9471b
Reviewed-on: https://chromium-review.googlesource.com/421307
Commit-Ready: Dino Li <Dino.Li@ite.com.tw>
Tested-by: Dino Li <Dino.Li@ite.com.tw>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
- Before the change was made, the "__ro_end" was at 00013520h.
We change to 00012760h.
- Rename "CONFIG_IT83XX_ILM_BLOCK_SIZE" to "IT83XX_ILM_BLOCK_SIZE"
this is because we don't support reconfiguration at board-level.
- Put some task functions into "__ram_code" section to
fill the gap and improving performance of code-fetch.
Signed-off-by: Dino Li <dino.li@ite.com.tw>
BRANCH=none
BUG=none
TEST=console commands: flasherase, flashwrite, and flashread.
Change-Id: I2f2906a2a0b6971aadd00120c282801161447808
Reviewed-on: https://chromium-review.googlesource.com/424248
Commit-Ready: Dino Li <Dino.Li@ite.com.tw>
Tested-by: Dino Li <Dino.Li@ite.com.tw>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reset-on-hibernate wake performs a soft-reset, which re-initializes GPIO
states to ROM POR values. Therefore, it is necessary to re-init GPIO
states once again based on board-level GPIO settings.
BUG=chrome-os-partner:58077
BRANCH=gru
TEST=Run `hibernate` on gru, wake, then run `bd99955_dump`. Verify
actual register values are printed rather than zeros.
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: Ib3eb1dd6aa264d00d42d8e386bfd1ef7f6cf7717
Reviewed-on: https://chromium-review.googlesource.com/395426
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
spi_transaction() can be called from motionsense, hooks, hostcmd,
console, and chipset tasks, so add a mutex to ensure an in-process
transaction isn't preempted by another transaction.
BUG=chrome-os-partner:57912
BRANCH=gru
TEST=On kevin, run "while true; do ectool motionsense odr 0 0; sleep 1;
ectool motionsense odr 0 1000000; sleep 1; done", verify watchdog crash
not encountered after 20 minutes.
Change-Id: I7ec495bab295dc03ce02372c20e5c7c5c196715d
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/391892
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
(cherry picked from commit eabdea443775fab834aaabbb7afae871306c7530)
Reviewed-on: https://chromium-review.googlesource.com/392226
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
The application may need to read/write/erase the flash memory,
but we not want console users to do so. This CL adds
CONFIG_FLASH_PHYSICAL, which allows the higher-level CONFIG_FLASH
to be undefined while still providing the chip-specific
flash_physical_* accessor functions.
There aren't many board.h files that needed changes, since
CONFIG_FLASH_PHYSICAL is enabled by default, just like CONFIG_FLASH.
BUG=chrome-os-partner:57408
BRANCH=none
TEST=make buildall; try on Gru with and without CR50_DEV=1
See that it still boots, updates, wipes, restores, etc. without
linking common/flash.o in the production image; and that the
flash commands are still there in the dev build.
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Change-Id: I7eb1bbcb414b1c70ee427c4fcb5cea899dbb9e93
Reviewed-on: https://chromium-review.googlesource.com/391188
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
The typical power consumption in sleep mode is 65uA.
IT83xx uses deep doze mode for low power idle task. The typical power
consumption in this state is 280uA (depends on EC tasks, it should be more)
and the wake up time is in microsecond. We are using deep doze mode for
low power idle task instead of sleep mode is because the wake up time
will be 6ms more.
While in system hibernate (EC sleep mode), EC won't wake up frequently so
we can keep the power consumption at 65uA.
Signed-off-by: Dino Li <dino.li@ite.com.tw>
BRANCH=none
BUG=none
TEST=- hibernate 0 [1|999999]
- hibernate [1|5|10|600]
- hibernate then press power button.
- hibernate then lid open.
Change-Id: I94884c010264f01ede4950c6bb1b0a444d7b1e6d
Reviewed-on: https://chromium-review.googlesource.com/383332
Commit-Ready: Dino Li <dino0303@gmail.com>
Tested-by: Dino Li <dino0303@gmail.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
Remove timeout to avoid fetching unknown instruction from e-flash
and causing exception.
Also fixed:
- To make sure immu(dynamic cache) is reset after a erasing/writing
operation.
- Verify function is in critical section.
Signed-off-by: Dino Li <dino.li@ite.com.tw>
BRANCH=none
BUG=none
TEST=console commands: "flasherase" and "flashwrite".
Change-Id: I0c84282ac4689cd762159071afae3efeea31d281
Reviewed-on: https://chromium-review.googlesource.com/380500
Commit-Ready: Dino Li <Dino.Li@ite.com.tw>
Tested-by: Dino Li <Dino.Li@ite.com.tw>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Since pretty much always, we've declared console commands to take
a "longhelp" argument with detailed explanations of what the
command does. But since almost as long, we've never actually used
that argument for anything - we just silently throw it away in
the macro. There's only one command (usbchargemode) that even
thinks it defines that argument.
We're never going to use this, let's just get rid of it.
BUG=none
BRANCH=none
CQ-DEPEND=CL:*279060
CQ-DEPEND=CL:*279158
CQ-DEPEND=CL:*279037
TEST=make buildall; tested on Cr50 hardware
Everything builds. Since we never used this arg anyway, there had
better not be any difference in the result.
Change-Id: Id3f71a53d02e3dc625cfcc12aa71ecb50e35eb9f
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/374163
Reviewed-by: Myles Watson <mylesgw@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
1. To assert keyboard IRQ GPIO pin instead of SERIRQ if keyboard data
ready to send.
2. Clear STATUS_PROCESSING bit in lpc_init() to avoid host waiting after
a sysjump.
3. Save and restore event masks while doing a sysjump.
Signed-off-by: Dino Li <dino.li@ite.com.tw>
BRANCH=none
BUG=none
TEST=1. keyboard work normally if host support this keyboard interrupt.
2. Software sync done and jumping to RW and boot to kernel.
3. EC generate SCI normally after a sysjump.
Change-Id: Ib0d9785106d4d4d21f8e9a6d1f0548f187fa7976
Reviewed-on: https://chromium-review.googlesource.com/372499
Commit-Ready: Dino Li <Dino.Li@ite.com.tw>
Tested-by: Dino Li <Dino.Li@ite.com.tw>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
If reset was caused by reset pin, we need this reset cause
for next sequence(recovery key).
Signed-off-by: Dino Li <dino.li@ite.com.tw>
BRANCH=none
BUG=none
TEST=To assert EC WRST pin and we will get the reset cause for
both power-on and reset-pin.
Change-Id: I0361091680a148df07cbbb8f4e53635dbf48fdee
Reviewed-on: https://chromium-review.googlesource.com/371798
Commit-Ready: Dino Li <Dino.Li@ite.com.tw>
Tested-by: Dino Li <Dino.Li@ite.com.tw>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
1. If one i2c transaction includes timeout and done events
at the same time, the transaction result will be timeout.
Fixed: The transaction is succeed instead of timeout.
2. The interrupt of i2c will not be enabled if an i2c write transaction
is split into two or more xfer.
Signed-off-by: Dino Li <dino.li@ite.com.tw>
BRANCH=none
BUG=none
TEST=1. Console commands:'i2cscan', 'i2cxfer', and 'battery'.
2. Use two or more i2c_xfer(the first with flag 'I2C_XFER_START'
and the last with flag 'I2C_XFER_STOP') to do a i2c write
transaction and no error.
Change-Id: Ieb2cb229748ac9504cf1636a2826bbb3097aa55c
Reviewed-on: https://chromium-review.googlesource.com/360762
Commit-Ready: Dino Li <Dino.Li@ite.com.tw>
Tested-by: Dino Li <Dino.Li@ite.com.tw>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
This workaround ensure that we can successfully get
register latch.
Signed-off-by: Dino Li <dino.li@ite.com.tw>
BRANCH=none
BUG=chrome-os-partner:55044
TEST=We simulate the delay time between first and second read,
and prove this method can avoid latch fail.
Change-Id: I7cafb53a8efbb2eee09af29d7365806dc0deb762
Reviewed-on: https://chromium-review.googlesource.com/358730
Commit-Ready: Dino Li <Dino.Li@ite.com.tw>
Tested-by: Dino Li <Dino.Li@ite.com.tw>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Default setting is at 48MHz.
For PLL frequency at 24MHz:
1. USB module can't work, it requires 48MHz to work.
2. SSPI clock frequency is divide by two.
Signed-off-by: Dino Li <dino.li@ite.com.tw>
BRANCH=none
BUG=none
TEST=1. uart, i2c, timer, and pd modules are function normally
at different PLL frequency settings.
2. use 'flashrom' utility to flash EC binary with different
PLL settings.
Change-Id: Iabce4726baff493a6136136af18732b58df45d7f
Reviewed-on: https://chromium-review.googlesource.com/347551
Commit-Ready: Dino Li <Dino.Li@ite.com.tw>
Tested-by: Dino Li <Dino.Li@ite.com.tw>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
The console adc command prints adc values in the
order they appear in hardware, however they are lableled
in the order they are enumerated in board.h, which is not
necessarily the same.
This prints the correct name and value pairs, and removes
the adc_read_all_channels function which is not otherwise
used.
BUG=chromium:571476
BRANCH=None
TEST="adc" command associates correct values with names now.
Change-Id: I688641953d20082224b4120eaefe0d634ad4c74c
Signed-off-by: Nick Sanders <nsanders@google.com>
Reviewed-on: https://chromium-review.googlesource.com/340892
Commit-Ready: Nick Sanders <nsanders@chromium.org>
Tested-by: Nick Sanders <nsanders@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
Before the change was made, the EC clock will be changed to 16MHz
when wake up from sleep mode, but we need it to keep at 8MHz.
This issue only occurs when EC sleep mode is implemented.
Signed-off-by: Dino Li <dino.li@ite.com.tw>
BRANCH=none
BUG=none
TEST=The 'IT83XX_ECPM_SCDCR3' register keeps default setting.
Change-Id: I206c5e657aba296684d60d6b30ed4071798dd96a
Reviewed-on: https://chromium-review.googlesource.com/345737
Commit-Ready: Dino Li <Dino.Li@ite.com.tw>
Tested-by: Dino Li <Dino.Li@ite.com.tw>
Reviewed-by: Randall Spangler <rspangler@google.com>
The 144-pins package IC(IT8320) supports these two GPIO groups.
Signed-off-by: Dino Li <dino.li@ite.com.tw>
BRANCH=none
BUG=none
TEST=1. Declare GPIO groups K/L in gpio.inc and using console commands
'gpioget'/'gpioset' to read/set GPIOs.
2. Choose four GPIO pins(GPIOK.0/1 and GPIOL.0/1)
and test interrupt functionally.
Change-Id: Ia618c314eeca1d061ffe172da762865f5df9b5c6
Reviewed-on: https://chromium-review.googlesource.com/345776
Commit-Ready: Dino Li <Dino.Li@ite.com.tw>
Tested-by: Dino Li <Dino.Li@ite.com.tw>
Reviewed-by: Randall Spangler <rspangler@google.com>
LPC access interrupt only enabled when EC entering deep doze mode. This
will reduce interrupt of LPC access. Also, this interrupt is always
enabled for LPC platform to support "CONFIG_LOW_POWER_S0".
Signed-off-by: Dino Li <dino.li@ite.com.tw>
BRANCH=none
BUG=none
TEST=Tested ectool command 'version' x 10000.
Change-Id: I9053c4018b38a8a852c3c6254e1fcde625f3fa3a
Reviewed-on: https://chromium-review.googlesource.com/336112
Commit-Ready: Dino Li <dino0303@gmail.com>
Tested-by: Dino Li <dino0303@gmail.com>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
There are more EC interrupts available.
Also, update interrupts that should be reserved.
Signed-off-by: Dino Li <dino.li@ite.com.tw>
BRANCH=none
BUG=none
TEST=Use 'task_enable_irq()' to enable new-added interrupts and
corresponding bit of interrupt enable register are set properly.
Change-Id: If1aecec7e208782b4580e33efb968095f30794fe
Reviewed-on: https://chromium-review.googlesource.com/344822
Commit-Ready: Dino Li <Dino.Li@ite.com.tw>
Tested-by: Dino Li <Dino.Li@ite.com.tw>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Using HOOK_PRIO_DEFAULT for peripheral initialization necessitates using
HOOK_PRIO_DEFAULT+1 for board-level code. Instead, use a
higher-than-default relative priority for peripheral initialization
outside of board.
BUG=None
TEST=Verify PWM and ADC are functional on kevin.
BRANCH=None
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: Ia8e90a7a866bdb0a661099dd458e3dfcaaa3f6bb
Reviewed-on: https://chromium-review.googlesource.com/342171
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
Previously the maximum number of deferred routines was specified by the
the default maximum number of deferred routines you had to override
this, and if you wanted fewer, you still payed the price of having the
defer_until array statically allocated to be the maximum size.
This change removes that define and instead creates the RAM state of
the deferred routine (the time to wait until to call the deferred) when
the deferred is declared.
Signed-off-by: Anton Staaf <robotboy@chromium.org>
BRANCH=None
BUG=None
TEST=make buildall -j
manually test on discovery-stm32f072
Change-Id: Id3db84ee1795226b7818c57f68c1f637567831dc
Reviewed-on: https://chromium-review.googlesource.com/335597
Commit-Ready: Anton Staaf <robotboy@chromium.org>
Tested-by: Anton Staaf <robotboy@chromium.org>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
This change is required for support 'CONFIG_LOW_POWER_S0'.
Signed-off-by: Dino Li <dino.li@ite.com.tw>
BRANCH=none
BUG=none
TEST=1. fanset 5555, EC enter doze mode only and fan control is functional.
2. fanset 0, EC will enter deep doze mode properly.
Change-Id: I3780b12ef54713258769616bfed0155c865c0725
Reviewed-on: https://chromium-review.googlesource.com/338750
Commit-Ready: Dino Li <dino.li@ite.com.tw>
Tested-by: Dino Li <dino.li@ite.com.tw>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
1. Always use wake-up control interrupt for keyboard KSI. This can also
wake-up EC from deep doze / sleep mode.
2. In keyboard ISR, we just clear interrupt status to prevent keyboard
interrupt can't be re-enabled.
(for example, a KSI interrupt wakes up keyboard scan task,
but keyboard_raw_read_rows() got 0.)
Signed-off-by: Dino Li <dino.li@ite.com.tw>
BRANCH=none
BUG=none
TEST=keyboard function is normally.
Change-Id: If8c292189c6133b179a63dedcb7a18abbc091312
Reviewed-on: https://chromium-review.googlesource.com/333865
Commit-Ready: Dino Li <dino.li@ite.com.tw>
Tested-by: Dino Li <dino.li@ite.com.tw>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
To ensure it8320's compatibility on the LPC platform, we need to
disable SPI slave interface (default enabled) so that LPC module
will function normally.
Signed-off-by: Dino Li <dino.li@ite.com.tw>
BRANCH=none
BUG=none
TEST=LPC module of it8320 works normally.
Change-Id: I259651b32f41ebae498e13bf07ebb68e5e520058
Reviewed-on: https://chromium-review.googlesource.com/328142
Commit-Ready: Dino Li <dino.li@ite.com.tw>
Tested-by: Dino Li <dino.li@ite.com.tw>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Before the change was made, the fan control timer keeps running
even all of the fans are off.
reproduce the problem:
1. fanset 3333
2. fanset 0
fan is disabled but fan control timer keeps running.
Signed-off-by: Dino Li <dino.li@ite.com.tw>
BRANCH=none
BUG=none
TEST=1. fanset 3333
2. fanset 0
both fan and timer are off.
Change-Id: Id38f3a4c64bbb36e8b32baefd285dbb0bf14e47e
Reviewed-on: https://chromium-review.googlesource.com/327870
Commit-Ready: Dino Li <dino.li@ite.com.tw>
Tested-by: Dino Li <dino.li@ite.com.tw>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
board_hibernate() may take alternate actions to place the chip into
hibernate, so inform the PD MCU that we're going to hibernate before
calling the function.
BUG=None
TEST=Run 'hibernate' on chell, verify that PD MCU goes to hibernate and
wakes when AC is attached.
BRANCH=glados
Change-Id: I71c12dcb416d54c79ac7d40e9bf430e268071fb2
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/327613
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Allow boards to take action (such as entering a custom low-power
hibernate-like state) before putting the chip into hibernate state.
BUG=chrome-os-partner:48835
BRANCH=glados
TEST=Manual with subsequent commit on chell. Verify board-level
hibernate callback is called when "hibernate" is run on EC console.
Change-Id: Ie1da044037a74ff8bce5c822f28ce837c62ceec0
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/324086
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
