Some hardware has an issue where the reset flags are lost on power cycle
because the EC backup ram loses power. This causes the flag to not power
on the AP (ap-off) to be lost.
In order to pass FAFT it is required that boards support this flag, so
this commit adds a workaround where the skylake chipset code will call into
the board to ask if it has working reset flags and if not it will skip the
PMIC reset if the "ap-off" flag has been set.
The "ap-off" flag is purely for testing, it is not possible for users to
do this without having access to the EC console. (which is currently not
possible at all with CCD unless you can also build a debug cr50 image)
BUG=b:38187362,b:35585876
BRANCH=none
TEST=manual testing on Eve: execute 'reboot ap-off' and ensure that the
AP does not power on. Also ensure that 'dut-control power_state:rec' works
as expected and does not power off at the recovery screen due to a power
button press.
Change-Id: If11e17179e9173509b9a6ae1ef0d94a50ba181d0
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://chromium-review.googlesource.com/514503
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
In chipset_handle_espi_reset_assert, check the state of SLP_SUS# signal
using power_get_signals instead of power_has_signals since we do not
care if the check fails. This avoids unwanted "power lost input" prints
on the EC console.
BUG=chrome-os-partner:63033
BRANCH=None
TEST=Verified that entry into S3 does not result in any "power lost
input" messages on EC console.
Change-Id: I88bc76a90b48e7c565423235f6e8431176ed4872
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/444262
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
In case there is a sudden power loss to PCH, then there are no eSPI VW
messages sent from the PCH to EC indicating power state transition into
S5. Instead, the eSPI compatibility spec defines such events as global
reset events. For global reset events, eSPI_Reset# signal is asserted
without SLP_SUS# being asserted. This acts as an indication to the EC
that there was a global reset event.
Add a callback chipset_handle_espi_reset_assert that takes any necessary
action whenever eSPI_Reset# pin is asserted. On skylake, it would check
if power button was being pressed and release the button.
BUG=chrome-os-partner:62014
BRANCH=None
TEST=Verified that apshutdown works as expected.
Change-Id: I409afa0d00faca55ae3aa577743cedac58d4d877
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/438935
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Add a config option that can be used by chipset to provide PMIC reset
using LDO_EN. This is required for ensuring that the AP is power
cycled properly. Implement the special pmic reset for skylake
chipsets.
BUG=chrome-os-partner:61883
BRANCH=None
TEST=Verified that reboot on EC console resets the AP and does not get
stuck in G3 on poppy.
Change-Id: I5f680fede5cb4effa86243f51edfdea09db4d975
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/431192
Reviewed-by: Duncan Laurie <dlaurie@google.com>
Grouping the Intel x86 power sequencing common code so that
the future chipset power sequencing implementation can make
use of the existing code.
BUG=chrome-os-partner:59141
BRANCH=none
TEST=make buildall -j
Manually tested on Reef & Chell.
System can boot to OS. S3, S5, hibernate are working.
Change-Id: I29dc208eacb3db47c640d028e9551ab3d8d4288c
Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/402272
Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Extracted Intel x86 power sequencing common code from skylake.c
and apollolake.c to implement common code for power sequencing.
BUG=chrome-os-partner:59141
BRANCH=none
TEST=make buildall -j
Reef can boot to OS. S3, S5, hibernate are working.
Change-Id: I73478fcabb24d6d98cd474bae3586ce5b02986fe
Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/406486
Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Prior x86 boards have had GPIO for toggling RCIN directly on the PCH,
although many likely had HW-assisted methods as well.
With eve we need to generate an eSPI Virtual Wire for RCIN, but in reality
software control over RCIN Virtual Wire is not available with the npcx EC,
so the legacy LPC interface for pulsing KBRST must be used instead as this
is the only way to generate RCIN.
This method will likely vary on different EC chips, but for skylake it
can just be abstracted into the LPC module.
BUG=chrome-os-partner:58666
BRANCH=none
TEST=successful 'apreset warm' on eve EC console
Change-Id: I7f9e7544a72877f75d05593b5e41f2f09a50e1c9
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/400037
Reviewed-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
This board function allows workarounds to be applied to a board after all
power rails are up but before the AP is out of reset.
Most workarounds for power sequencing can go in board init hooks, but for
devices where the power sequencing is driven by external PMIC the EC may
not get interrupts in time to handle workarounds.
For x86 platforms and boards which support RSMRST# passthrough this board
callback will allow workarounds to be applied despite the PMIC sequencing
by ensuring that the function is executed before RSMRST# deassertion.
BUG=chrome-os-partner:58666
BRANCH=none
TEST=test IMVP8 workaround on multiple eve boards
Change-Id: I0569494084000a4b1738ee18aafce5c96900dc4b
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/402591
Reviewed-by: Shawn N <shawnn@chromium.org>
Add the default undefined state for CONFIG_ESPI and rename
CONFIG_VW_SIGNALS to CONFIG_ESPI_VW_SIGNALS.
BUG=chrome-os-partner:58666
BRANCH=none
TEST=pass presubmit checks
Change-Id: I45242d545915c16bb46f751532a01ab937cee5f0
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/400032
Reviewed-by: Shawn N <shawnn@chromium.org>
Add virtual wire power signals support for skylake. By adding
CONFIG_VW_SIGNALS definition in board level driver, we can save three
GPIOs (SLP_S3/SLP_S4/CLK_RUN) on skylake platform.
Modified sources:
1. common.c: Add support for VW power signals.
2. skylake.c: Add upper func to get system sleep state through GPIOs or VWs.
BRANCH=none
BUG=none
TEST=make buildall; test boot up and shut down on eSPI POC of wheatley.
Change-Id: I0eae363dad8cec011eb32929a40701f19fde7e1a
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/366711
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Previously calls to hook_call_deferred were passed the function to call,
which was then looked up in the .rodata.deferred section with a linear
search. This linear search can be replaced with a subtract by passing
the pointer to the deferred_data object created when DECLARE_DEFERRED
was invoked.
Signed-off-by: Anton Staaf <robotboy@chromium.org>
BRANCH=None
BUG=None
CQ-DEPEND=CL:*255812
TEST=make buildall -j
Change-Id: I951dd1541302875b102dd086154cf05591694440
Reviewed-on: https://chromium-review.googlesource.com/334315
Commit-Ready: Bill Richardson <wfrichar@chromium.org>
Tested-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
Various voltage rails will be enabled / disabled by the PMIC when
GPIO_PMIC_SLP_SUS_L changes. We need to delay the disable of V0.85A
by approximately 25ms in order to allow V1.00A to sufficiently discharge
first.
BUG=chrome-os-partner:52047
TEST=Probe V1.00A and V0.85A during power-down, verify V1.00A discharges
faster than V0.85A.
BRANCH=glados
Change-Id: Ibbf4f989e1814e131dc373d2b5da9b6fa1ac9cce
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/337325
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
this is to move the existing code from chipset level to board level
since PseudoG3 is a board feature that required specific hardware.
BUG=none
BRANCH=glados
TEST=use hibernate command to enter PseudoG3
Change-Id: I309ef89e0ff7057ce46c634baa9791731a771984
Signed-off-by: Kevin K Wong <kevin.k.wong@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/327677
Reviewed-by: Shawn N <shawnn@chromium.org>
In the S0 <-> S3 transition, Coreboot sends EC messages to set/clear the
wake masks when the SMI is invoked. For S0ix, EC sets and clears the
wake mask via this patch.
These functions are directly invoked from the state machine transition states.
During S0ix entry, the wake mask for lid open is enabled. During S0ix exit,
the wake mask for lid open is cleared. All pending events are also cleared
BRANCH=none
BUG=chrome-os-partner:48834
TEST=test lidopen in S0ix
Signed-off-by: Archana Patni <archana.patni@intel.com>
Signed-off-by: Subramony Sesha <subramony.sesha@intel.com>
Change-Id: I52a15f502ef637f7b7e4b559820deecb831d818f
Reviewed-on: https://chromium-review.googlesource.com/320190
Commit-Ready: Divya Jyothi <divya.jyothi@intel.com>
Tested-by: Divya Jyothi <divya.jyothi@intel.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
If we are doing a cold reset or if Deep S5 is disabled we will go into S5
and need to be able to power up again, but we do not have enough information
to know what direction the sequencing may go from S5 (to G3 or up to S0).
So limit the RTCRST check to just the explicit G3->S5 path and let the normal
checking of SLP_S4 signal happen otherwise.
BUG=chrome-os-partner:49564
BRANCH=glados
TEST=pass FAFT testing finally
Change-Id: I202234e58281e6b007ad2b98396994222d0831b2
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/323087
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The power state machine goes through POWER_S5 state both when
sequencing up and down, but we only should check for it to
time out on the way up. In order to know what direction it
is going add a variable to indicate the direction.
On samus where this was done before it did not go through
POWER_S5 on the way down, instead going directly to POWER_S5G3
so I did not run into this same issue.
BUG=chrome-os-partner:49564
BRANCH=glados
TEST=successfully power down without the EC thinking it is
timing out and trying to reset RTC.
Change-Id: I1f53f3a252bdc2ec8c656e30b3de7f98aaa661a0
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/322898
Reviewed-by: Shawn N <shawnn@chromium.org>
In order to pulse RTC reset to the PCH when power sequencing exit fails we
need to watch for SLP_S4 to deassert and if it does not then assert RTCRST
using a board specific method. This is attempted up to 5 times before giving
up and staying in G3.
On skylake the RSMRST passthru needs to be honored when the task is woken up,
so while waiting call handle_rsmrst() if woken up early. This is needed
because it is RSMRST that actually tells the PCH to try and wake.
This is all wrapped in a config option and board specific method because not all
boards have a GPIO to control RTCRST and if they do they may not all use the
same method to assert it.
BUG=chrome-os-partner:49564
BRANCH=glados
TEST=manually tested on chell EVT:
First, ensure board sequences properly if everything is OK for a normal boot.
Next, modify handle_rsmrst() to not pass through the signal in order to
simulate being stuck in S5, and ensure that the EC attempts to assert RTCRST
and power up again 5 times before giving up and staying in G3.
Change-Id: Ia3c13069c92762b51beb682a19e5a074194a3c26
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/322724
Reviewed-by: Shawn N <shawnn@chromium.org>
x86 systems will auto-power-on when power is applied to the EC. When
the battery level is critically low, power-on is prevented, except when
the system is unlocked. So, when unlocked, some systems will
auto-power-on regardless of battery level, overcurrent the charger /
battery, and then repeat forever.
Prevent this reboot loop by ignoring auto-power-up when the battery is
critically low, regardless of system unlocked status.
BUG=chrome-os-partner:48339
TEST=Verify power-up is prevented on no-battery chell w/ donette. Then,
run 'powerbtn' on EC console and verify system powers on (and
overcurrents).
BRANCH=None
Change-Id: Ia631b5a8c45b42ec805e4a0c3f827929a0efd236
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/319187
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
During power up, system will wait at most CHARGER_INITIALIZED_TRIES
delay to check if battery percentage or negociated charger power can
meet minimum requirement. In some cases, it takes longer time(observed
negotiated to min power took 2 seconds). So increase
CHARGER_INITIALIZED_TRIES from 10 to 40 to give total 4 seconds delay.
BUG=chrome-os-partner:48339
BRANCH=none
TEST=Verified in Kunimitsu system, negotiation to 5V@3A is done within
retry/delay.
Change-Id: I18c5fc676076f8d37d0a5360543f54aa85f48f77
Signed-off-by: li feng <li1.feng@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/318652
Commit-Ready: Li1 Feng <li1.feng@intel.com>
Tested-by: Li1 Feng <li1.feng@intel.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
On assertion of SLP_S0, EC goes to S0ix while system is in Lucid sleep
and EC is eligable to enter heavy sleep idle task.
Wakeup from S0ix by lid open, any key press, power button or track pad
will be done by PCH block by asserting SLP_S0.
At S0ix, 1 msec pulse will be generated every 8sec and this signal
should be ignored since this is NOT S0ix entry/exit related and defered
interrupt for SLP_S0 were added.
BRANCH=master
BUG=none
TEST=in OS shell, run following commands.
Following command is valid with coreboot with S0ix patches.
"echo freeze > /sys/power/state"
then,
Measure EC power consumption and compare it with one in S0.
And on EC console, there should be NO periodic message, "power
state 4 = S0ix, in 0x001d" every 8 sec.
Change-Id: Ia9cf5256b1ad7234815d4b6dbe2b45788aaf49dd
Signed-off-by: Kyoung Kim <kyoung.il.kim@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/307947
Commit-Ready: Kyoung Il Kim <kyoung.il.kim@intel.com>
Tested-by: Kyoung Il Kim <kyoung.il.kim@intel.com>
Reviewed-by: Kyoung Il Kim <kyoung.il.kim@intel.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
Some boards may not have a USB2_ENABLE GPIO so we need each
board to do the USB power enable/disable in a board hook.
BUG=chrome-os-partner:46289
BRANCH=none
TEST=make -j buildall
Change-Id: I830cbaf41c118b2f74e23fa946a4187f6293a7d5
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/304397
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Enable the support for limiting the inrush current by routing the PCH_SLP_SUS
through EC gpio PMIC_SLP_SUS which allows the DUT to boot on charger without
the battery / dead battery. This is applicable to Kunimitsu FAB4 only.
Enabling the Glados patch for Kunimitsu FAB4.
Change-Id: I55de857f7006777640f7853b7bde98ba97e8bd13
Reviewed-on: https://chromium-review.googlesource.com/287378
BUG=chrome-os-partner:44706
TEST=FAB4 prototype boots to UI without battery / dead battery.
BRANCH=none
Change-Id: Ie81cdf3c59fc02d6d59dd06ca321705ca06e7b88
Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/296521
Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
On skylake the apshutdown command holds the power button asserted until
the power state machine decides to deassert the power button. Previously
this check was taking place in G3 state. As such when the board waited
in S5 for 10 secs one couldn't re-power on the system. To alleviate that
move the logic for power button deassertion into the S5 state.
BUG=chrome-os-partner:44532
BRANCH=None
TEST=Used apshutdown. When device got to S5 power noted another
powerb command would bring the system back up instead of waiting
to enter G3 power state.
Change-Id: I9989b27bd48819d7c3e5efd071b0327c38fe91e2
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/295198
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
The internal keyboard and trackpad must be disabled in tablet mode to
prevent unwanted input.
BUG=chrome-os-partner:44305,chrome-os-partner:40849
TEST=Manual on Glados. Boot system with lid open, verify that keyboard
is functional and ENABLE_TRACKPAD is high. Swing lid to tablet mode,
verify that keyboard is not functional and ENABLE_TRACKPAD is low.
BRANCH=None
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: I9f250ae82963c8b497de991b6cce52c86841d08a
Reviewed-on: https://chromium-review.googlesource.com/295206
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
BUG=none
TEST=Used "shutdown -h now" Kernel console command to test on Kunimitsu.
With only battery after 1 hour, device enters to Pseudo G3 and the
V3p3A is off. With AC connected, device is in G3.
BRANCH=none
Change-Id: I955662eb69ac608e9b2d12bdcfbc1258ca83f3a5
Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/292976
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
There are a number issues with the current skylake power
sequencing. First, SLP_SUS_L was not being honored from
the chipset when a deep S5 or S3 was requested. Additionally
the BATLOW_L signal was being used to block the chipset from
waking which caused a race in waking from deep S5 that required
an additional pulse of the PCH_WAKE_L signal instead of the
chipset seeing the power button event. Another issue is that
POWER_S5 state was being completely bypassed so any global
resets that brought down SLP_S4_L caused the state machine
to enter into G3 state.
The code was changed to remove BATLOW_L usage, PCH_WAKE_L
in the POWER_G3S5 state, and SLP_SUS_L is honored in the
non POWER_S5G3 and POWER_G3 state. That allows SLP_SUS_L
pass-thru to work on glaods. Lastly the code was reorganized
to accomodate the above change without sprinkling them
throughout the state transitions.
BUG=chrome-os-partner:44081
BUG=chrome-os-partner:44082
BUG=chrome-os-partner:43475
BRANCH=None
TEST=Built and booted glados. Deep S3 and S5 wakes work. Fresh
flash plus a global reset doesn't bring the system down to G3.
Change-Id: Id1d7af1b6a733a9db5aad584950da8ab5898ea83
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/293844
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
The system will not wake from Deep S5 if BATLOW# is asserted,
so wait for that to deassert, then pulse the wake pin and wait
for SLP_SUS_L to deassert.
BUG=chrome-os-partner:43545,chrome-os-partner:44079
BRANCH=none
TEST=verified on P2 board
Change-Id: I3b36159b574d418c9b79c478d0a41f753474fa6a
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/293595
Reviewed-by: Shawn N <shawnn@chromium.org>
Switch to V2 glados as the default, and remove support for V1.
BUG=chrome-os-partner:43075
TEST=`make buildall -j`
BRANCH=None
Change-Id: I58f33225177d259916e8877084c2c431922e7bc5
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/293303
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Inhibit AP power-on through the BATLOW pin, even if the system is
unprotected, until our charger and current limit are initialized.
Note that this feature is only functional on glados v2 since other
skylake boards do not have BATLOW connected.
BUG=chrome-os-partner:41258
TEST=Manual on glados v1 with rework. Remove battery and attach Zinger.
Verify EC powers on and AP doesn't boot. Run `powerbtn`, verify that AP
boots. Remove all power and attach battery, verify that EC powers on
and AP boots. Also verify compilation on glados v2.
BRANCH=None
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: I55de857f7006777640f7853b7bde98ba97e8bd13
Reviewed-on: https://chromium-review.googlesource.com/287378
Changes for glados proto 2 build. These changes are behind GLADOS_BOARD_V2,
which is not defined by default in order to support existing boards.
BUG=chrome-os-partner:42933
TEST=Verify that Glados v1 board continues to boot AP. Verify
compilation on GLADOS_BOARD_V2.
BRANCH=None
Change-Id: I68634f95f94d3d37f18d676c01219f92b6ddfc45
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/287291
Reviewed-by: Alec Berg <alecaberg@chromium.org>
BUG=none
TEST=Enabled the config and tested on Kunimitsu.
Enter "shutdown -h now" form the Kernel console.
Device goes to Sleep mode in G3 and charger LED turns off.
BRANCH=none
Change-Id: I962018dcfac2998ee0a11784adeceb09931b930d
Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/286781
Reviewed-by: Shawn N <shawnn@chromium.org>
- Disable USB, wireless and audio power rail when powering down from S3
- Disable sensor power rail and display backlight when powering down
from S0
BUG=chrome-os-partner:42104
TEST=Manual on Glados. Boot AP, verify that display backlight and USB
are functional.
BRANCH=None
Change-Id: I2879f57db555753b280e785df3d2cc967c152f21
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/285545
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Alec Berg <alecaberg@chromium.org>
According to spec, RSMRST shouldn't be deasserted until 10ms after power
signals become active.
BUG=chrome-os-partner:41556
TEST=Manual on Glados. Verify that AP boots to S0 on power-on, goes to
G3 on apshutdown, and back to S0 on powerbtn.
BRANCH=None
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: I0acc897fff7c18ad83fc87734569ec7639ae5cf4
Reviewed-on: https://chromium-review.googlesource.com/280571
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
If the AP is already shutdown, apshutdown would previously power the AP
up with a power press. Fix this by making sure we're not already in G3
before triggering the power press.
BUG=chrome-os-partner:40677
TEST=Run 'apshutdown' on glados while in G3, verify that AP does not
power up.
BRANCH=None
Change-Id: I8b898b034dcf40f0acef4fb6098af0aebba566c6
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/277400
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Holding the power button is currently the best known way to bring the AP
back to a state where it is shutdown and not powered.
BUG=chrome-os-partner:40826, chrome-os-partner:40677
TEST=Run `apshutdown` on glados, verify that power state machine transitions
to G3 after several seconds. Run `powerbtn`, verify that state machine
transitions back to S0.
BRANCH=None
Change-Id: Ia799c5f199127f31bd24907b93946c6289d381f8
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/275060
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This change is necessary to ensure power-up of edge-case Skylake parts.
BUG=chrome-os-partner:40677
TEST=Manual on Glados. Boot system to S0, run "i2cxfer r 4 0x60 0x38",
verify that 0x7a is read.
BRANCH=None
Change-Id: Id9e62731aaa75fb2357a05d898ba2d4d28f87d9e
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/274114
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
PCH_SLP_SUS_L can take up to 29ms to be deasserted after power-on or
RTC reset.
BUG=chrome-os-partner:40677
BRANCH=None
TEST=Manual on glados. Power board, verify that state machine
transitions to S0. Run "reboot" on EC console, verify that state machine
again transitions to S0.
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: I3f6e89eee1190a3fe84fdc7d939c05dfe5b94953
Reviewed-on: https://chromium-review.googlesource.com/274077
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Always enable these signals to help debug power sequencing. We'll need
to revert this change later.
BUG=chrome-os-partner:40677
BRANCH=none
TEST=sequence to S0 on glados and stay there
Change-Id: Ia845532fe7aed71bcb42b4ca6a9bfa20aa9e3e00
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/273900
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
This change will help us to debug power sequencing and will likely need
to be reverted later.
BUG=chrome-os-partner:40677
BRANCH=none
TEST=sequence to S0 on glados and stay there
Change-Id: I85d1f0f97a3c93cf26c766a749feb23f9cf4ac62
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/273680
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Debounce time for the GPIO SYS_RESET_L is 16ms hence increased the time
delay between SYS_RESET_L pin toggling to 20ms.
BUG=chrome-os-partner:40246
TEST=Tested "apreset cold" EC console command on Kunimitsu
BRANCH=none
Change-Id: If17229ce485de708b550ec84939e2696e451cb0c
Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/270776
Reviewed-by: Randall Spangler <rspangler@chromium.org>
