Decrease the time to wake up from deep sleep when not using
LFIOSC (when using PIOSC in deep sleep). This helps keep us
in deep sleep longer and therefore save power.
BUG=none
BRANCH=samus
TEST=Load onto samus and run for a couple of hours, varying from
S0 to S5, with and without EC. Use idlestats to check that closest
we get to missing deadline is 86us away.
Change-Id: I3eee908e9f42a1c5b549e93d63588a3cb6e29a5d
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/238412
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Check the flash protection at startup, if the RDP is still at level 0
(no read protection) or if the RO partition is not write protected :
- set the write protection on the first 16KB of flash (4 LSB of WRP0)
- push the RDP to level 1, so SWD/serial monitor needs to fully erase
the part before re-writing the code or the write-protection.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=samus
BUG=chrome-os-partner:34935
TEST=dump the content of the option bytes.
Change-Id: I11af64365a6fbc34327b2e463eb8e2d369ffacd2
Reviewed-on: https://chromium-review.googlesource.com/238262
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
Trybot-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Use the PORT event for keyboard inputs.
Make a column mask for driving all outputs at once.
BUG=chrome-os-partner:34477
BRANCH=none
TEST=Used hadoken and the Ryu base keyboard to check that the keys are all
functional, that the keyboard polls while keys are held, and that it waits
for interrupts when the keys are released.
Signed-off-by: Myles Watson <mylesgw@chromium.org>
Change-Id: Ie1dd1ca17b21ed76b2d412bf25fe87e45c5ba757
Reviewed-on: https://chromium-review.googlesource.com/234394
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Tested-by: Myles Watson <mylesgw@chromium.org>
Commit-Queue: Myles Watson <mylesgw@chromium.org>
Add structures to keep track of which interrupts are associated with which pin.
There are IN[] events, and one PORT event. The IN[] events have an array.
The PORT event can be used for multiple pins at once.
BUG=chrome-os-partner:34477
BRANCH=none
TEST=Configured pins as IN[] events and PORT events, and saw console output.
Signed-off-by: Myles Watson <mylesgw@chromium.org>
Change-Id: I129a6586dca4d5eb141c86fd92fbfbb70080bc2a
Reviewed-on: https://chromium-review.googlesource.com/234392
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Tested-by: Myles Watson <mylesgw@chromium.org>
Commit-Queue: Myles Watson <mylesgw@chromium.org>
Updated to use parameters for GPIOTE_OUT, GPIOTE_IN, and GPIOTE_CONFIG
Updated with NRF51_GPIOTE_IN_COUNT to remove the magic number.
BUG=chrome-os-partner:34477
BRANCH=none
TEST=Configured IN[] events and PORT events and checked that they triggered
events and wrote to the console.
Signed-off-by: Myles Watson <mylesgw@chromium.org>
Change-Id: I2021ecbee67c39571f277c97082378dce4de024f
Reviewed-on: https://chromium-review.googlesource.com/234289
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Tested-by: Myles Watson <mylesgw@chromium.org>
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Commit-Queue: Myles Watson <mylesgw@chromium.org>
Add support for alternate functions for nrf51.
Add more register definitions for the nrf51.
Use assertions for conditions that should never happen.
Use BUILD_ASSERT to keep the sources in sync.
Add three more GPIOs to hadoken.
BQ27621_GPOUT - Configurable output from the fuel gauge.
LID_PRESENT_L - The input for the hall sensor.
IND_CHRG_DISABLE - The output to control inductive charging.
BUG=chrome-os-partner:34477
BRANCH=none
TEST=Used gpioget and magnets for LID_PRESENT_L
Used fuel gauge console commands to trigger BQ27621_GPOUT
Tested the assertions with gdb
Signed-off-by: Myles Watson <mylesgw@chromium.org>
Change-Id: I508f79ae45127104fa14f9f75fbf545f226387e4
Reviewed-on: https://chromium-review.googlesource.com/234286
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Tested-by: Myles Watson <mylesgw@chromium.org>
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Commit-Queue: Myles Watson <mylesgw@chromium.org>
With the type-c connector, it's common for VBUS to make contact before
D+/D-, which can lead to charger misdetection. To work around this, add
a 200ms delay and trigger re-detection when a charger is inserted. This
should fix most misdetects due to unintentional slow plug (though it's
still possible to misdetect if insertion is deliberately very slow).
BUG=chrome-os-partner:34584
TEST=Manual on Samus. Plug in Apple charger 20 times, verify that it is
always detected correctly. Deliberately plug in slowly, verify it is
detected as 500mA SDP port. Repeat tests with various other CDP / SDP
ports to verify detection never over-currents and always indicates a
charger is plugged (or not plugged) correctly.
BRANCH=Samus
Change-Id: I8a776f516d8e7f0cedcb9d8579239eba641cab09
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/237241
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Add EC2I control module for emulation board.
The EC2I bridge enables the EC to access the host controlled
module registers (e.g., host configuration module(PNPCFG) and SWUC)
Signed-off-by: Dino Li <dino.li@ite.com.tw>
BRANCH=none
BUG=none
TEST=EC2I read: Read a logical device page, the results are correctly.
EC2I write: Initialize PNPCFG success.
Change-Id: I900450d4a8c49182c438b69b5e738c12dc437fe4
Reviewed-on: https://chromium-review.googlesource.com/230410
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Commit-Queue: Dino Li <dino.li@ite.com.tw>
Tested-by: Dino Li <dino.li@ite.com.tw>
STM32 seems to actually measure the rising and falling time of the I2C clock, so
if one uses a really small resistor the timing will go faster than with a bigger
resistor.
This commit makes it so the I2C frequency is limited to max 100kHz (respecting
the spec) no matter what size resistor (essentially we assume 0 rise and fall
times). While this will make stuff slower on boards with big resistors (where
they might have been under 100kHz anyway) this is the best compromise (since the
spec does not specify min frequency) without getting config defines for the
fall/rise times.
The TSCLH of some boards would be too short with the recommended timing
settings from spec, so increases the TSCLH would be better for everyone.
This patch does not touch the higher frequencies since the rise and fall times
do contribute a lot more to clocks, if the same method was used for those
frequencies, the speeds would have to be a lot slower.
BUG=chrome-os-partner:34375
BRANCH=None
TEST=on any EC, note how frequency does not go above 100kHz
TEST=As per tSCL = tSYNC1 + tSYNC2 + { [(SCLH+1) + (SCLL+1)] x
(PRESC+1) x tI2CCLK } from datasheet
Change-Id: Ibbeecac7f3da1b22d2ba3bca29ee3c17bfe997f5
Signed-off-by: Chris Zhong <zyw@rock-chips.com>
Signed-off-by: Alexandru M Stan <amstan@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/234077
Reviewed-by: Randall Spangler <rspangler@chromium.org>
When the EC is busy enough to start missing RX characters an ORECF might come
(Overrun error), we never check for this bit, so that means the interrupt
handler will be called in a loop because it never clears that bit.
This disables the overrun detection feature.
BUG=chrome-os-partner:33451
TEST=get firmware to poll the EC for keyboard presses, type really fast on the
keyboard, note how system does not watchdog reset anymore but loses the
occasional character instead.
BRANCH=None
Change-Id: I711483768e4ba80aaeb4a324c7dee790b3a23682
Signed-off-by: Alexandru M Stan <amstan@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/236088
Reviewed-by: Randall Spangler <rspangler@chromium.org>
According the STM32L RM, when writing to RCC_CFGR to change HSI or MSI
clock source, SWS bits of RCC_CFGR register have to be checked if the
new clock source is taken into account. Also, when writing ACC64 bit and
LATENCY bit to FLASH_ACR register, those bits have to be checked too.
Also changed in this CL is to disable MSI if HSI is enabled, and disable
HSI if MSI is enabled.
BUG=chrome-os-partner:32936
BRANCH=none
TEST=passed suspend_stress_test on big, blaze and nyan
Change-Id: I3ec660d149ecdec3ca3097239612bf2c542d0548
Signed-off-by: Yen Lin <yelin@nvidia.com>
Reviewed-on: https://chromium-review.googlesource.com/234490
Reviewed-by: Kary Jin <karyj@nvidia.com>
Tested-by: Kary Jin <karyj@nvidia.com>
Reviewed-by: Andrew Bresticker <abrestic@chromium.org>
(cherry picked from commit 400d9dca8c41f74cf0c2587e881707b80bb17d3d)
Reviewed-on: https://chromium-review.googlesource.com/236050
Added check for collision just before transmitting on CC line.
To check for collision, RX monitoring is left on all the time
(except when in the act of receiving or transmitting, or in
between receiving and sending a goodCRC), and a
simple check for RX transmission started is used to see if the
CC line is idle or not.
RX monitoring is also changed to only trigger on 3 edges within
20us, as per the PD spec.
When a collision is detected by seeing that CC is not idle, the
transmitting packet is dropped.
BUG=chrome-os-partner:30135
BRANCH=samus
TEST=load onto samus and zinger. make sure we negotiate and make
sure custom VDMs succeed. enabled pings and made sure we stay
alive with pings for a few min.
Also added code to pd_rx_handler to toggle a test point on EVT
board to verify the timing of when we get RX interrupts:
Change-Id: I22d172163319437d3d901e019eda79d4d592f6b8
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/226118
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Ryu sensor hub has asymectric RO/RW images. The first one is very limited
(not i2c master, no sensor drivers, gesture recognition).
Image size is alter to offer more space for the RW firmware image,
compiled with ryu_sh board.
To write RO image and basic RW image:
flashrom -V -p ec:type=sh,block=0x800 --fast-verify -w /tmp/ryu_sh_loader/ec.bin
To write the expected RW image:
flashrom -V -p ec:type=sh,block=0x800 --fast-verify -w -i EC_RW:/tmp/ryu_sh/ec.bin
BRANCH=ToT
BUG=chrome-os-partner:33908
CQ-DEPEND=CL:231970,CL:233233
TEST=load on Ryu, confirmed limited operation.
Change-Id: Ib976e2b048935adfb9b2b072c071db5be2bc1c09
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/231984
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
The task based approach made sense when it looked like
there would be a case closed debugging task to handle
multiple bridges (SPI/I2C/USART...). I'm not convinced
anymore that that task will be needed, so this
simplification seems good.
Signed-off-by: Anton Staaf <robotboy@chromium.org>
BRANCH=None
BUG=None
TEST=make buildall -j
Change-Id: Ic431c287c28d10252246fe9f507d9c5fcc64a077
Reviewed-on: https://chromium-review.googlesource.com/232733
Tested-by: Anton Staaf <robotboy@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Commit-Queue: Anton Staaf <robotboy@chromium.org>
This allows the USB SPI bridge to be controlled from the
host at a larger timescale than a single SPI transaction.
This allows the host to signal that many transactions
will take place and that the device should keep the SPI
bridge enabled across them. This allows the device to
hold the AP or other possible user of the SPI bus in
reset while the bridge is enabled.
Signed-off-by: Anton Staaf <robotboy@chromium.org>
BRANCH=None
BUG=None
TEST=make buildall -j
Change-Id: Ifd6f96b0ff47f35d853735d44e255a205b0e677a
Reviewed-on: https://chromium-review.googlesource.com/232732
Tested-by: Anton Staaf <robotboy@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Commit-Queue: Anton Staaf <robotboy@chromium.org>
Build the hardware version string from the register definitions,
so I no longer forget to update it.
Check it at runtime against the build version registers.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=none
BUG=none
TEST=On the console command line,
type "version" and see the following string:
"Chip: g cr50 A1 20141203_224409"
Change-Id: I6d902780d42f2dd18a57ccc08fd4ba4fee5ebc7c
Reviewed-on: https://chromium-review.googlesource.com/233582
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
Trybot-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
- record and display reset cause
- add the hard reset option
- add the scratchpad to store values across reboots.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=none
BUG=chrome-os-partner:33818
TEST=On the console command line, chech the "[Reset cause: xxx]" string
- for the initial reset cause
- use "waitms 4000" to trigger a watchdog reset
- use "reboot soft"
- use "reboot hard"
The "utils" test is now building and passing.
Change-Id: I68c7096e5b7bfd102be89fd8eef6fe20da37a6f8
Reviewed-on: https://chromium-review.googlesource.com/233581
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
Trybot-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Implement a driver to trigger a watchdog reboot if we are stuck
somewhere. Also display a nice warning when we reach half of the
watchdog period.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=none
BUG=none
TEST=On the console, type "waitms 500" and see nothing,
type "waitms 2000" and see the watchdog warning.
Type "waitms 4000" and see the warning, the platform rebooting.
Change-Id: Iac5d0100febd5eab1ae6cfac5a47ff728ebda3a6
Reviewed-on: https://chromium-review.googlesource.com/233430
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Trybot-Ready: Vincent Palatin <vpalatin@chromium.org>
We were losing timer events because usecs_to_ticks(deadline) was
clipping the value when deadline was larger than 0x08888888 (deadline is
a timestamp rather than a delay).
The computation of the timer deadline has been modified to avoid the
clipping issue.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=none
BUG=chrome-os-partner:34347
TEST=run on Cr50 with the watchdog activated and no longer see watchdog
warnings.
Run the "timer_calib" test and see that the 1s sleep is 1000038 us :
make BOARD=cr50 tests
fhl ../build/cr50/timer_calib/timer_calib.RO.hex
Change-Id: Id2200a89eb1b72099e536291af321609b24b4777
Reviewed-on: https://chromium-review.googlesource.com/233531
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
Trybot-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
CL to migrate the flashing VDMs from zinger's custom vdm to
common/usb_pd_flash.c such that other updateable type-C devices can
share.
Additionally adds gaskets to call standard runtime flashing facilities
for USB-PD devices using it.
Signed-off-by: Todd Broch <tbroch@chromium.org>
BRANCH=samus
BUG=chrome-os-partner:31192,chrome-os-partner:31193
TEST=manual,
Try following:
1. From samus_pd console w/ zinger in port 1
pd 1 flash version
pd 1 flash reboot
pd 1 flash info
2. From samus linux prompt w/ zinger in port 1
ectool --name cros_pd flashpd 1 1 <zinger RW payload>
Reading 16384 bytes from
/usr/local/zinger_v1.1.2528-d809e42.ec.RW.bin...
Erasing expected RW hash
Rebooting
Erasing RW flash
Writing RW flash
Rebooting PD into new RW
Complete
3. Repeat 1&2 above on hoho & dingdong.
Change-Id: I018055fa9de128f937c57debdc21dea026137bcf
Reviewed-on: https://chromium-review.googlesource.com/231835
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Tested-by: Todd Broch <tbroch@chromium.org>
Commit-Queue: Todd Broch <tbroch@chromium.org>
Until we implement a proper reset of the microcontroller,
add a reset of the Cortex-M3 CPU core in system_reset() in order to
avoid getting stuck in a weird loop if we get a panic.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=none
BUG=none
TEST=trigger a data abort and verify we are not going into a panic loop.
Change-Id: Ie046379e6a9469bd683fa774cdc9abb10a14e8f1
Reviewed-on: https://chromium-review.googlesource.com/233109
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
A non-zero error code returned by the callback causes EP0 to STALL.
This is the common mechanism used in USB to indicate an error while
processing a control request. This simplifies the implementation
of interface callbacks.
Signed-off-by: Anton Staaf <robotboy@chromium.org>
BRANCH=None
BUG=None
TEST=make buildall -j
Change-Id: I89ceb4892f9f810fcaf6e975e6982fc5b2ae447b
Reviewed-on: https://chromium-review.googlesource.com/232368
Reviewed-by: Anton Staaf <robotboy@chromium.org>
Commit-Queue: Anton Staaf <robotboy@chromium.org>
Tested-by: Anton Staaf <robotboy@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
When using gpio_set_flags_by_mask() to modify a GPIO pin setting, the
former code was not able to revert an open-drain GPIO into push-pull
mode (the other way round was working). Fix it to be able to transition
in each direction.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=all
BUG=none
TEST=on Twinkie, run "tw res none RP3A0" then "adc" and see the RP3A0
GPIO set to 1 and pulling the CC to 3.3V.
Change-Id: Ic2d8ed95ea21b21d261a12ba298931d8bd5e6919
Reviewed-on: https://chromium-review.googlesource.com/231150
Reviewed-by: Vic Yang <victoryang@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
The latest gcc picked up a couple out-of-bounds issues, so
"make buildall" was failing. This fixes them.
BUG=none
BRANCH=ToT
TEST=make buildall -j
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Change-Id: Idcd6a3358ecbb0e0d2a610e1cd28c2f138ce520b
Reviewed-on: https://chromium-review.googlesource.com/231156
Reviewed-by: Randall Spangler <rspangler@chromium.org>
For USB console, we wait for USB host to grab the data before writing
the next chunk of characters. However, if the USB peripheral is
disabled, the current implementation is confused as to whether the host
has grabbed the previous chunk of data.
Fix this by explicitly checking for USB peripheral enabled.
BRANCH=ryu
BUG=None
TEST=Boot on Ryu and check console isn't slow.
Signed-off-by: Vic Yang <victoryang@chromium.org>
Change-Id: I438c95835e56707b7ca1796734f2e47062799f44
Reviewed-on: https://chromium-review.googlesource.com/231115
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
This is fairly large change set to accomodate a new hardware
release. There are enough differences to require refactoring the
registers.h file. Autogenerated constants are now in gc_regdefs.h
and all constant names begin with GC_, while register names are
defined in registers.h and begin with GR_.
Yes, I know the new header files are wider than 80 chars, but we
agreed that was okay in some cases if it makes them more readable
(see commit 3500c28).
BUG=chrome-os-partner:33423
BRANCH=none
TEST=make buildall -j
Build and run on the development board.
Change-Id: I21bd88c490f4f359ad17b5af9d17d8caca8dc9e4
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/230513
Reviewed-by: Sheng-liang Song <ssl@chromium.org>
Add commands to send PD packets and to tweak individual parameters (TX
clock frequency, RX detection threshold, resistors on CCx).
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=none
BUG=chrome-os-partner:28337
TEST=verify that the PD sniffing is still working by dumping traffic
between Zinger and Samus.
Connect Twinkie to Zinger, set Rd by using "tw res NONE RD" and see VBUS
going to 5V (reading it using "ina 0").
Send a BIST mode 2 request using the following command :
tw send 2 0x1043 50000000
and see the other end starting sending BIST.
Change-Id: I3c8ddf858435ac1c17a43f59351bbaa69603a209
Reviewed-on: https://chromium-review.googlesource.com/227778
Reviewed-by: Todd Broch <tbroch@chromium.org>
Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Extend the Zinger runtime to take into account the disable_sleep()
issued by the USB protocol stack and avoid going into deep-sleep while
connected.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=samus
BUG=none
TEST=connect Zinger to a PD power sink (Twinkie) and monitor the stop
mode entry/exit on a GPIO.
Change-Id: I04e35fdd65f3be3da7a4304dc1a92e6268930888
Reviewed-on: https://chromium-review.googlesource.com/230340
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Allow to use larger RSA keys by setting CONFIG_RSA_KEY_SIZE to 4096 or
8192 rather than using the default 2048-bit size.
It's mainly for benchmarking purpose right now as we don't have the RAM
to store the 3x key size buffer and the flash space for the public key
structure.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=samus
BUG=none
TEST=build Zinger with CONFIG_RSA_KEY_SIZE equals to 4096 and run it.
Change-Id: I9839121bf158d0a30dde1e48d875f345191bfec2
Reviewed-on: https://chromium-review.googlesource.com/228925
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
It's really annoying to have to type two different commands. If I
want to read a location and then write it and then read it back
(which often happens when poking at hardware), then this:
rw 0x40570008
rw 0x40570008 14
rw 0x40570008
is much easier to enter than this:
rw 0x40570008
ww 0x40570008 14
rw 0x40570008
The "ww" command is still there, if you're really attached to it.
BUG=none
BRANCH=none
TEST=manual
Tried the example above. It worked.
Change-Id: I2302ed60df3dd3ec2224afa7c32d997bd2468ec1
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/229660
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Implement the API expected by common/timer.c
BUG=chrome-os-partner:33699
BRANCH=none
TEST=manual
Run the "gettime" and "timerinfo" and "taskinfo" and "waitms"
commands. Compare the elapsed time with the real world. They seem
to match.
Change-Id: Ie5acae76780ee09e7dfb6cc0282de25f8063e96f
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/229642
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
This enables forwarding of the local PD/EC console
over debug USB. It gates the console functionality
based on the CCD mode that is set.
Signed-off-by: Anton Staaf <robotboy@chromium.org>
BRANCH=None
BUG=None
TEST=make buildall -j
Enable partial CCD mode on ryu and verify that it is
enumerated by the host correctly, but doesn't respond
to console input, and doesn't generate output.
Enable full CCD mode on ryu and verify that it is
enumerated and that the console works as expected.
Verify that the console still works by default on the
discovery-stm32f072 board.
Change-Id: I0325ce9689486c41387d6075330be1d7d42f1d42
Reviewed-on: https://chromium-review.googlesource.com/229342
Reviewed-by: Anton Staaf <robotboy@chromium.org>
Commit-Queue: Anton Staaf <robotboy@chromium.org>
Tested-by: Anton Staaf <robotboy@chromium.org>
Previously enabling USB would automatically (using an
init hook) initialize the USB peripheral. This would
take over the GPIO lines assigned to the USB module.
This is not OK on Ryu for Case Closed Debug because it
interferes with the AP's access to the USB 2.0 lines
even when not in Case Close Debug mode.
This change adds a configuration option to inhibit this
default initialization of the USB peripheral. It also
renames the existing CONFIG_USB_INHIBIT to
CONFIG_USB_INHIBIT_CONNECT now that there are two
possible inhibitions.
Signed-off-by: Anton Staaf <robotboy@chromium.org>
BRANCH=None
BUG=None
TEST=make buildall -j
Enable console on ryu_p2 and discovery-stm32f072 board
Verify that it works on both
Change-Id: I6734357131b4356e3d4164349d6c74deac196ce5
Reviewed-on: https://chromium-review.googlesource.com/229138
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Commit-Queue: Anton Staaf <robotboy@chromium.org>
Tested-by: Anton Staaf <robotboy@chromium.org>
