These boards are using the OPT3001 ALS. Enable the drivers for them as
well as the motionsense stack.
BUG=b:70290036, b:69140267
BRANCH=None
TEST=Flash meowth and zoombini; verify that they still boot okay.
Change-Id: Iddbf0af5cc01973999703de4a75ad461bc6a025f
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/833168
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Gwendal Grignou <gwendal@chromium.org>
Typically this routine runs on low priority hook task.
A pre-emption by a higher priority task might be mistaken for timeout.
Double check the transfer done status after the timeout time has passed.
Also clear the TXDONE status before starting a fresh transaction to make sure
we wait for the current transaction to complete; an errand TXDONE status
at start of the transaction will pre-empt waiting for the current transaction
and return stale data.
BRANCH=none
TEST=mn50 stress test fails within minutes vs. now stable.
Main test component is higher priority console task
that does intermittent compute during usb-spi transfers.
Change-Id: Ide4390e42d3957bc45eea8160617a52dd31ed866
Reviewed-on: https://chromium-review.googlesource.com/849662
Commit-Ready: Marius Schilder <mschilder@chromium.org>
Tested-by: Marius Schilder <mschilder@chromium.org>
Reviewed-by: Marius Schilder <mschilder@chromium.org>
Reviewed-by: Nagendra Modadugu <ngm@google.com>
Reviewed-by: Nick Sanders <nsanders@chromium.org>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
All shipping products will have board ID >= 8, so the board ID
strap 3 will never be left floating. In particular, board ID 8-15
will have an external pull-down on that pin, so leaving the
internal pull-up enabled is detrimental to power.
BUG=b:64503543
BRANCH=none
TEST=Boot poppy rev6.
Change-Id: I810b2a68ab8d35e9cea6fa18f1eeafa10e7039ea
Signed-off-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/845240
Tested-by: Ruben Rodriguez Buchillon <coconutruben@chromium.org>
Reviewed-by: Ruben Rodriguez Buchillon <coconutruben@chromium.org>
Old oak boards that still use these functions have long been
deprecated, let's make the unneeded functions static.
BRANCH=none
BUG=b:35573263
TEST=make buildall -j => makes newsizes: up to 64 bytes saved on
a few boards.
Change-Id: I8f2503ce324e34b87b3bbfa3c509079357880c9e
Signed-off-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/848574
Reviewed-by: Shawn N <shawnn@chromium.org>
In the CL:826909, the name and the restore address of ec_spiflash lfw
are modified becaue of introducing the UUT. This CL modified the openocd
scripts to follow the changes of the lfw.
BRANCH=none
BUG=none
TEST=Apply CL:826906 and "BOARD=npcx7_evb make";
Run cmd "./util/flash_ec --board=npcx7_evb" to flash ec image;
Make sure the ec firmware can be updated with the new npcx_minotor lfw
+ this CL via JTAG on Servo v2.
Change-Id: If622f83e2d2132d66b390bcee30c77e7a9d5f7bd
Signed-off-by: CHLin <CHLIN56@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/828341
Commit-Ready: CH Lin <chlin56@nuvoton.com>
Tested-by: CH Lin <chlin56@nuvoton.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
The original ec_npcxspiflash lfw is used by the openocd to program SPI
flash via Servo JTAG. In order to support UUT mode to program SPI flash,
this CL modified the lfw with the following changes:
1. Rename the lfw ec_npcxflash to npcx_monitor to unify the naming.
2. The npcx_monitor will read the first 4 bytes from the area of monitor
header. If the monitor identifies the first 4 bytes is a UUT tag, it
will read parameters(SPI_OFFSET/IMAGE_SIZE) from the relative offset of
monitor header. Otherwise, it will read parameter from the general
register r0/r1 which will be restored by openocd script in advance.
3. Add monitor_hdr.c to generate the monitor header binary files
(monitor_hdr_ro.bin/monitor_hdr_rw.bin)) automatically after compiled.
The memory layout to restore the reuqired binaries are listed below:
ec firmware(RO/RW) - the start address of Code RAM area.
monitor header - 0x200C3000
npcx_monitor - 0x200C3020
BRANCH=none
BUG=none
TEST=No build errors for "make buildall".
TEST=Follow instructions in CL:826763; make sure the ec firmware is
updated and ec can boot up.
CQ-DEPEND=CL:828341
Change-Id: I5de997a4dee5449d578972e2f929c6e08c5dff67
Signed-off-by: CHLin <CHLIN56@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/826909
Commit-Ready: CH Lin <chlin56@nuvoton.com>
Tested-by: CH Lin <chlin56@nuvoton.com>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
Some upcoming designs based on the g chip require GPIOs connected to
open drain circuits.
Even though the chip explicitly provides only two open drain GPIOs,
the desired behavior of the rest of the pins when configured as 'open
drain' could be simulated by software if when 'high' is required the
output is disabled instead of driving the pin value.
To make sure there is no fallout from RO driving the pins, also add an
explicit 'disable output' initialization in case a GPIO is configured
for open drain and the initial output value is 'high'.
BRANCH=cr50
BUG=none
TEST=verified that Cr50 booted successfully, also confirmed that on
the test board that GPIOs defined as Open Drain allow we set
output to 1 only if pulled up.
Change-Id: Id2daa19b992bab7fb01148b6fa7b57fd0728b33d
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/848152
Reviewed-by: Randall Spangler <rspangler@chromium.org>
This adds the driver for the SB-TSI temp sensor.
This is a sensor on the AMD AP SOC (Stoney Ridege FT2) that acts like an
8-pin temp sensor with an I2C interface.
BUG=b:69379715
BRANCH=None
TEST=Build
Change-Id: Iaafe6c7beb3e02e4e341617e8f117c03c0a882a2
Signed-off-by: Alec Thilenius <athilenius@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/833346
Commit-Ready: Alec Thilenius <athilenius@google.com>
Tested-by: Alec Thilenius <athilenius@google.com>
Reviewed-by: Edward Hill <ecgh@chromium.org>
RT4531 wants PWM input frequency between 20 and 100 kHz.
BRANCH=none
BUG=b:66575472
TEST=Flash wand, pwm 0 50, check with oscilloscope that frequency
is around 50kHz, and that duty cycle is 50%.
Change-Id: I6a37ef435a51cf730805ef57a0e3ebd05f9820a3
Signed-off-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/845541
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
This CL adds scripts to support updating ec image to the SPI flash by
UUT(UART Update Tool) for npcx ec. A new array BOARDS_NPCX_UUT is
introduced to include the board name which will use the UUT mechanism.
The detail of test setup/procedure is listed below:
1. Connect the following singals between npcx7 evb and Servo board v2.
NPCX7 EVB Servo V2
---------------------------------------
GPIO64/CR_SIN <--> UART1_SERVO_DUT_TX
GPIO65/CR_SOUT <--> UART1_DUT_SERVO_TX
VDD_3.3V <--> PPDUT_UART1_VREF
2. Manually pull the UUT mode strap pin(GPIO65/CR_SOUT) to ground with a
10 KOhm resistor.
3. Assert a EC VCC1_RST reset or issue a Power-Up reset.
4. Remove the pull-down in step 2.
5. Move npcx7_evb from array BOARDS_NPCX_7M6X_JTAG to BOARDS_NPCX_UUT in
flash_ec.
6. ./util/flash_ec --board=npcx7_evb.
BRANCH=none
BUG=none
TEST=Follow the steps above. Dump the SPI flash content to a file via
JTAG. Compare the file and ec image. Make sure their content is all
the same. Check the ec can reboot after programming.
Run "sysjump rw"; make sure RW image works well.
Change-Id: Iada5acb53179bdb78459c4fea7488fd2691575b6
Signed-off-by: CHLin <CHLIN56@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/826763
Commit-Ready: CH Lin <chlin56@nuvoton.com>
Tested-by: CH Lin <chlin56@nuvoton.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
Add espi_signal_is_vw in new file common/espi.c for
testing if a signal is an eSPI virtual wire. API used
in power common and intel_x86.
Fix CONFIG_BRINGUP support for eSPI (off by default).
Add espi_vw_get_wire_name returning a pointer to
constant string. Chip modules do not need to maintain
names of eSPI signals.
BRANCH=none
BUG=
TEST=Build poppy and other eSPI enabled boards. Test
power state machine.
Change-Id: I13319e79d208c69092a02ec3ac655477d3043d61
Signed-off-by: Scott Worley <scott.worley@microchip.corp-partner.google.com>
Reviewed-on: https://chromium-review.googlesource.com/836818
Commit-Ready: Randall Spangler <rspangler@chromium.org>
Tested-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Because Scarlet doesn't use smart battery, in the current
implementation of charging algorithm, we simply provide constant
voltage/current to the battery.
However, the datasheets of Scarlet battery packs do state different
desired voltage/current in different temperature range.
So we should implement the custom charging profile for the battery.
BUG=b:65597565
BRANCH=none
TEST=override measured temperature to confirm zone changing is fine
on rev2
Change-Id: I188578fd46e28f1f05fbce2150af23aaae457cc5
Signed-off-by: Philip Chen <philipchen@google.com>
Add Microchip MEC17xx family trace fifo debug
(TFDP) files. TFDP is a MCHP specific two pin,
output only software message port.
Added TFDP module ID.
Change-Id: Ibe2399a8c3618b207a89552450d80b7901e85f23
Signed-off-by: Scott Worley <scott.worley@microchip.corp-partner.google.com>
Add Micorchip MEC17xx family files for
hardware timers, keyboard scan, host
port 80h, UART, and watch dog timer.
BRANCH=none
BUG=
TEST=Review only.
Change-Id: Iac8a912af4d29521964f606637041b06fa7238ee
Signed-off-by: Scott Worley <scott.worley@microchip.corp-partner.google.com>
Added I2C sensors ADT7481 and TMP411 with config
items and build rules.
BRANCH=none
BUG=
TEST=Define CONFIG_TEMP_SENSOR_ADT7481 or _TMP411
and build board.
Change-Id: I4d1eb55ee56ad3f42787538bb839193e683d0a60
Signed-off-by: Scott Worley <scott.worley@microchip.corp-partner.google.com>
Add Microchip MEC17xx family PWM and fan
source files for review
BRANCH=none
BUG=
TEST=Review only.
Change-Id: I91439ab999a4662d690b58b0fbbb887f643b3673
Signed-off-by: Scott Worley <scott.worley@microchip.corp-partner.google.com>
Add Microchip MEC17xx family SPI master
controllers and flash files. SPI implements
public interface wrapper for QMSPI and GPSPI.
MEC17xx family uses QMSPI for loading
EC firmware. GPSPI is for general use (sensor).
BRANCH=none
BUG=
TEST=Review only.
Change-Id: I23001e254dd437caa0917949f4dd2eb903f1adb1
Signed-off-by: Scott Worley <scott.worley@microchip.corp-partner.google.com>
This CONFIG DISCHARGE_ON_AC enables discharging
battery even when AC is connected.
BUG=b:71364739
BRANCH=glkrvp
TEST=On glkrvp EC console, execute command
"chgstate discharge on" and verify if battery
is discharging with "battery" command.
Change-Id: I709c7b5ccfea9058961d387a1575db9aebe70707
Signed-off-by: Divya Sasidharan <divya.s.sasidharan@intel.com>
Issue was found when EC would not wake up from hibernate after
specified time period.
The infinite while loop blocks further hibernate functions
that needs to be executed after the board specific
hibernate method.
Remove this while loop to complete hibernation logic.
Also in hibernate function we should not be cutting down power
to EC (SMC_SHUTDOWN) as this will limit supporting wake sources
feature. Removing it in this patch.
BRANCH=master
BUG=b:70690772
TEST=On glkrvp EC console, check if "hibernate 30" wakes up EC
after 30 sec, with only battery, only AC, with AC+battery.
Change-Id: Iae735cc26eeef8e205771d2f3c6e5260918e093e
Signed-off-by: Divya Sasidharan <divya.s.sasidharan@intel.com>
Modify ALS module to use CPRINT macros with
channel support.
BRANCH=none
BUG=
TEST=Build board(s) with ALS support such glados.
Test ALS CPRINT messages go out over EC UART and
can be masked off by channel mask UART command.
Change-Id: I65ffc889d63a778f3fb8995f508773842ba875ef
Signed-off-by: Scott Worley <scott.worley@microchip.corp-partner.google.com>
Experimental and disabled by default feature for
powering down GPIO pins on those EC's supporting it.
Pins may be powered down by module ID or pin name.
Goal is to make use of common GPIO pin table.
If enabled, developer must implement power down
support in chip level. Developer re-powers module
pin(s) by calling the current gpio module enable
API in the wake path.
BRANCH=none
BUG=
TEST=Feature is disabled by default. Build all
boards with feature disabled.
Change-Id: Ifacd08e51def6424baf5c78c84b24f1d9f4bc4aa
Signed-off-by: Scott Worley <scott.worley@microchip.corp-partner.google.com>
BRANCH=none
BUG=
TEST=Review only. Committing small pieces until
all code passes review.
Change-Id: I9d16f95314a7c97b11c4fe61602c6db2621e6024
Signed-off-by: Scott Worley <scott.worley@microchip.corp-partner.google.com>
Add Microchip MEC17xx family little-firmware
(LFW) folder and files.
Change-Id: I9142266d41234574730fadccd5a2cc27fe3d8fd7
Signed-off-by: Scott Worley <scott.worley@microchip.corp-partner.google.com>
If AC is present but we're not charging yet, it's very possible this
status is transient (eg. due to cut-off battery, brief spike in current
useage, etc), so don't use very long task timeout.
BUG=b:70554834
BRANCH=None
TEST=Verify soraka doesn't take over a minute to boot when exiting from
ship mode.
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: I9dbfd8cb7dfc54cb8017bb0c7d633c5d64a15025
Move all the peripheral blocks base addresses in a common block rather
than spread among the register definitions.
This will help making a cleaner STM32H7 implementation whose base
addresses are all different from other families.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=none
BUG=b:67081508
TEST=compare all the ec.bin generated by 'make buildall' and verify
they are bit-identical with and without the change.
Change-Id: I52cafd2f3c9145dbcd585166df3fc78e38573bb4
libfpsensor is using it.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=none
BUG=b:70320279
TEST=run on Eve FP MCU with external library and see its traces are
correctly printed.
Change-Id: Iea1bc04d7ea7931478d14d655a7e986a0839a51a
For compatibility/convenience, implement the '%li' printf format
as a *32-bit* integer format, as it might be expected by non-EC code.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=none
BUG=b:70320279
TEST=run on Eve EVT with unspecified external binary and see its traces
are correctly printed.
Change-Id: Iac20e823c74aac4f659176416eebd804c321d47c
NCP15WB is actually the correct thermistor, let's drop that
copy-pasted comment.
BRANCH=none
BUG=b:35585396
TEST=make buildall -j
Change-Id: I5577bb70e354a6f2ef6338894793b808fe4b0e9a
Signed-off-by: Nicolas Boichat <drinkcat@chromium.org>
Nothing in fizz/nami code uses that thermistor: the 2 places that
would use it (ec_adc.c and bd99992gw.c) are not compiled in on
fizz/nami.
BRANCH=fizz
BUG=none
TEST=make buildall -j
Change-Id: Ib2af8ad066eb05cd9510669600feb26641433eed
Signed-off-by: Nicolas Boichat <drinkcat@chromium.org>
On dual-battery slave, we use the charging allowed signal from
master to indicate whether external power is present.
In most cases, this actually matches the external power status
of the master (slave battery charging when AC is connected, or
discharging when slave battery still has enough capacity), with
one exception: when we do master to slave battery charging (in
this case the "external" power is the master).
BRANCH=none
BUG=b:65697962
TEST=Deplete wand battery to 5%, see that lux still provides power
to it but the battery does not charge.
Change-Id: I8bd9f52c386a0a9edfae3837ba33725b3101a008
Signed-off-by: Nicolas Boichat <drinkcat@chromium.org>
Scarlet has only one PD port.
Let's always source 1.5A instead of 3A.
BUG=b:70524967
BRANCH=none
TEST=Monitor PD packets, see Scarlet rev2 broadcast
source_cap as 'FixedVol=5.00V, MaxCur=1.50A'
Change-Id: Id9bcd69f3a20ef5eb55eb7b17539fd304abb08e4
Signed-off-by: Philip Chen <philipchen@google.com>
It's a dead board.
BUG=none
BRANCH=none
TEST=make buildall -j
Change-Id: I9f5530afdea07bb5787fa2b674984147f8425fba
Signed-off-by: Philip Chen <philipchen@google.com>
When SLP_SUS_L is deasserted, that means the chipset is in S5.
BUG=None
BRANCH=None
TEST=Flash meowth; boot from AC only, verify that when SoC actually
boots the power state is reported as S0 instead of G3.
Change-Id: Ib9cd76aa9efd6f81df432205b8c1e8c342e32af6
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/837485
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This patch makes EC save the max current and voltage of a barrel jack
adapter before sysjump and restore them after sysjump.
BUG=b:64442692
BRANCH=none
TEST=Boot Fizz and let coreboot set the adapter current and voltage.
Verify EC-RW inherits the current and voltage set by coreboot.
Change-Id: Ib1addf6e5ce059a39cb2d8b355515df1138409eb
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/835628
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
