This patch makes cbi-util print the tag and the size of each field.
It also fixes help message and adds indendation for readability.
BUG=b:70294260
BRANCH=none
TEST=Run the command as follows:
$ cbi-util --show /tmp/cbi.bin
CBI blob: /tmp/cbi2.bin
TOTAL_SIZE: 18
CBI_VERSION: 0
Data Field: name: value (hex, tag, size)
BOARD_VERSION: 514 (0x202, 0, 2)
OEM_ID: 2 (0x2, 1, 1)
SKU_ID: 3 (0x3, 2, 1)
Data validated successfully
Change-Id: I5f0fde4690c29c0ee58c798e8cc35bac3ed1b6f8
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/926781
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Release the reset of the FP MCU later after loading the proper spidev
kernel module else the STM DFU bootloader is confused by the SPI state
and fails half of the time.
Also update the SPI device for the current board configuration.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=none
BUG=b:36125319
TEST=On Meowth, run a lot of 'flash_fp_mcu ec.bin'
Change-Id: I634fbc91fc5da52b07c48696594661f88338d986
Reviewed-on: https://chromium-review.googlesource.com/924284
Commit-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Gwendal Grignou <gwendal@chromium.org>
BUG=chromium:803955
BRANCH=none
TEST=Verify counters are printed every hour and before sysjump as follows:
[12.540051 HC Suppressed: 0x97=25 0x98=0 0x115=0]
Change-Id: I1c1aecf316d233f967f1d2f6ee6c9c16cc59bece
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/912150
Currently CBI data offset and size are fixed. This patch makes them
variable. Each data item consists of <tag><size><value> where <tag>
is a numeric value assigned to each data item, <size> is the number
of bytes used for <value>.
BUG=b:70294260
BRANCH=none
TEST=Use 'ectool cbi set' to set board version, oem, sku.
Verify the contents by cbi console command and ectool cbi get.
1. ectool cbi set 0 0x202 2 2 (Init CBI and write board ver. of size 2)
2. ectool cbi set 1 1 1 (write oem id of size 1)
3. ectool cbi set 2 2 1 (write sku id of size 1)
4. ectool cbi get 0
514 (0x202)
5. ectool cbi get 1
1 (0x1)
6. ectool cbi get 2
2 (0x2)
7. Run cbi console command:
CBI_VERSION: 0x0000
TOTAL_SIZE: 18
BOARD_VERSION: 514 (0x202)
OEM_ID: 1 (0x1)
SKU_ID: 2 (0x2)
43 42 49 8c 00 00 12 00 00 02 02 02 01 01 01 02
01 02
Change-Id: I5a30a4076e3eb448f4808d2af8ec4ef4c016ae5e
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/920905
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Add support for an additional finger image capture type
used for quality testing.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=none
BUG=b:72360575, b:71770455
TEST=On Meowth, run 'ectool --name=cros_fp fpmode capture qual'
then 'ectool --name=cros_fp fpframe raw > finger_mq.bin'
Change-Id: I1b9525dc2adf0b91aef2f7124803c90d6a3bb0ca
Reviewed-on: https://chromium-review.googlesource.com/924124
Commit-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Nicolas Norvez <norvez@chromium.org>
Replace the current led code with an implementation that uses the new
led_pwm interface. Grunt has a blue LED which we use for power and an
amber LED which we use for battery.
The colours used are documented in update_leds() in led_pwm.c
BUG=b:71902053
BRANCH=none
TEST=manual
Check for the various states:
* Solid Amber == Charging
* Solid Blue == Charging (near full)
* Fast Flash Amber == Charging error or battery not present
Did not test low / critical battery
Change-Id: Ie46075855ab17e6e7301025b62e57db2c596b2a4
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/919765
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Edward Hill <ecgh@chromium.org>
The EC_BATT_PRES_ODL is an open drain signal. The SN74LVC1G07
IC which drives that signal is an open drain buffer. There is
no external pull. Therefore, an internal pullup is required.
BRANCH=none
BUG=b:73286869
TEST=gpioget shows 0 with battery and 1 without
Change-Id: I98e18f54b62ddd558bedd9cec65aa003589a0681
Signed-off-by: Edward Hill <ecgh@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/923102
Commit-Ready: Jett Rink <jettrink@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
According to Nuvoton datasheet, when SHM windows are in IO mode, only the
bottom 16-bits of registers @ offset xF4 and xF8 are used.
"This register is ignored when WRAM1_IO bit in WIN_CFG register is set to
1 (LPC / eSPI Peripheral Channel I/O access with 16-bit address). This
register is set to its default value by Host Domain reset."
BRANCH=none
BUG=none
TEST=boot grunt and verify host communication still works.
Change-Id: I3e48ea1b09355eaf6967b9f7522bc3d35459b76b
Signed-off-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/919006
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Mulin Chao <mlchao@nuvoton.com>
This patch also removes make rules to stop producing CBI blobs.
CBI blobs will be produced by another protage package.
BUG=b:73123025,chromium:809250
BRANCH=none
TEST=emerge-fizz chromeos-firmware-fizz and verify
/build/fizz/firmware/cbi contains EEPROM images.
Verify emerge ec-utils ec-devutils succeeds.
Change-Id: I13744b0ab97675afa0247046bffa3edac3e62ceb
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/909692
A typical CCD use case is when the DUT is not fully functional, or
even completely dead, including corrupted AP/EC firmware.
We still want to be able to enable CCD in this case, but routing CCD
commands through TPM task context (necessary to ensure the large stack
size some CCD commands require) is blocked if TPM was not reset after
startup.
Let's allow both reset requests and alternative commands when AP is
held in reset after reboot. The only situation when the alternative
command arrives would be the CCD use case of the system not generating
TPM reset pulse at startup and the operator is trying to execute a CCD
or RMA reset command.
BRANCH=cr50, cr50-mp
BUG=b:73292631
TEST=on a reef device: destroyed AP firmware and observed that the
'ccd open' command indeed results in the hung Cr50 console after
Cr50 is reset in this state.
Loaded the new Cr50 image, (which caused another Cr50 reset),
successfully took it through the 'ccd open' sequence resulting in
enabling AP flash write access, restored the AP flash and
observed the DUT boot into Chrome OS.
Change-Id: I4413bc200f5b2be563ba666ff80dd2d889ae5790
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/920924
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
Add a way to report the current state using this command. This is useful
when debugging.
BUG=b:71902053
BRANCH=none
TEST=manually
> ledtest 0
PWM LED 0: led_id=0, auto_control=1
> ledtest 0 enable amber
> ledtest 0
PWM LED 0: led_id=0, auto_control=0
Change-Id: I478980d82573b60b536ea0f4dcf324b7ccfb6fdb
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/919764
The console command now calls the vendor command to do the work.
Otherwise, the same as before.
BUG=chromium:804507
BRANCH=cr50 release (after testing)
TEST=manual:
# Sample sequence
spihash ap -> requires physical presence; tap power button
spihash 0 1024 -> gives a hash; compare with first 1KB of image.bin
spihash dump 0 128 -> dumps first 128 bytes; compare with image.bin
spihash 128 128 -> offset works
spihash 0 0x100000 -> gives a hash; doesn't watchdog reset
spihdev ec
spihash 0 1024 -> compare with ec.bin
spihash disable
# Test timeout
spihash ap
# Wait 30 seconds
spihash 0 1024 -> still works
# Wait 60 seconds; goes back disabled automatically
spihash 0 1024 -> fails because spihash is disabled
# Presence not required when CCD opened
ccd open
spihash ap -> no PP required
spihash 0 1024 -> works
spihash disable
# Possible for owner to disable via CCD config
ccd -> HashFlash is "Always"
ccd set HashFlash IfOpened
ccd lock
spihash ap -> access denied
# Cleanup
ccd open
ccd reset
ccd lock
Change-Id: Ife9335a1e402a7596d99bf515ec89ff94e8a0044
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/910083
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
we need to enable CONFIG_CMD_PD_CONTROL so the AP (depthcharge) can do
TCPC firmware update. this was left disabled for bringup.
BUG=b:69010531
BRANCH=none
TEST=booted on meowth, was able to update TCPC firmware
Change-Id: If383cff27c7b79f46f451c6380585d1300fc3413
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/910322
Commit-Ready: caveh jalali <caveh@chromium.org>
Tested-by: caveh jalali <caveh@chromium.org>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
the npcx7 can only run eSPI at (up to) 50MHz while the npcx5 can go up
to 66MHz. so, set the max speed to whatever the hardware can actually
do. the bit pattern for 66MHz is "reserved" on the npcx7, so let's
not even define it in the npcx7 case.
BUG=b:72838699, b:71859563
BRANCH=none
TEST="make buildall" passes; boots on meowth
Change-Id: I428caf72a41fe58008df4624c475dafadca4a0bc
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/910321
Commit-Ready: caveh jalali <caveh@chromium.org>
Tested-by: caveh jalali <caveh@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
This will prevent earlier released images from running on the device
unless Info1 is erased.
BRANCH=cr50, cr50-mp
BUG=b:70891959
TEST=verified that two bits in the rollback mask have been erased now:
> sysinfo
Reset flags: 0x00000800 (hard)
[...]
Rollback: 2/2/128
Change-Id: Ic345c79010fbe0e075e14e652ea1eba263226ab1
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/916737
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
The new key ID is set to zero.
BRANCH=cr50, cr50-eve
BUG=b:70891959
TEST=verified that prod server properly responds to the challenge
generated by a CR50 running on Robo device.
Change-Id: I1e0da4a2cebca7f985c5f2a6da509c850924a874
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/915503
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Michael Tang <ntang@chromium.org>
On sysjump, if power button is held down, first check
power_button_pulse_enabled setting to decide if powerbtn to pch should
be asserted. This is important to prevent accidental shutdowns when
user is attempting to do an EC reset with Vup+Pwr held down.
BUG=b:73129177
BRANCH=None
TEST=Verified following:
1. Reset EC by holding Vup+Pwr.
2. Keep holding Vup+Pwr until AP reaches depthcharge.
3. Ensure that AP does not shutdown.
Change-Id: I0375fc8e8baabb40807dfdc6d4c9fa70c9b3b87d
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/912364
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
According to table 4-25 in USB TypeC spec version 1.3, Vconn should be
sourced before Vbus or within 2ms. On Grunt I am see tVconnON around 2.3
ms, which is out of spec. We can simply source Vconn first to comply with
spec.
BRANCH=none
BUG=b:72811851
TEST=Grunt's tVonnOn is now <2ms
Change-Id: I52ca6a52bf576487061b2c33f348edf58eb06ca0
Signed-off-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/911928
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Edward Hill <ecgh@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
EN_PWR_A GPIO turns on PP1800_A, PP5000_A, PP3300_A, PP950_A.
These should be off in G3 and on in S5 and higher.
VGATE (S0 power) is pulled high in G3 when SPOK (system power,
S5) is low because PP5000_A turns off, so add a check for this
and only pass through high VGATE when SPOK is also high.
Leave kahlee behavior unchanged (power stays on in G3).
BUG=b:72744306
BRANCH=none
TEST=power on and off SOC, see GPIO_EN_PWR_A go low in G3
Change-Id: I68a1ac10263ad84d5ee154613e5e248edb4d287c
Signed-off-by: Edward Hill <ecgh@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/904729
Commit-Ready: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Jett Rink <jettrink@chromium.org>
Deep Sleep states (DS3, DS5) are a special mode of the Intel PCH chipset
that has very limited wake capabilities and breaks a number of common
user expected behahviors.
In particular, when in Deep S3 the USB ports are turned off and cannot
continue to charge, wake the system, or maintain their internal state
as they will lose 5V power. This is particularly painful with gnubby
devices as they will need unlocked after every DS3 suspend/resume cycle.
The only external signal that the PCH uses to determine whether or not
to enter Deep Sx states is the ACPRESENT (aka ACOK) pin.
Currently this pin is simply buffered from the charger and will be
asserted whenever a charger is connected. This change extends the EC
control over the pin to also assert ACPRESENT if either Type-C port is
currently supplying VBUS.
Now when a USB device is inserted the system will be enter S3 state,
but not go into Deep S3 state. This allows the USB device to continue
to charge, maintain it's internal state, and wake the system.
BUG=b:64406191
BRANCH=eve
TEST=verify GPIO_PCH_ACOK pin from the EC in different scenarios and
test that system goes into S3 or DS3 state as expected:
1) no charger, no USB device: ACOK not asserted, DS3 enabled
2) charger but no USB device: ACOK asserted, DS3 disabled
3) no charger but USB device: ACOK asserted, DS3 disabled
4) charger and USB device: ACOK asserted, DS3 disabled
Change-Id: I1cd132459194382e418970d29b1b195d8132cfad
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://chromium-review.googlesource.com/896164
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Disable sensor power (lid accel, gyro) in G3+S5. Enable
it in S3+S0. We want it on in S3 for calculating the lid
angle (needed on convertibles to disable resume from
keyboard in tablet mode).
BUG=b:72741289
BRANCH=none
TEST=GPIO_EN_PP1800_SENSOR =0 in G3+S5 and =1 in S3+S0
Change-Id: I043b880b9fbd44242df0d2ac01c92a066d6b4377
Signed-off-by: Edward Hill <ecgh@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/912452
Reviewed-by: Lann Martin <lannm@chromium.org>
Reviewed-by: Jett Rink <jettrink@chromium.org>
In the case where we are resetting Vbus and it is our only power source,
then we will brown out before we set the active port to 0.
BRANCH=none
BUG=none
TEST=Did a cold reset on grunt with no battery power. System booted as
normal.
Change-Id: I3823af6b0475e4cf8abbe12dd8ae4ceef26d1eab
Signed-off-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/911613
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Edward Hill <ecgh@chromium.org>
Turn off vSafe0V interrupts. They were not being handled or
cleared causing the interrupt line to be stuck low after
unplugging a USB device.
Also don't use read-modify-write for INT_STATUS_REG4 since
this would clear the dead battery mode bit before it has
been checked.
BUG=b:73076662
BRANCH=none
TEST=unplug USB device, see USB_C1_SWCTL_INT_ODL=1
TEST=USB2 mouse can be connected multiple times, PPC VBUS
detection works, BC1.2 chip turns on and off correctly
(USB_C1_BC12_VBUS_ON_L).
Change-Id: I96980ee330dd6e5f98e447e5e87f11dd60768a5d
Signed-off-by: Edward Hill <ecgh@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/909549
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Jett Rink <jettrink@chromium.org>
Configure the fingerprint to be compile only in the RW partition for
size reason, and keep the RO for firmware update only.
Enable the RW signature to jump automatically to RW.
The dev key was generated with the following command:
openssl genrsa -3 -out board/meowth_fp/dev_key.pem 3072
Enable the new STM32H7 internal flash support along the way.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=none
BUG=b:72360575
TEST=run on ZerbleBarn and see the firmware jumping to RW,
then run 'fptest' console command and get a proper capture.
CQ-DEPEND=CL:*552559
Change-Id: Icc894b8a59b255b4c6a139f177e99d0fde7c4e19
Reviewed-on: https://chromium-review.googlesource.com/880955
Commit-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
We share the same shared memory fields for both batteries. When
the host wants to switch battery to read out:
- The host sets EC_ACPI_MEM_BATTERY_INDEX to the required index
- EC then swaps the data is the shared memory fields, then update
EC_MEMMAP_BATT_INDEX
- Host waits for EC_MEMMAP_BATT_INDEX to have the required value,
then fetches the data
BRANCH=none
BUG=b:65697620
TEST=Boot lux, both /sys/class/power_supply/BAT0 and BAT1 are
present, data is valid.
TEST=Unplug base, BAT1 goes away, replug, BAT1 comes back.
Change-Id: Icce12f9eef2f6f8cde9bae0a968a65e1703d0369
Signed-off-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/888382
Reviewed-by: Gwendal Grignou <gwendal@google.com>
The STM32H7 family has 2 banks of flash (with 2 hardware controllers
able to do 2 parallel operations at the same time).
Each bank of flash has 4 or 8 128-kB erase blocks (1MB and 2MB
variants).
The flash can only be written by 256-bit word (with an additional 10-bit
ECC computed by the hardware).
For the flash write-protection, we cannot use our 'classical' PSTATE
scheme as the erase-blocks are too large (128-kB) to dedicate one to
this and the embedded word in the RO partition would not work as the
flash has ECC and triggers bus-fault when the ECC is incorrect (which
includes the case where the 256-bit word is written a second time).
So we will do the following:
- use the RSS1 bit in the option bytes as the Write-Protect enabled bit.
- if the WP GPIO is set, lock at startup the option bytes until next
reboot.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=none
BUG=b:67081508
TEST=run flashinfo/flashwp/flashwrite/flasherase commands on the EC
console.
Change-Id: I823fce3bd42b4df212cf0b8ceceaca84109b78e6
Reviewed-on: https://chromium-review.googlesource.com/901423
Commit-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
We want to build the shmalloc common code in test mode *only* for the
shmalloc test not for all test binaries (which are missing the helper
functions).
The previous version was broken for any board declaring CONFIG_SHMALLOC
(but none were excepted cr50 which has tests disabled)
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=none
BUG=b:72360575
TEST=emerge-meowth chromeos-ec
Change-Id: Ic89c74569fbadbc75d9090b084adab8f40ddfa5d
Reviewed-on: https://chromium-review.googlesource.com/909210
Commit-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
This allows hashing or dumping SPI flash from the Cr50 console even on
a locked device, so you can verify the RO Firmware on a system via CCD.
See design doc: go/verify-ro-firmware
(more specifically, "Cr50 console commands for option 1")
BUG=chromium:804507
BRANCH=cr50 release (after testing)
TEST=manual:
# Sample sequence
spihash ap -> requires physical presence; tap power button
spihash 0 1024 -> gives a hash; compare with first 1KB of image.bin
spihash 0 128 dump -> dumps first 128 bytes; compare with image.bin
spihash 128 128 -> offset works
spihash 0 0x100000 -> gives a hash; doesn't watchdog reset
spihdev ec
spihash 0 1024 -> compare with ec.bin
spihash disable
# Test timeout
spihash ap
# Wait 30 seconds
spihash 0 1024 -> still works
# Wait 60 seconds; goes back disabled automatically
spihash 0 1024 -> fails because spihash is disabled
# Presence not required when CCD opened
ccd open
spihash ap -> no PP required
spihash 0 1024 -> works
spihash disable
# Possible for owner to disable via CCD config
ccd -> HashFlash is "Always"
ccd set HashFlash IfOpened
ccd lock
spihash ap -> access denied
# Cleanup
ccd open
ccd reset
ccd lock
Change-Id: I27b5054730dea6b27fbad1b1c4aa0a650e3b4f99
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/889725
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
We need to wake up charger task right after AC is plugged
so that the charge state can be updated immediately.
BUG=b:71520398
BRANCH=none
TEST=Confirm charger task wakes up immediately when AC is
plugged in a Scarlet in G3.
Change-Id: I4a65b3da363cdc204b800bd300824dae616770cb
Signed-off-by: Philip Chen <philipchen@google.com>
Reviewed-on: https://chromium-review.googlesource.com/869419
Commit-Ready: Philip Chen <philipchen@chromium.org>
Tested-by: Philip Chen <philipchen@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
When AP requests cold reboot, currently EC does not perform PMIC
reset because chipset_handle_reboot is executed only after EC jumps
to RW. This causes EC to miss CHIPSET_STARTUP and CHIPSET_RESUME
events because power rails do not cycle.
This patch will make EC execute PMIC reset to before vboot_main.
BUG=b:73093795
BRANCH=none
TEST=reboot, reboot ap-off, verify USB ports are powered after
transitionining to dev mode.
Change-Id: Ic04395d8a4bff45d9fc60601b07c600dfb75d9c0
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/908094
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
1. Prochot/Shutdown Point
a. Prochot on: >=81C, off: <=77C
b. Shutodwn: >=82C
2. custom fan table
There are three projects sharing two tables, and
use Kench & Teemo's table before getting correct OEM ID
because it raises fan speed quicker than the other one.
a. Kench & Teemo & default
b. Sion
BUG=b:70294260
BRANCH=master
TEST=EC can get two fan tables with different cbi value.
Change-Id: Ie1bffbcf5c353a9aae5806f6c2b41554eed22b7d
Signed-off-by: Ryan Zhang <ryan.zhang@quanta.corp-partner.google.com>
Reviewed-on: https://chromium-review.googlesource.com/886121
Commit-Ready: Daisuke Nojiri <dnojiri@chromium.org>
Tested-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
BRANCH=none
BUG=b:72722179
TEST=lidopen/lidclose, see that USB interface is getting enabled/disabled
TEST=Close/open sensor with a magnet, see that USB interface is getting
enabled/disabled
TEST=Boot with sensor open, USB interface is on
Change-Id: Ic738fa2f2adea03cd29914bb5fc96a1fa6834122
Signed-off-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/894783
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Since there is no KEYPROTO task on chromebox such as fizz and sion, lpc
driver doesn't declare KBC IBF/OBE ISRs for these events. If host put
data in ec's KBC input buffer unexpectedly, exception_panic() will be
executed in default_handler. Then we will see ec print
"=== PROCESS EXCEPTION: 29 ====== xPSR: 01000000 ===" message without
any hard fault and reset.
This CL fixed this symptom by turning off KBC if there is no KEYPROTO task.
We also run suspend stress test on fizz and no watchdog reset symptom
occurred.
BRANCH=none
BUG=b:72353876
TEST=No build errors. Run suspend stress test on fizz and no watchdog
reset occurred.
Change-Id: I4744fac0d6fb2628849c728d4860509434fa2cbb
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/899706
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Duncan Laurie <dlaurie@google.com>
