There is leakage on SYS_RST_ODL from the internal pullup cr50 has on
DIOM0. This change removes the internal pullup on reef.
On Kevin there is a bug preventing the EC from being able to pull
sys_rst_l up high enoug for cr50 to detect that it is pulled high. This
change adds an internal pullup back when cr50 detects that it is on a
kevin or gru.
BUG=chrome-os-partner:56945
BUG=chrome-os-partner:53544
BRANCH=none
TEST=On gru and kevin remove servo verify when apreset is run on the EC
it resets cr50 and the AP. Run pinmux and check that there is a pullup
on diom0 on kevin but not on gru.
Change-Id: Ica4f557745967b93e0bd9c8462916b1f735756ac
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/381322
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
This changes how tpm_register_put() debug messages are displayed
to show only the bytes that are sent instead of some
uninitialized bytes as well.
BUG=none
BRANCH=none
TEST=make buildall; run on Cr50 hardware
On the console, run
chan -1
to enable displaying the debug output.
Before this CL, you'd see messages like this:
tpm_register_put(0x024, 21 180)
tpm_register_put(0x024, 1 17f)
tpm_register_put(0x018, 1 120)
tpm_register_put(0x018, 1 140)
Afterwards, you'd see accurate messages:
tpm_register_put(0x024, 21, 80 01 00 00 ...)
tpm_register_put(0x024, 1, 01)
tpm_register_put(0x018, 1, 20)
tpm_register_put(0x018, 1, 40)
Change-Id: Iad798804a4b6060e9bfafad50c90138eb1144c8f
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/382664
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
All PIN() assignments in board/$BOARD/gpio.inc must be unique,
since otherwise you're just creating duplicate names and table
entries for the same core interrupt and may not be initializing
things the way you think.
BUG=none
BRANCH=none
TEST=make buildall; test on Cr50 hardware
Also verified that the image size is exactly the same before an
after this CL.
Change-Id: Ifb1805a010905f67fc5c0d246b6252af73715409
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/383773
Reviewed-by: Randall Spangler <rspangler@chromium.org>
On different systems SYS_RST may be edge triggered, so it is not
guaranteed holding it low will hold the AP in reset. With this change,
enable_ap_spi now holds the EC in reset, so it is guaranteed the AP is
in reset.
BUG=chrome-os-partner:54982
BRANCH=none
TEST=run 'sudo flashrom -p raiden_debug_spi:target=[EC|AP] --flash-name'
on gru, kevin and reef
Change-Id: I3176462b932eba5bf8d69dbab70500bca8c7ff46
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/380484
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
For kevin, we are not using the PROCHOT# signal for the charger so we
can enable a power save mode. This commit will leave BGATE on but
without monitoring the PROCHOT# signal. When VBUS or VCC is removed
from the charger, the charger will enter this power save mode. It will
return to normal functionality when VBUS or VCC is applied.
BUG=chrome-os-partner:55631
BRANCH=kevin
TEST=Flash kevin; Verify we can still charge; Verify that power
consumption is less with this patch applied than without.
CQ-DEPEND=CL:382877
Change-Id: I05274a770b35c981e0541d8f79f66b81ffb4d153
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/383391
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
The BD99956 charger has a power save mode that it can enter once VBUS or
VCC is removed. This commit adds an optional config option that can be
used to select the power save mode:
CONFIG_BD99955_POWER_SAVE_MODE
By default, no power save mode will be enabled. However, a board can
device what level of power savings they wish to use.
The levels are the following:
BD99955_PWR_SAVE_LOW /* BGATE ON w/ PROCHOT# monitored only system
* voltage. */
BD99955_PWR_SAVE_MED /* BGATE ON w/ PROCHOT# monitored only system
* voltage every 1ms. */
BD99955_PWR_SAVE_HIGH /* BGATE ON w/o PROCHOT# monitoring. */
BD99955_PWR_SAVE_MAX /* BGATE OFF */
BUG=chrome-os-partner:55631
BRANCH=kevin
TEST=make -j buildall
Change-Id: Ibab7ad30d5f1ae9917b46b40d6f2800ef19e52dd
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/382877
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
Enable interrupt from BMI160 for FIFO control.
It can be use for significant motion detection.
BRANCH=kevin
BUG=b:28552512
TEST=Pass CTS tests SensorBatchingTests, SingleSensorTests
To trigger FIFO interrupt during the batch tests, EC lid angle
calculation is disabled from the EC with "acclerate 0 0"
Change-Id: I3ed4afcdee7075c5e5e20974d70a9e6bd64ecd52
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/382677
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Allow the detection of tablet mode for sensors and powerd.
BUG=chromium:606718,b:28552512
BRANCH=kevin
TEST=Check with evtest that events are send.
Check sensor data is in lid referal in tablet mode.
Change-Id: I0822e7419ccba01d70bf9327593164c15493fb10
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/380377
Reviewed-by: Randall Spangler <rspangler@chromium.org>
When tablet mode is detected, send an event to the AP.
BUG=chromium:606718
BRANCH=none
TEST=Check with evtest that events are sent when the tablet goes in tablet
mode and back to device mode.
Change-Id: I49f2404b5ecf87e71fa5aef4c8ce9c9beda26a15
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/380414
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
User of sensor data can use tablet mode to rotate the sensor datums
along the X axis.
This is useful on Kevin where we gather base data.
When the base is behind the lid, the datums needs to be rotated by 180
to be in the lid referential.
BUG=b:27849483
BRANCH=none
TEST=check the sensors changes when kevin is in tablet mode.
Change-Id: I60147600f534df0770a44b5158ef8afe87d9dd9d
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/380413
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Using the lid angle, detect if we are in tablet mode or not.
We are in tablet mode when the lid angle is large enough:
tablet_mode:
1 | +-----<----+----------
| \/ /\
| | |
0 |------------------------>----+
+------------------+----------+----------+ lid angle
0 240 300 360
BRANCH=kevin
BUG=chrome-os-partner:55702,b:27849483
TEST=Check on Kevin event are sent on tablet mode transition.
Change-Id: Id9935ce4dd717e2c20fa6c9520defb504a1760d9
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/383073
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
When lid is closed, the lid angle can move to 358, 360, 0, 359 ...
Prevent transition 0 from/to 360 by keeping the last calculated value.
BRANCH=kevin
BUG=chrome-os-partner:55702
TEST=Check transition does not happen anymore.
Change-Id: Ifa8415470f425c893e2c3662c84c8fd0156e0524
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/373040
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
There is no point in waiting for a reset to clear the fallback
counter, it can be cleared as soon as USB update is finished.
BRANCH=none
BUG=chrome-os-partner:56864
TEST=on a kevin-tpm2 device: set the reset counter to 7 by running
> rw 0x40000128 1
> rw 0x4000012c 7
on the cr50 console. Then try uploading a new RW image over Suzy-Q
and verify that it is running after reset.
Then verify that cr50 can still be updated
Change-Id: I098a87c48b2fe864143715b1e90d4bb2409b9eae
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/383077
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
This makes minor changes to GPIOs for the next build:
- USB_C0_PD_RST_L is actually push-pull in next build, so remove the
comments about USB_C0_PD_RST_ODL.
- Added TABLET_MODE
- Make the net name for volume up/down buttons match the name in the
schematic.
BUG=none
BRANCH=none
TEST=built and booted on Reef EVT
Change-Id: I0799de059d71809174e246b6bbd7f3a2fe25686a
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/381791
Reviewed-by: Shawn N <shawnn@chromium.org>
This adds support for the GD25LQ40 NOR flash chip which is identical
to W25Q40 for the purposes of write-protection support for the ranges
that we care about.
BUG=chrome-os-partner:57015
BRANCH=none
TEST=needs testing
Change-Id: I09ad02e04fab4c539b9558180d73bf6c31da6aed
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/382641
Reviewed-by: Shawn N <shawnn@chromium.org>
Sanity tested by powering up cr50 and checking for correct RBOX
register values.
This patch is mainly to address RBOX debounce issues and key blocking
while EC_RST is asserted. A debounce value less than 4, sometimes
causes initial pin values to be incorrectly detected. The latter is
related to https://chromium-review.googlesource.com/#/c/357590/.
As RBOX controls cannot be selectively bypassed (they have to be
bypassed as a group), all registers are set up in this patch
BUG=chrome-os-partner:54602
BRANCH=None
CQ-DEPEND=CL:377621
TEST=manual on Kevin
Do three-finger salute, enter recovery mode.
Change-Id: Ieb82c94fa33888ead359a77bf77981567998b3fc
Signed-off-by: Timothy Chen <timothytim@google.com>
Reviewed-on: https://chromium-review.googlesource.com/372001
Commit-Ready: Bill Richardson <wfrichar@chromium.org>
Tested-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
Data from the sensor (in Pa) does not fit in 16 bits.
Add set_range/get_range to allow the AP to set the precision.
For pressure around ~1000 hPa, we need to right shift by 2 bits.
BUG=chrome-os-partner:57117
BRANCH=reef
TEST=Check data is not truncated anymore:
> accelrange 4
Range for sensor 4: 262144 (Pa ~= 2621 hPa)
> accelread 4
Current data 4: 24030 0 0
Last calib. data 4: 24030 0 0 (x4 = 961.2 hPa)
Change-Id: I3f7280336e5120d903116612c9c830f4150d2ed7
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/382323
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
TTC must be written twice, otherwise the value will be lost on EC reset,
even if VBAT stays stable.
BUG=chrome-os-partner:57010
BRANCH=None
TEST=On kevin, run 'rtc set 55555' then trigger cold reset through
servo. Run 'rtc' on subsequent boot and verify timing ticks did not
reset to zero.
Change-Id: If05b698e75eece5f8879a109b98886b547eb71a4
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/382654
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
The CTR was set to 1 less than the max PWM value, so when the DCR
is set to max PWM value, duty goes to zero. The bug is fixed by
setting CTR to PWM max vlaue.
BUG=chrome-os-partner:57052
BRANCH=None
TEST=Manual on terminal.
> pwmduty 1 raw 0
Setting channel 1 to raw 0
1: disabled
> pwmduty 1 raw 65535
Setting channel 1 to raw 65535
verified that screen didn't blank
Change-Id: I10885d382f1bd252a5e7355da99dc00bd876e29f
Reviewed-on: https://chromium-review.googlesource.com/381632
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
We often find it handy to build test images that are unlocked or
have special powers. To avoid confusing these with production
images, this adds a "DEV/" to the version string:
"make BOARD=cr50" looks like this:
> version
Chip: g cr50 B2
Board: 0
RO_A: * 0.0.9/0088a3eb
RO_B: 0.0.8/710d4375
RW_A: * 0.0.6/cr50_v1.1.5261-4848d7e
RW_B: 0.0.6/cr50_v1.1.5261-4848d7e
[...]
"CR50_DEV=1 make BOARD=cr50" looks like this:
> version
Chip: g cr50 B2
Board: 0
RO_A: * 0.0.9/0088a3eb
RO_B: 0.0.8/710d4375
RW_A: 0.0.6/cr50_v1.1.5261-4848d7e
RW_B: * 0.0.6/DEV/cr50_v1.1.5261-4848d7e
[...]
BUG=chrome-os-partner:55557
BRANCH=none
TEST=make buildall; also..
Build both with and without the CR50_DEV=1 environment variable.
Observe that the version string differs even if nothing else
does.
Change-Id: Ifee9fbf922c2bbb40a1a9d0a716d2d11aa0d3ec2
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/382851
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
In order to improve the performance of sysjump, the CL increases the clock
freq of ec to 50M HZ (The maximum freq rate for SPI flash.). Once ec jumps
into the other region successfully, the clock freq is restored to the
default value (15MHz) in main routine.
Modified sources:
1. clock.c: Add clock_turbo for speed up clock's freq to max.
2. clock_chip.h: The declarartion for clock_turbo.
3. system.c: Speed up clock rate before downloading FW.
BRANCH=none
BUG=chrome-os-partner:34346
TEST=make BOARD=npcx_evb; test nuvoton IC specific drivers
Change-Id: I996e35fff336e6292599497feb1ee6c2f95becba
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/381799
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Input to the EC UART console is restricted by default so that
casual passers-by can't type random commands to it through the
case-closed debug connection. However, there's no need to
restrict the AP UART console, since it's entirely under the AP's
control.
This CL leaves the AP console enabled by default whenever the CCD
cable is connected. It will be disabled when the AP is powered
down or while servo is attached, but enabled otherwise.
BUG=chrome-os-partner:55322
BRANCH=none
TEST=make buildall, test on Cr50 hardware
Use the "ccd" command to see and modify the UART console
settings, and the "devices" command to observe how things change
when servo is connected and things are powered up and down.
Change-Id: I5cc453bc60473269e22112cf49f61495733abb10
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/382152
Commit-Ready: Bill Richardson <wfrichar@google.com>
Tested-by: Bill Richardson <wfrichar@google.com>
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
Add a hook to act when the a device is going in tablet mode and back.
BUG=chromium:606718
BRANCH=kevin
TEST=Test with evtest that an event is sent to the AP.
Change-Id: Ic9c3b158f1178504af41abff18b28de8e07fc7a7
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/380412
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
We don't really have the ability to build the latest signer yet, but
this should not stop us from being able to build a properly signed
image using the ec makefiles.
As a stopgap measure the suggestion is to keep the latest signer
binary in ~/bin/codesigner in chroot, then with this patch applied
invoking make with CR50_DEV=1 will cause the proper sighner used and
proper signing procedure followed.
The signed targets need to be built in series to avoid concurrent use
of the signer fob, an addition dependency is being added to enforce
that.
BRANCH=none
BUG=chrome-os-partner:55557
TEST=ran make as follows:
CR50_DEV=1 make BOARD=cr50
touched the fob when requested, uploaded the generated
build/cr50/ec.bin on a kevin-tpm2 using usb_updater, and observed
it boot properly with the new version.
Change-Id: Ia9494bdc60b4bd3b8e5e09cbcbd8b27409c739d2
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/376885
Tested-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
Enabled the trickle charging mode by setting the VPRECHG_TH_SET
register[0x18H] to board specific battery voltage minimum value.
When the battery voltage drops below the battery voltage minimum
value, trickle charging is enabled.
BUG=chrome-os-partner:56684
BRANCH=none
TEST=Manually verified on Reef. Drained the battery below battery
voltage minimum value. On plugging in the charger, State
Machine Status register CHGSTM_STATUS [0x00h] is 0x01 which
indicates, current state of the charger state-machine is in
Trickle-Charge condition.
Change-Id: Ic4b985c71ff68ea4f5ab22e18feab03d776ec134
Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/376939
Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
To be able to parse binary panicinfo from feedback reports, we need
a host tool:
- Move panicinfo generic parsing functions to a separate C file
- Create a new host utility to parse panicinfo
BRANCH=none
BUG=chromium:643062
TEST=base64 -d | ec_parse_panicinfo
Change-Id: Idd8560a2894f270d0ab3a9f654c333135759e57f
Reviewed-on: https://chromium-review.googlesource.com/379639
Commit-Ready: Nicolas Boichat <drinkcat@chromium.org>
Tested-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reads of the TPM fifo by the Host are done in chunks of up to 63 bytes
at a time. The existing routine used to copy data read from the TPM
layer to the I2CS fifo operates one byte at a time. This method is
fine for single and four byte register reads. However, for larger
buffers the performace can be improved by aligning the the fifo write
pointer to be at a word boundary.
BRANCH=none
BUG=chrome-os-partner:40397
TEST=manual
Utilized test code on the host to initiate TPM fifo reads of various
lengths and added timing markers on the Cr50 to compare performance
between the existing byte at a time and the new full buffer write
funciton. Verifed that the fifo reads will still correct and compared
the time consumed copy TPM fifo data to the I2CS HW fifo.
This test processed 1910 bytes over 34 fifo reads.
Byte at a time method:
1910 bytes: 6375 uS: Avg Time = 3.233 uS per byte
Full buffer write:
1910 bytes: 3009 uS: Avg Time = 1.57 uS per byte
Change-Id: I3a47a350ab7af740a452fd115c33117b453b9611
Signed-off-by: Scott <scollyer@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/377663
Commit-Ready: Scott Collyer <scollyer@chromium.org>
Tested-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
This CL adds support for reading of TPM fifo registers. Since I2C does
not provide means to communicate how many bytes the host wants to read
there must be some handshake involved between the host and Cr50.
The method added by this CL to allow Host reads of the TPM fifo
assumes the following steps:
1. Host reads burstcount from Cr50 (which will be set to default 63)
2. Host reads 1st 10 bytes of the TPM response.
3. Cr50 will copy MIN(burstcount, msg_len) bytes into its I2CS HW fifo
4. Host computes msg_len and calculates amount of data still buffered
5. Host does a TPM fifo read of buffered data only
(The following steps are repeated until the response read is complete)
6. Host reads burstcount from STS register.
7. Host issues read of burscount bytes from TPM fifo
8. I2CS will copy burstcount amount of bytes in to I2CS HW fifo
9. TPM layer sets burstcount to MIN(63, remaining msg bytes)
The version register is treated similar to a fifo access. The data
written or the number of bytes is a don't care, but there must be
at least one byte of data written with the version register write.
In the case of reads, the host must read burstcount bytes of the
version register. If burstcount is longer than the Cr50 version string
there is no issue because the version register read function always
returns the number of bytes requested, stuffing in 0s once the end of
the version string is reached.
BRANCH=none
BUG=chrome-os-partner:40397
TEST=manual
Created test code in coreboot that exercises TPM register reads and
writes. In addition, created a means to spoof a TPM cmd send and
response read by Host. For these tests the header length is defined as
10 bytes and used 3 different payload lengths. The results for a
payload length of 256 and 39 (message < 63) are shown below. Note the
0xaa and 0x55 have been inserted by the TPM spoof code on the host to
mark the end of the header.
=================================================
Cr50 TPM Register Read tests
TPM Access = 0x0
TPM2 STS = 0x4003f80
TPM2 DID_VID = 0x281ae0
DID = 0x28, VID = 0x1ae0
Ver segment read 1, ret = 0
Version: B2:0 RO_A:0.0.1/84e2dde7 RW_A:0.0.1/cr50_v1.1.5151-acaef21+
=================================================
TPM Cmd: 266 bytes, Hdr = 10, Payload = 256 (last = ff)
TPM STS: Sending command_ready
fifo wr: burstcount = 63
fifo wr: Sent TPM Cmd: len = 266 bytes
TPM STS: Sending TPM GO
TPM STS: data_avail set
TPM STS: 04 00 3f d0: burst = 63
fifo rd: Msg_len = 266
fifo rd: Hdr Len = 10, fifo_adjust = 53
fifo rd: Drained Cr50 HW fifo of 53 bytes
fifo rd: burst = 63
fifo rd: burst = 63
fifo rd: burst = 63
fifo rd: burst = 14
fifo rd: complete 266 byte msg read
[0000]: 00 00 00 00 01 0a 00 00 aa 55 00 01 02 03 04 05
[0010]: 06 07 08 09 0a 0b 0c 0d 0e 0f 10 11 12 13 14 15
[0020]: 16 17 18 19 1a 1b 1c 1d 1e 1f 20 21 22 23 24 25
[0030]: 26 27 28 29 2a 2b 2c 2d 2e 2f 30 31 32 33 34 35
[0040]: 36 37 38 39 3a 3b 3c 3d 3e 3f 40 41 42 43 44 45
[0050]: 46 47 48 49 4a 4b 4c 4d 4e 4f 50 51 52 53 54 55
[0060]: 56 57 58 59 5a 5b 5c 5d 5e 5f 60 61 62 63 64 65
[0070]: 66 67 68 69 6a 6b 6c 6d 6e 6f 70 71 72 73 74 75
[0080]: 76 77 78 79 7a 7b 7c 7d 7e 7f 80 81 82 83 84 85
[0090]: 86 87 88 89 8a 8b 8c 8d 8e 8f 90 91 92 93 94 95
[00a0]: 96 97 98 99 9a 9b 9c 9d 9e 9f a0 a1 a2 a3 a4 a5
[00b0]: a6 a7 a8 a9 aa ab ac ad ae af b0 b1 b2 b3 b4 b5
[00c0]: b6 b7 b8 b9 ba bb bc bd be bf c0 c1 c2 c3 c4 c5
[00d0]: c6 c7 c8 c9 ca cb cc cd ce cf d0 d1 d2 d3 d4 d5
[00e0]: d6 d7 d8 d9 da db dc dd de df e0 e1 e2 e3 e4 e5
[00f0]: e6 e7 e8 e9 ea eb ec ed ee ef f0 f1 f2 f3 f4 f5
[0100]: f6 f7 f8 f9 fa fb fc fd fe ff 00 00 00 00 00 00
=================================================
TPM Cmd: 49 bytes, Hdr = 10, Payload = 39 (last = 26)
TPM STS: Sending command_ready
fifo wr: burstcount = 63
fifo wr: Sent TPM Cmd: len = 49 bytes
TPM STS: Sending TPM GO
TPM STS: data_avail set
TPM STS: 04 00 3f d0: burst = 63
fifo rd: Msg_len = 49
fifo rd: Hdr Len = 10, fifo_adjust = 39
fifo rd: Drained Cr50 HW fifo of 39 bytes
fifo rd: complete 49 byte msg read
[0000]: 02 00 00 00 00 31 00 00 aa 55 00 01 02 03 04 05
[0010]: 06 07 08 09 0a 0b 0c 0d 0e 0f 10 11 12 13 14 15
[0020]: 16 17 18 19 1a 1b 1c 1d 1e 1f 20 21 22 23 24 25
[0030]: 26 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
Change-Id: I0e05156d6012c6dc86844e4c0ea80cc04f45734a
Signed-off-by: Scott <scollyer@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/374528
Commit-Ready: Scott Collyer <scollyer@chromium.org>
Tested-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
Removed 3 TPM register definitions which were not used in
tpm_registers.c and added missing entries to the I2CS translation
table for TPM register address lookup.
Moved the SPI specific locality 0 offset from tpm_registers.c to
sps_tpm.c so the register defines in tmp_registers.c can be
common to both the SPS and I2CS interface.
BRANCH=none
BUG=chrome-os-partner:40397
TEST=manual
For I2CS verification on Reef AP console used the command 'i2cget
-y 8 0x50 <addr> b' to read both the TPM access and RID register.
For SPI verifcation updated Cr50 FW on Kevin and verified that the
AP successfully boots. Additionally, issued the command from the
Kevin console 'trunks_client --own' and got the following console
output without any errors being listed.
[INFO:tpm_utility_impl.cc(1692)] CreateStorageRootKeys: Created RSA SRK.
[INFO:tpm_utility_impl.cc(1735)] CreateStorageRootKeys: Created ECC SRK.
Change-Id: Ib0b70e22cd46de2c59bd2e73f3c9aebd661e66c4
Signed-off-by: Scott <scollyer@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/368621
Commit-Ready: Scott Collyer <scollyer@chromium.org>
Tested-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
This CL includes changes in Cr50 required to support TPM via
the I2CS interface.
BRANCH=none
BUG=chrome-os-partner:40397
TEST=manual
Limited testing so far. Verified that the I2CS interface is
initialized properly and that register reads occur when
initiated on the AP console via command i2cget -y 8 0x50 0x1 w
Change-Id: I16ac17c7c82d420a384908e4b5a9867a3b24bc9e
Reviewed-on: https://chromium-review.googlesource.com/356241
Commit-Ready: Scott Collyer <scollyer@chromium.org>
Tested-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
Remove timeout to avoid fetching unknown instruction from e-flash
and causing exception.
Also fixed:
- To make sure immu(dynamic cache) is reset after a erasing/writing
operation.
- Verify function is in critical section.
Signed-off-by: Dino Li <dino.li@ite.com.tw>
BRANCH=none
BUG=none
TEST=console commands: "flasherase" and "flashwrite".
Change-Id: I0c84282ac4689cd762159071afae3efeea31d281
Reviewed-on: https://chromium-review.googlesource.com/380500
Commit-Ready: Dino Li <Dino.Li@ite.com.tw>
Tested-by: Dino Li <Dino.Li@ite.com.tw>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
If we're sourcing 5V to the port, consider the port as not providing
power, for the purpose of VBUS / BC1.2 detection.
BUG=chrome-os-partner:55432
BRANCH=None
TEST=Manual on kevin, attach legacy peripheral in one port, zinger in
the other, run "reboot" on EC console, and verify zinger port is
selected as charge port. Also attach Apple charge-thru accessory w/o
charger plugged, verify that charge manager is not informed of a BC1.2 /
VBUS supplier.
Change-Id: Ifbe587215f28756760e7106e1a00dd96319438e3
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/380324
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Port USB firmware update to stm32f4 dwc usb from st usb.
This includes usb dwc usb stream inplementation, generic
endpoint interfaces, and the sweetberry test case.
BUG=chromium:608039
TEST=usb update works
BRANCH=None
Change-Id: Ia26e4f7e990ee64991468799c99b036f5f32190f
Signed-off-by: Nick Sanders <nsanders@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/377520
Reviewed-by: Randall Spangler <rspangler@chromium.org>
To save space of working image, make the console memory commands
optional.
BRANCH=veyron
BUG=b:27849483
TEST=Compile, save 320 bytes.
Change-Id: Ia538b30b4c06955c44b29eb22ed1a09fad83bd9e
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/379115
Reviewed-by: Randall Spangler <rspangler@chromium.org>
