The default setting is to wait 1.3s from receiving the command, to
enable the OTG output: that's too long, and makes time to active
base very long when running on battery.
BRANCH=none
BUG=b:76396020
TEST=Probe POGO 1/5 and one of the USB lines, check that time from
connect to active USB is reduced to 580 ms (from 1920 ms).
Change-Id: Iee00fd27978434ccac052e60a94534919dc29f43
Signed-off-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/981853
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
CONFIG_VSTORE is needed as a part of the verified boot process. When
the AP boots up, it hashes its FW and asks the EC to store this hash.
When resuming, the AP will ask the EC for this hash.
Meowth and Zoombini were missing this option which was a reason why
resume was failing.
This CL simply enables the VSTORE module and adds 1 VSTORE slot.
BUG=b:72472969
BRANCH=None
TEST=With updated AP FW with HAVE_ACPI_RESUME, verify that
suspend/resume works.
Change-Id: I07d0ce3ef426dc1924de6085703a4174f353f83d
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/982598
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Vaibhav Shankar <vaibhav.shankar@intel.com>
Tested-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
A new ebuild allows to install codesigner as /usr/bin/cr50-codesigner,
let's make use of it instead of manually copied instance of the
signer.
BRANCH=none
BUG=b:74100307
TEST=verified that error message is generated if cr50-codesigner is
not installed, and that signing succeeds once cr50-codesigner is
installed.
Change-Id: I468803443e7b052a8ecb074ee80f63f588888985
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/982495
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
No one is using this method and it implies that all chipset should
support the RCIN# Virtual Wire if using eSPI. Only large core chips
use RCIN#; small core chips don't.
This method was introduced for skylake and has since been replaced
since CL:575947 was merged.
BRANCH=none
BUG=none
TEST=build all
Change-Id: Ic541e3d61d1e0ecc64a0bb12385bdada40f0acf2
Signed-off-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/975904
The control of trackpad from EC was entirely removed by CL:421275.
So remove the unnecessary words of disabling touchpad in the comment
of lid_angle_peripheral_enable().
BUG=none
BRANCH=poppy
TEST=none
Change-Id: Ie688d9dc98c5f6f60a9d3908945495f4b6fdb00d
Signed-off-by: Kaiyen Chang <kaiyen.chang@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/979572
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
CL:957872 introduced "get_time().val + 400" as the deadline to perform
compensation and the comment in bma2x2.c mentioned the deadline should be
400ms. But the unit of val in timestamp_t is microsecond not milisecond
so only 400us is defined not 400ms.
BRANCH=none
BUG=b:76234078
BUG=b:76202592
TEST=test manually on the dut by performing calibrate.
Change-Id: I7a834ef6dcb0772569d2c8d6c507803deb5d2fc1
Signed-off-by: Marco Chen <marcochen@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/979512
Commit-Ready: Gwendal Grignou <gwendal@chromium.org>
Tested-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-by: Gwendal Grignou <gwendal@chromium.org>
We have a growing list of boards in chip/npcx/system.c that are
unable to distinguish a reset from a power-on or a reset-pin type.
Instead of being a temporary issue this is now solidified in the
design on some kabylake boards.
Instead of defining board-specific checks in the chip code this
change adds a config option that the relevant boards can define.
BUG=b:76232539
BRANCH=none
TEST=make -j buildall passes
Change-Id: I76e0f011d70ce6f778b1fb6a56c2779c39c3cbd6
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://chromium-review.googlesource.com/979575
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
The keyboards that have an assistant key also move the row that
the refresh key is on from 2 to 3. The row is hardcoded and
used by the early boot key detection code to determine if
boot keys should be honored.
The fallout from not having the right refresh row defined was
not seen on Eve because that board has a different quirk where
it does not distinguish reset-pin vs power-on reset types so
the test in check_boot_keys() was not failing.
BUG=b:76232955
BRANCH=none
TEST=manual testing on Eve board
Change-Id: I5b94b4e32024afa1768bdf371a7eb951753014e8
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://chromium-review.googlesource.com/979574
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
In APL & GLK, cold reset code does a AP force shutdown (with board
specific AP shutdown code) by power sequencing the SOC all the way
to S5 and bring it back to S0. However there is no separate GPIO
in APL & GLK for doing AP cold reset hence removed the AP cold
reset logic.
BUG=b:72426192
BRANCH=none
TEST=make buildall -j
Manually verified on GLKRVP, apreset cold & warm behave same
Change-Id: I6ee5e4c4df94e685acdabe31b8b5554295883792
Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/974107
Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
This is helpful during early debugging to identify if the EC is up and
running. This will be later cleaned up as part of LED support for
yorp.
BUG=b:74952719
BRANCH=None
TEST=Verified that blue led glows up on booting up EC.
Change-Id: I4670c210045c649a926e7c3f23c5d6097df69e3d
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://chromium-review.googlesource.com/979270
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
GPP_B14_STRAP is being moved due to a change in EC SKU. We're not
currently using this pin, but if we decide to in the future, we can set
up the appropriate one based upon reading the Chip ID register.
BUG=b:71717245
BRANCH=None
TEST=Build and flash on both ECs, verify that they both boot up
normally.
Change-Id: Iaa25d5d77939bf55d6dc3991eec89ad5d6e92abb
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/978677
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Since all of the uses of CONFIG_USB_PD_TCPM_ANX74XX are actually for
ANX3429, rename the option especially since the ANX7447
driver will not reuse the ANX74XX driver which is being introduced
in CL:956790.
Also adding the CONFIG_USB_PD_TCPM_ANX740X and
CONFIG_USB_PD_TCPM_ANX741X options to advertise which versions of the
ANX chip the anx74xx.c driver applies to.
BRANCH=none
BUG=chromium:824208
TEST=build all
Change-Id: Ib47f4661466e54ff2a0c52d517eb318d3bfd25a2
Signed-off-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/973558
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Recently, when building images for Cr50 the following warnings started
being generated by make:
board/cr50/build.mk:98: warning: overriding recipe for target \
'build/cr50/tpm2/libtpm2.a'
board/cr50/build.mk:98: warning: ignoring old recipe for target \
'build/cr50/tpm2/libtpm2.a'
The reason for this turned out to be changes under
https://chromium-review.googlesource.com/954444
Let's make sure specific make file is not included in the build twice.
BRANCH=cr50, cr50-mp
BUG=none
TEST='make buildall -j' succeeded. Verified that there is no warnings
reported in the make output.
Change-Id: I96924752eb91669957d2b514d8926ac843b2bf93
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/977021
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Jett Rink <jettrink@chromium.org>
The NPCX driver doesn't use anything but >= 0; make everything
consistent as to not imply something is different between UART and
everything else.
BRANCH=none
BUG=none
TEST=none
Change-Id: Ib98f56f7004df2405df7d2cc1847f1ed4b3ec558
Signed-off-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/976524
Reviewed-by: Edward Hill <ecgh@chromium.org>
Seems expected from the kernel side since we are using a SPI interface
for host commands.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=none
BUG=b:71986991
TEST=run on Meowth, check kernel logs.
TEST=re-flash meowth_fp RW partition through the host command interface
e.g. flashrom -p ec:type=fp -i EC_RW -w meowth_fp.bin
Change-Id: I8455ba169d0fca7f99dc040c465693c73cebb6b3
Reviewed-on: https://chromium-review.googlesource.com/966022
Commit-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
ST firmwares are released in FTB format, which can't be written to flash
directly. This python script can convert a file in FTB format into
bin file. Currently, we only support FTB files of whiskers touchpad
firmware.
BRANCH=none
BUG=b:70482333
TEST=manual
Signed-off-by: Wei-Han Chen <stimim@chromium.org>
Change-Id: I179de12663580881347a31f11b5b10659e00b879
Reviewed-on: https://chromium-review.googlesource.com/918603
Commit-Ready: Wei-Han Chen <stimim@chromium.org>
Tested-by: Wei-Han Chen <stimim@chromium.org>
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
For the dual data role, when the state is UFP
assert the otg pins to activate the usb device controller.
This will enable usb gadget mode and the board will act as
usb device instead of host.
For DFP state, de-assert the otg pins to activate the host mode.
BUG=b:74339386
BRANCH=NONE
TEST=Connect two Eve boards with the usb type c cable.
On ec console, type the command usb pd 0 swap data.
pd 0 state should return UFP mode.
Verify that the otg pins are high (USB2_OTG_ID and USB2_OTG_VBUSSENSE).
Change-Id: I0efb08ae3946ff09ce9dfeb89cff049e551fe000
Signed-off-by: Jagadish Krishnamoorthy <jagadish.krishnamoorthy@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/961381
Reviewed-by: Divya S Sasidharan <divya.s.sasidharan@intel.com>
Reviewed-by: Duncan Laurie <dlaurie@google.com>
