It turns out SCLH = 0x5 is still a little fast (411 kHz on hammer),
let's update it to 0x6.
See 5e6f9a2b38 "chip/stm32/i2c-stm32f0: Adjust 400kHz setting (48Mhz clock source)"
for details.
BRANCH=none
BUG=b:36172041
TEST=Measure I2C speed to be <400 kHz on hammer
Change-Id: I2b5acc532963c407144b8e2a7786d3e2302192d3
Reviewed-on: https://chromium-review.googlesource.com/625507
Commit-Ready: Nicolas Boichat <drinkcat@chromium.org>
Tested-by: Toshak Singhal <toshak@google.com>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
In boot protocol mode, we must only send the first 8 bytes of the
report. Also, go back to report mode on USB reset.
When mode is changed, we immediately toggle keyboard endpoint,
to make sure the appropriately sized packet is sent (otherwise,
a longer packet packet will be sent once, which confuses AP
firmware).
BRANCH=none
BUG=b:62004286
BUG=b:64953295
TEST=Flash hammer, check that keyboard works at firmware screen
and in the OS, and that new key works in OS.
Signed-off-by: Nicolas Boichat <drinkcat@chromium.org>
Change-Id: If7d6aa6c2dd127b9de34fc93d06bc0dd6e6128a2
Reviewed-on: https://chromium-review.googlesource.com/627344
Commit-Ready: Nicolas Boichat <drinkcat@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
The STM32F76x is really close to the STM32F4 family, so the most concise
implementation is just using CHIP_FAMILY_STM32F4 and adding
CHIP_VARIANT_F76X.
Tune the clock settings to 180 Mhz CPU clock as the goal is performance.
(over-drive is not implemented yet to get to 216 Mhz)
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=none
BUG=none
TEST=ran on nucleo-f767zi board.
'make BOARD=nucleo-f767 flash', the red LED is on and the green LED
turns on/off when pressing the user button, UART console works properly.
Change-Id: I1f67df3aec874c965c81188df46c72de210728d9
Reviewed-on: https://chromium-review.googlesource.com/612750
Commit-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
Similarly to what we have done with keyboard events, we put touch
events in a FIFO. The AP will need to interpret the timestamp
in the events to be able to process the events correctly tough.
Resume should typically take about 50ms, so a 8-event long FIFO
should be good enough. Also, we bypass the FIFO altogether in most
cases, when the USB interface is not suspended.
BRANCH=none
BUG=b:35775048
TEST=Connect hammer, force autosuspend using:
DEVICE=$(dirname $(grep 5022 /sys/bus/usb/devices/*/idProduct))
echo 500 > $DEVICE/power/autosuspend_delay_ms
echo auto > $DEVICE/power/control
Look at evtest output.
Wait a second, make a swipe, see that events are received in
a very short amount of time after resume (every EP interval/2ms),
but the event timestamps show that some of them are older.
Change-Id: If6ab56396f7d564b19e6c3c528847196ffa4d849
Signed-off-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/612221
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
We use the unofficial, Windows 8, Relative Scan time HID usage
(Digitizer page, 0x56) to add timestamps to our HID touchpad
events.
The timestamps is a rolling, unsigned, 16-bit integer, with a
resolution of 100us (so it wraps around every 6.5s).
The host will be able to synchronize to that timestamp, resetting
an offset every time the touchpad is quiet a certain amount of
time (e.g. 1 second).
BRANCH=none
BUG=b:63685117
TEST=Flash hammer, timestamps are reported in HID descriptor.
Change-Id: Ie5d56a9df14e464d2cdcd559f550d6e3cc81961f
Signed-off-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/603041
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Put key events in a FIFO. This is especially useful when USB is
suspended, so that we can replay the events on resume. This makes
sure that no key strokes are lost on resume from USB autosuspend.
We coallesce events happening within some interval (18 ms), greater
than EP interval (16 ms) to ensure we cannot have a backlog of keys.
The interval must also be short enough to ensure that the intended
order of key presses is passed to AP, and that we do not coallesce
press and release events (which would result in lost keys).
We also discard key events in the FIFO buffer that are older than
1 second. Note that we do not fully drop them, we still update
the report, but we do not send the events individually anymore
(so an old key press and release will be dropped altogether, but
a single press/release will still be reported correctly).
BRANCH=none
BUG=b:35775048
TEST=Connect hammer, force autosuspend using:
DEVICE=$(dirname $(grep 5022 /sys/bus/usb/devices/*/idProduct))
echo 500 > $DEVICE/power/autosuspend_delay_ms
echo auto > $DEVICE/power/control
Wait a second, type something quickly, verify that no keys are lost.
Change-Id: I64d33c15a39ae33af42039fba62cf4ed3abef462
Signed-off-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/471188
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
As suggested in CL:411741, makes the follow-up CL that buffers
key strokes much simpler.
We can revisit later if we can still sneak it that change, but,
all in all, we can guarantee the same key latency by halving the
USB endpoint interval.
BRANCH=none
BUG=b:35775048
TEST=Connect hammer, keyboard works.
Change-Id: I6624fde9bd5561ddceb7ce195470d7af7cca7140
Signed-off-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/471187
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Some USB interface handlers need to know when USB has been
successfully resumed after a wake event. For example, this is
useful so that HID keyboard can send the events at the right time.
BRANCH=none
BUG=b:35775048
TEST=Using USB HID keyboard patches to queue keys in a FIFO:
After USB autosuspends, press a single key and hold it. Without
this patch the endpoint data only gets reloaded on the _next_
event.
TEST=On hammer, I2C passthrough still works.
Change-Id: I9b52b9de16767c8a66c702a5ae70369334a3d590
Signed-off-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/569547
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
To enable console with DMA, we need to specifically
remap DMA channels for USART1.
ch2/3 and ch6/7 are already used by SPI1/2 modules.
So we have to remap USART1_TX to ch4 and USART1_RX to ch5.
BUG=b:64575809
BRANCH=none
TEST=confirm ec console works on scarlet rev1
Change-Id: Ie2bb141c72252aee98e4cd4a284a01b4d57605f4
Signed-off-by: Philip Chen <philipchen@google.com>
Reviewed-on: https://chromium-review.googlesource.com/611147
Commit-Ready: Philip Chen <philipchen@chromium.org>
Tested-by: Philip Chen <philipchen@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Indentation is growing out of control, let's move to a separate
function so that we can return early.
BRANCH=none
BUG=b:35775048
TEST=Flash hammer, usb_wake works.
Change-Id: I9abf99ff55b3977dfc307fc99aac6f1ab7dd1f6a
Signed-off-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/612922
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
When resuming from S3, it may take a while for the bus to become
alive again, so let's increase the timeout. 3 seconds is probably
a bit too long, but should work for our purpose: we just do not
want to be stuck in that state forever.
BRANCH=none
BUG=b:35587173
TEST=Use powerd_dbus_suspend to put poppy in S3. Press key, see
that hosts sometimes takes ~90ms, but sometimes up to 1.5s
to resume.
Change-Id: Ic800481b2b500fb68a8d1de16b11cbe77a4013d4
Reviewed-on: https://chromium-review.googlesource.com/569523
Commit-Ready: Nicolas Boichat <drinkcat@chromium.org>
Tested-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
In the previous version of the code, we were counting ESOF (every
ms) to figure out when to clear the resume bit, and then using ESOF
counts again to wait for the USB interface to resume.
This missed the fact that ESOF (expected SOF) interrupts are not
triggered when SOF are actually received.
Somehow, this worked fine in most cases, except that sometimes the
last ESOF would race with the RXDP/RXDM going to state 2, and we
would not know that the resume completed successfully.
Let's also count SOF interrupts, and also take a received SOF as an
indicator of a successful resume.
While we're at it, trim down USB debugging messages, and add a line
when resume is successful.
BRANCH=none
BUG=b:35587173
TEST=Connect hammer, force autosuspend using:
DEVICE=$(dirname $(grep 5022 /sys/bus/usb/devices/*/idProduct))
echo 500 > $DEVICE/power/autosuspend_delay_ms
echo auto > $DEVICE/power/control
Add debugging in hammer code, make sure that usb_wake_done goes
back to 1 after resume succeeds.
Change-Id: I206c9c6b3066a3a337b6bd2370c9d0c6a9e2396c
Reviewed-on: https://chromium-review.googlesource.com/569522
Commit-Ready: Nicolas Boichat <drinkcat@chromium.org>
Tested-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
id only really needs 4 bits (16 touch events should be more than
enough), so we can steal 2 bits from that field.
We also reorder the fields to make sure that width/x are aligned
on 8-bit boundary.
BRANCH=none
BUG=b:63936194
TEST=Flash hammer, touchpad works, ABS_PRESSURE > 255 is reported
when a palm is pressed on the touchpad.
Change-Id: I1abf1bf53cc9dd998082cea5dc7cd3be17f99ec6
Reviewed-on: https://chromium-review.googlesource.com/583297
Commit-Ready: Nicolas Boichat <drinkcat@chromium.org>
Tested-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Chun-ta Lin <itspeter@chromium.org>
Reviewed-by: KT Liao <kt.liao@emc.com.tw>
Add support for OTP memory: if needed store serial number in first bank.
BUG=chromium:746471
BRANCH=none
TEST=On sweetberry, check we can write serial number with serialno
command. Check serial number survive a firmware update.
First, check without write protect, check we can write 0s (but not 1s)
serialno
Serial number: NNNNNNNNNNNNNNNNNNNNNN
>
> serial set MMMMMMMMMMMMMMMMMMMMMMMMMMMMM
Saving serial number
Serial number: LLLLLLLLLLLLLLLLLLLLLL
After lock enabled, check we can not overwrite.
> serial set AMMMMMMMMMMMMMMMMMMMMMMMMMMMM
Saving serial number
Serial number: LLLLLLLLLLLLLLLLLLLLLL
Access Denied
Check that serialno returns "Uninitialized" if it was never set.
Change-Id: I9ab08486a7c3e1958e964649640d69b5b70947e3
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/580290
Reviewed-by: Nick Sanders <nsanders@chromium.org>
One Time Programmable memory can be used to store permanent data like
serial numbers.
Reorganize the code to support writing serial number to OTP, in
addition to pstate (if using its own memory bank) or autogenerate from
unique id (hammer).
+ Add CONFIG_OTP to enable OTP code
+ Add CONFIG_SERIALNO_LEN to indicate the size of the serial number
string. Currently set to 28, when USB serial number is needed.
+ Expose flash_read|write_pstate_serial and add otp_read|write_serail,
remove more generic flash_read|write_serial.
+ Make board_read|write_serial generic, declared outside of USB subsystem.
Priority order to read|write serial string:
- board definition (like hammer)
- pstate location, if stored in its private memory bank
- otp area
If none of these methods are available, a compilation error is raised.
BUG=chromium:746471
BRANCH=none
TEST=compile
Change-Id: I3d16125a6c0f424fb30e38123e63cf074b3cb2d3
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/580289
Reviewed-by: Nick Sanders <nsanders@chromium.org>
Currently sweetberry hits an integer truncation issue
at 2.4 ohm when uA per div goes below 1. We can use 100ths
of a uA as the current per div scale.
BRANCH=None
BUG=chromium:608039
TEST=log from sweetberry with 10 ohm config.
Signed-off-by: Nick Sanders <nsanders@chromium.org>
Change-Id: I9e9216230329483fd0bfcb44ce23cd15bae864b3
Reviewed-on: https://chromium-review.googlesource.com/577051
Commit-Ready: Nick Sanders <nsanders@chromium.org>
Tested-by: Nick Sanders <nsanders@chromium.org>
Reviewed-by: Nick Sanders <nsanders@chromium.org>
Unique device ID register (96 bits) is at a different place on STM32F4
compared to other STM32.
BUG=none
BRANCH=none
TEST=Using board_read_serial() from hammer/board.c in
sweetberry/board.c, confirmed that we can extract and assign a unique
USB serial number.
Change-Id: Idb257f0f20422482c729a2b97b4b16ee231ca4d9
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/579575
Commit-Ready: Gwendal Grignou <gwendal@google.com>
Tested-by: Gwendal Grignou <gwendal@google.com>
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
STM32 I2C frequency can be computed as such:
tSCL = tSYNC1 + tSYNC2 + { [(SCLH+1) + (SCLL+1)] x
(PRESC+1) x tI2CCLK }
The default values we use come from the datasheet, which assume,
for 400 kHz setting, that tSYNC1 + tSYNC2 = 750 ns, and therefore
set tSCLH as 500 ns and tSCLL as 1250ns.
On hammer, we measured a total tSCL of ~2150 ns (465 kHz) with
these settings, so we can easily slow it down to ~2500 ns (400 kHz)
by increasing tSCLH to 750 ns (SCLH = 0x5).
As highlighted in 48b2edf031
"stm32f0/i2c: adjust the 100kHz setting to never go above 100kHz"
this has the disadvantage of slowing down other boards where
the RC value on the I2C bus are different, but slowing down should
always be safe, and is the best we can do without adding config
defines for the fall/rise time.
BRANCH=none
BUG=b:36172041
TEST=Flash hammer, measure SCL frequency to be about 400 kHz
Change-Id: Ia2cac9fb09228abd8a318d57335855be529485c2
Signed-off-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/563219
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Before
72afc55bd9 "stm32: cleanup flash-f by using constant from register.h"
lock() function would simply do:
STM32_FLASH_CR = FLASH_CR_LOCK;
which would clear all other bits in STM32_FLASH_CR, including
FLASH_CR_OPTER and FLASH_CR_OPTWRE.
This allow preserve_optb to work, as it does:
1. erase_optb
a. unlock()
b. Set FLASH_CR_OPTER
c. lock() (clears FLASH_CR_OPTER!)
2. write_optb
a. unlock()
b. Set FLASH_CR_OPTPG
c. Write option byte
d. Clear FLASH_CR_OPTPG
e. lock()
After the patch, we now have:
STM32_FLASH_CR |= FLASH_CR_LOCK;
which seems more correct. However, 1.c. does not clear FLASH_CR_OPTER,
and 2.b. ends up with both FLASH_CR_OPTPG and FLASH_CR_OPTER set,
and the programming operation does not do anything.
This patches does 3 things:
- Rename FLASH_CR_OPTSTRT to FLASH_CR_OPTER, as that's the correct
register name for STM32F0 and STM32F3.
- Fix the above by clearing FLASH_CR_OPTER in erase_optb
- Also clear FLASH_CR_OPTWRE in lock(). Not strictly necessary,
but this seems to be the right thing to do.
BRANCH=none
BUG=chromium:739608
TEST=On hammer, type flashwp true; reboot; flashwp all; reboot
flashinfo => All flash is protected
Change-Id: Ic276545ae3c0bdb685c7b117a7f896ec341731bb
Reviewed-on: https://chromium-review.googlesource.com/562839
Commit-Ready: Nicolas Boichat <drinkcat@chromium.org>
Tested-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Wei-Ning Huang <wnhuang@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
PSTATE is already included in WP_BANK_OFFSET + WP_BANK_COUNT,
so this change is not only unnecessary, but also harmful.
BRANCH=none
BUG=chromium:739608
TEST=Flash hammer, flashwp true; reboot; flashinfo
=> RO is protected
Change-Id: I31048c0156eff354fbcc6ae5828a6ef313b56b97
Reviewed-on: https://chromium-review.googlesource.com/561037
Commit-Ready: Nicolas Boichat <drinkcat@chromium.org>
Tested-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
We currently set STM32_FLASH_OPT_LOCKED
to (STM32_FLASH_CR & FLASH_CR_OPTWRE), however the bit is set
when option byte are _unlocked_.
From STM32F0 Reference Manual:
Bit 9 OPTWRE: Option byte write enable
When set, the option byte can be programmed. This bit is set
on writing the correct key sequence to the FLASH_OPTKEYR register.
This bit can be reset by software
BRANCH=none
BUG=chromium:739608
TEST=Flash hammer, flashwp true; reboot; flashinfo
=> hammer does not hang on reboot, RO is protected
Change-Id: I1b6eb5d638534ece90d6d5164586f49bdb0c151d
Reviewed-on: https://chromium-review.googlesource.com/561036
Commit-Ready: Nicolas Boichat <drinkcat@chromium.org>
Tested-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Wei-Ning Huang <wnhuang@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
STM32F0 cannot keep PWM output active when chip is in deep sleep.
The only other board that uses both CONFIG_LOW_POWER_IDLE
and CONFIG_PWM on stm32 is jerry, and this logic should also apply
to it.
Also, switch using_pwm from array to bitmask to simplify handling.
BRANCH=none
BUG=b:36173380
TEST=On AP, tell it to autosuspend hammer:
echo auto > /sys/bus/usb/devices/1-2/power/control
Then see, using idlestats, that hammer does to deep sleep.
In hammer console: pwm 0 50, see that PWM output is stable,
idlestats shows EC does not sleep.
In hammer console: pwm 0 -1, idlestats shows EC sleeps again.
Change-Id: Ic74c1905364fe4335239da95a99193d0e3e979f7
Reviewed-on: https://chromium-review.googlesource.com/541115
Commit-Ready: Nicolas Boichat <drinkcat@chromium.org>
Tested-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
flash_physical_protect_now(), which is called when
EC_FLASH_PROTECT_ALL_NOW is set, should protect the entire flash
temporarily until reboot. Current behavior enable flash protect on all
region permanently. The correct implementation should be writing an
invalid key to the flash controller to disable flash flash only
temporarily until reboot.
Since the implementation of flash-stm32f3 and flash-stm32f4 is almost
the same after restoring the changes made in commit
35f4d8acaa, we merge to file by creating a
symlink from flash-stm32f3.c to flash-stm32f4.c to reduce code
duplication.
BRANCH=none
BUG=b:37584134
TEST=on eve:
1) `ectool --name=cros_tp flashprotect`
Flash protect flags: 0x00000008 wp_gpio_asserted
2) `flashrom -p ec:type=tp --wp-enable
3) `ectool --name=cros_tp reboot_ec`
3) `flashrom -p ec:type=tp --wp-status`
WP: status: 0x80
WP: status.srp0: 1
WP: write protect is enabled.
WP: write protect range: start=0x00000000, len=0x00040000
4) `ectool --name=cros_tp flashprotect`, all_now should present
Flash protect flags: 0x0000000f wp_gpio_asserted ro_at_boot ro_now \
all_now
5) `ectool --name=cros_tp reboot_ec; sleep 0.3; \
ectool --name=cros_tp rwsigaction abort` to stay in RO.
In EC console, `flashinfo`, should show that only RO is actually
flash protected:
Protected now:
YYYYYY..
6) `flashrom -p ec:type=tp -w ec.bin -i EC_RW` works
7) `make BOARD=ryu -j` works (for testing flash-stm32f3.c)
Change-Id: Ia7a60ae8b3084198abb468e4fc8074b4445d6915
Signed-off-by: Wei-Ning Huang <wnhuang@google.com>
Reviewed-on: https://chromium-review.googlesource.com/549681
Commit-Ready: Wei-Ning Huang <wnhuang@chromium.org>
Tested-by: Wei-Ning Huang <wnhuang@chromium.org>
Reviewed-by: Gwendal Grignou <gwendal@chromium.org>
Don't discard irqprio data when the IRQ_PRIORITY macro is used directly
(for watchdog / watchdog timer).
This change is probably a NOP for all platforms, since the power-on
default for the IRQ prio register seems to be zero, which is the same
priority we're setting in our direct use of IRQ_PRIORITY.
BUG=chromium:634701
BRANCH=None
TEST=Verify 'prio_44' entry exists in irqprio section by checking
ec.RO.map on kevin.
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: Idaffc484a2ce4749c18212f179b3951ff570aed0
Reviewed-on: https://chromium-review.googlesource.com/545201
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
On stm32f412, AHB prescaler must be 1 in order for stm32f412 to be
clocked at greater than 50MHz. APBX prescaler must be 2 so the clocks
can be in the right range. When APBX prescaler != 1, it results in 2x
timer clocks on both APB1 and APB2. We added a new
clock_get_timer_freq() function for stm32 to get timer specific clock
frequency so we can return 2x timer clocks when APBX != 1.
Flash latencies also need to be changed when we clock at 96MHz, the
FLASH_ACR_LATENCY defines are moved into the variant-specific switches
so each board can defined latency when setting CPU clocks.
BUG=b:38077127
TEST=`make BOARD=rose -j`, touch performance improved by 2x.
Change-Id: Ieb211ad80c168d3f57e72a8d16b954b703ee1444
Reviewed-on: https://chromium-review.googlesource.com/539375
Commit-Ready: Wei-Ning Huang <wnhuang@chromium.org>
Tested-by: Wei-Ning Huang <wnhuang@chromium.org>
Reviewed-by: Rong Chang <rongchang@chromium.org>
By default, read USB serial number from flash, but provide a way
for boards to override the function (e.g., to read serial number
from unique chip id).
BRANCH=none
BUG=b:62280271
TEST=Flash hammer
lsusb -d 18d1:5022 -v -v | grep iSerial
shows different chip IDs on different boards.
Change-Id: I0917752bb8e04c1eff4dffc0b3714f63dcd942b0
Reviewed-on: https://chromium-review.googlesource.com/523045
Commit-Ready: Nicolas Boichat <drinkcat@chromium.org>
Tested-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Nick Sanders <nsanders@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Add nucleo-f411re for testing STM32F411.
Fix registers.h to include F411 specific features.
TEST=Check uart,gpio works. Check BMI160 accel/gyro sensor works over
i2c
Install firmware with "make BOARD=nucleo-f411re flash"
BUG=b:38018926
BRANCH=none
Change-Id: I8514d1aa48e06708053e72f8d4be15738eda6cf4
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/249994
Reviewed-by: Alexandru M Stan <amstan@chromium.org>
Add support to write and erase all flash with flashrom.
Add support to use all the memory.
Note that PSTATE must not used its own page, as the STM32F4 use big pages.
BUG=b:38018926
BRANCH=none
TEST=With flashrom, write all, RO, RW regions.
Use flash command on the console, including flashwp
Change-Id: I4f0aee1b3a4f342bdf4ca97bf5d8e8bcc153fd9c
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/264032
Commit-Ready: Wei-Ning Huang <wnhuang@chromium.org>
Tested-by: Wei-Ning Huang <wnhuang@chromium.org>
Reviewed-by: Alexandru M Stan <amstan@chromium.org>
There is a new keyboard matrix layout:
- We can map the search key to both KSO1, KSI0 and KSO0, KSI3
(old layout will only use the former, new layout will use the latter).
- There is a new key on KSO0, KSI5, which we can map to HID page 0xffd1
code 0x0018.
BRANCH=none
BUG=b:62004286
TEST=Flash hammer
kbpress 0 3 1; kbpress 0 3 0 reports KEY_LEFTMETA as expected
kbpress 0 5 1; kbpress 0 5 0 reports "BTN_0", which is probably
incorrect, and needs to be fixed.
Change-Id: I9fb428805ff756b6d63f50cc5b061c6a0e1defbc
Reviewed-on: https://chromium-review.googlesource.com/512502
Commit-Ready: Nicolas Boichat <drinkcat@chromium.org>
Tested-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Use constants from registers.h, to easily support other ECs.
Fix indentation in registers.h
BRANCH=none
TEST=compile + following patches tested on STM32F411
BUG=None
Change-Id: Iecb3ce759a5c4ff13463e7df1cb7e03fc1ce6f69
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/264030
Reviewed-by: Alexandru M Stan <amstan@chromium.org>
We need to process the stop condition after slaver receiver is executed,
or else we will lost the last byte of the transmission.
BRANCH=none
BUG=b:38510075
TEST=`make BOARD=rose -j`, AP suspend/resume should complete within 3 secs
Change-Id: I6390a908b6c05b875b8bb2c0a124292785110b20
Signed-off-by: Wei-Ning Huang <wnhuang@google.com>
Reviewed-on: https://chromium-review.googlesource.com/512463
Commit-Ready: Wei-Ning Huang <wnhuang@chromium.org>
Tested-by: Wei-Ning Huang <wnhuang@chromium.org>
Reviewed-by: Rong Chang <rongchang@chromium.org>
First, libpayload expects the keyboard interface index to be 0.
Then, hid_iface_request needs to reply to USB_HID_DT_HID request
with the content of struct usb_hid_descriptor. With current code,
the variable name is generated (and therefore hard to guess), so
we create a new set of macros so that we can use a specific
variable name.
Also, add support for HID Get_Protocol and Set_Protocol, as they
are compulsory for devices supporting boot protocol, even though
those are mostly no-op for now.
Finally, add a note regarding USB HID keyboard boot protocol, to
make sure that we do not accidentally change the report format.
BRANCH=none
BUG=b:36538963
TEST=Keyboard works in FW screen, both trackpad and keyboard
still work when AP has booted.
TEST=hammer/staff can still be updated (both RO from RW, and RW
from RO)
Change-Id: Ibea4888385909c9ce3b430464e5805c039d4b9ed
Reviewed-on: https://chromium-review.googlesource.com/505796
Commit-Ready: Nicolas Boichat <drinkcat@chromium.org>
Tested-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Some chip supports two owned slave address. The second slave address is
used for other purpose such as board specific i2c commands. This option
can be set if user of the second slave address requires larger host
packet er size.
BRANCH=none
BUG=b:37187312
TEST=`make BOARD=rose -j`
Change-Id: I8d0b04bf4dded55e3957c7b25d849663299593e5
Signed-off-by: Wei-Ning Huang <wnhuang@google.com>
Reviewed-on: https://chromium-review.googlesource.com/472288
Commit-Ready: Wei-Ning Huang <wnhuang@chromium.org>
Tested-by: Wei-Ning Huang <wnhuang@chromium.org>
Reviewed-by: Rong Chang <rongchang@chromium.org>
This patch clones I2C slave and hostcmd driver from stm32f0.
This patch contains contribution from Wei-Ning Huang <wnhuang@chromium.org>
for fixing i2c slave transmitter (CL:471726).
BUG=chromium:688979
TEST=build and load on dev board, run i2cget/set on host and check
return value.
BRANCH=none
Change-Id: I3d159d5bdd4bda6c229cf6d275ab4982836628dc
Signed-off-by: Rong Chang <rongchang@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/461037
Tested-by: Wei-Ning Huang <wnhuang@chromium.org>
Reviewed-by: Wei-Ning Huang <wnhuang@chromium.org>
In principle, trackpad dimensions (logical and physical), can be
probed from the trackpad at runtime, but this would slow down setup
time, as we need to wait for the trackpad to be initialized to read
those. Also, we do not have a framework to generate HID report
at runtime, and a new base with new trackpad would probably require
a new overlay anyway.
Also, set appropriate (temporary) values for both hammer and staff.
BRANCH=none
BUG=b:38277869
TEST=Connect hammer/staff to host, correct logical dimensions are
shown in evtest, and resolution is always 32.
Change-Id: I39b84274d71ca2f4e285f3324c0841331aae9bc1
Reviewed-on: https://chromium-review.googlesource.com/505856
Commit-Ready: Nicolas Boichat <drinkcat@chromium.org>
Tested-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Since a04fc68e72 "usb_i2c: refactor into common", the code in
chip/stm32/usb_i2c.* is dead, let's remove it to avoid confusion.
BRANCH=none
BUG=b:35578857
TEST=On hammer, userspace application can still talk to trackpad.
Change-Id: Idd9cc1109c80f3949fa8c4e50f4fe2e267d5a7ae
Reviewed-on: https://chromium-review.googlesource.com/492768
Commit-Ready: Nicolas Boichat <drinkcat@chromium.org>
Tested-by: Chun-ta Lin <itspeter@chromium.org>
Reviewed-by: Nick Sanders <nsanders@chromium.org>
When usb_wake is called (key press, trackpad event), pulse
detection pin for 100us. This allows Lid EC to wake the AP
even when it is in deep S3 mode, where normal wake using USB
lines does not work.
BRANCH=none
BUG=b:35775062
TEST=Flash hammer, looks at poppy console: base power is not
disconnected, but events appear in the console.
Change-Id: I7b8ee407046d4caa1ce75190c30d693b71b00d2e
Reviewed-on: https://chromium-review.googlesource.com/448380
Commit-Ready: Nicolas Boichat <drinkcat@chromium.org>
Tested-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Current usb_wake was sleeping between setting and clearing RESUME
bit, which is unprecise.
Instead, we count ESOF interrupts in usb_interrupt to detect when
to clear RESUME.
It is also important that usb_wake does not block, as the calling
task (e.g. keyboard scanning) must continue to service events while
the USB device is resuming.
BRANCH=none
BUG=b:35587173
TEST=Connect hammer, force autosuspend using:
DEVICE=$(dirname $(grep 5022 /sys/bus/usb/devices/*/idProduct))
echo 500 > $DEVICE/power/autosuspend_delay_ms
echo auto > $DEVICE/power/control
Wait a second, type something quickly, verify that no keys are lost.
Change-Id: I53b46cce5a4adb0ee4c4a7e9f935c00f7f321636
Reviewed-on: https://chromium-review.googlesource.com/490129
Commit-Ready: Nicolas Boichat <drinkcat@chromium.org>
Tested-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
