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We need to change PLL settings if host apply eSPI operating frequency higher than 50MHz, because FND clock is required to be higher than half of operating frequency. BRANCH=none BUG=b:70537592 TEST=Change PLL succeed with chip select is low. Change-Id: Ieba62f33ed024aed7a8e7f4cc48b1398ed781170 Signed-off-by: Dino Li <Dino.Li@ite.com.tw> Reviewed-on: https://chromium-review.googlesource.com/817717 Reviewed-by: Randall Spangler <rspangler@chromium.org>