BRANCH=smaug
BUG=chromium:506101
TEST=On samus, check we can set the offset and are taken into account.
Check the bias added is correct in the measurements.
Change-Id: I6cf06271ac080a47a008a342d9d108fd302241cc
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/283164
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Add code to store bias from AP at boot and correct
raw data from accelerometer on the fly.
Also return the raw data on 16 bits, as recommned by sysfs.
BRANCH=smaug
BUG=chromium:506101
TEST=check set and get offset works fine.
Check value from accelerometer are sane (on Samus).
Change-Id: Ia62f02aadb9e11988edf0049a0cfee817641db88
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/283163
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Add code to store bias from AP at boot and correct
raw data from accelerometer on the fly.
Also return the raw data on 16 bits, as recommned by sysfs.
BRANCH=smaug
BUG=chromium:506101
TEST=check set and get offset works fine.
Check value from accelerometer are sane (on Samus).
Change-Id: I2ad4ce601665b497527dc8c6acb6e7d398366afe
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/283162
Move calibration in the EC to returns raw value with offset already
applied, as recommended by iio interface.
BRANCH=smaug
TEST=On Samus, with kernel change CL:283103
Check raw value are returned properly.
BUG=chromium:506101
Change-Id: I3dcb4f2fcfff35639e3bfdcc6c1468bdb5e53c45
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/283161
Reviewed-by: Alec Berg <alecaberg@chromium.org>
All boards in ToT have the same RO configuration.
Boards which define CONFIG_FLASH_PSTATE_BANK have pstate following RO.
BRANCH=none
BUG=chrome-os-partner:22990
TEST="git grep" to see that none of the affected functions are called.
Change-Id: Ie1eb9a726e1fa157852b0c55d474c9b4587c41f0
Signed-off-by: Myles Watson <mylesgw@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/273908
Reviewed-by: Randall Spangler <rspangler@chromium.org>
rename setup_openocd -> flash_openocd
refactor so that flash_npcx and flash_lm4 set OCD_CMDS and call flash_openocd
BRANCH=none
BUG=chrome-os-partner:22990
TEST=run flash_ec before and after and compare the sequence of calls to
dut-control and the command-line args to openocd
tested with ryu (non-lm4), samus, link, npcx_evb, and peppy
Change-Id: I7a05e3219d4b324bcf19a20f86b149f8e3377465
Signed-off-by: Myles Watson <mylesgw@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/273907
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Avoid duplicating servo configurations for every chip.
BRANCH=none
BUG=chrome-os-partner:22990
TEST=None. This is an intermediate step to make it clear what's happening.
CQ-DEPEND=CL:273950
Change-Id: I448543b6ab9d39423955e8d2589b6035c59e838a
Signed-off-by: Myles Watson <mylesgw@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/273906
Reviewed-by: Randall Spangler <rspangler@chromium.org>
This adds a module that attaches to the SPS driver to process
host commands delivered over the SPI slave interface.
BUG=chrome-os-partner:40969
BRANCH=none
TEST=make buildall
This feature is not yet enabled, so there's nothing new to test.
That will come next.
Change-Id: If57a6fce698a7eb050e2a68b7f4d18d8b0e2956f
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/284010
Reviewed-by: Randall Spangler <rspangler@chromium.org>
1. Added new config option CONFIG_USB_PD_TRY_SRC
2. Added pd_try_source_enable global flag with console command
3. Added bit to pd.flags to indicate Try.SRC states are active
BUG=chrome-os-partner:39724
TEST=Manual samus to samus with the Try.SRC enabled on both and just
one samus. Tested Samus to Honeybuns and Samus to Zinger connections.
BRANCH=TOT
Change-Id: Ifa5d5d82e443f376e546aaf852ff24d92ef04d72
Signed-off-by: Scott Collyer <scollyer@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/282052
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Tested-by: Alec Berg <alecaberg@chromium.org>
1. Add flash control module for emulation board.
2. Fix system jump for Andes core.
3. Change the physical size of the flash on the chip to 256KB.
note:
1. Only IT839x series supports flash write protect by registers.
2. Static DMA method of flash code only for IT839x series and IT838x Dx.
Signed-off-by: Dino Li <dino.li@ite.com.tw>
BRANCH=none
BUG=none
TEST=1. console command flashwp and flashinfo
1-a. flashwp enable
1-b. WP asserted and reboot
1-c. flashinfo RO protected now
1-d. WP deasserted and reboot
1-e. No protected
1-f. flashwp disable
1-g. WP asserted and reboot
1-h. No protected
2. console sysjump and sysinfo
2-a. sysjump rw
2-b. jumping to image RW
2-c. sysinfo, Copy : RW, Jumped : yes
2-d. sysjump ro
2-e. jumping to image RO
2-f. sysinfo, Copy : RO, Jumped : yes
3. RO/RW firmware image test
3-a. sysjump rw
3-b. use console command "eflash" to erase RO region,
erase OK and system still work.
3-c. reflash firmware
3-d. sysjump rw, sysjump ro
3-e. use console command "eflash" to erase RW region,
erase OK and system still work.
Change-Id: I7666a095e73026a02fb812e5143bc5172ab713e8
Reviewed-on: https://chromium-review.googlesource.com/271390
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Commit-Queue: Dino Li <dino.li@ite.com.tw>
Tested-by: Dino Li <dino.li@ite.com.tw>
Board jerry was removed from the list in CL 276524. The board share the same
overlay as pinky. So ideally user can call flash_ec with board set to pinky.
This applies to other veyron boards in BUG 505003 as well.
However, servo in the lab runs on ToT, and it only updates firmware of the dut
by calling flash_ec with board name retrieved from the overlay file. Also, lab
has a tool to check the servod's board and the dut's board. That is, if we
change servod to return board name pinky for servo connected to a jerry dut,
the lab script will raise a warning that the servod is running with a wrong
board.
Before we have a good design to really address the issue, I'd like to add jerry
back to flash_ec so the board can run FAFT in the lab.
BUG=chromium:505003
BRANCH=None
TEST=None
Change-Id: I155e79710f2731701af0acdfeab6089701cf52a8
Reviewed-on: https://chromium-review.googlesource.com/283494
Tested-by: Dan Shi <dshi@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Commit-Queue: Dan Shi <dshi@chromium.org>
The SPS (SPI Slave) driver handles incoming traffic from the SPI
master. This abstracts the basic hardware functions into a clean
API so that the response to the SPI bytes can be put into
separate files.
BUG=chrome-os-partner:40969
BRANCH=none
TEST=make buildall
If CONFIG_SPI is not defined, incoming SPI traffic is completely ignored.
Even when it's enabled, nothing is reacting to the traffic so
incoming SPI bytes return 0xFF bytes to the master (SPI traffic
is always bidirectional).
Change-Id: I9bbcebc9c5223b942362200fe43a11ac57dfff40
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/283581
Reviewed-by: Sheng-liang Song <ssl@chromium.org>
This provides a way to experiment with or support random
functionality not specifically related to the normal EC
operation. With this, we can use a standard host command to pass
opaque data blobs between the AP and EC without specifying a
particular meaning to them.
BUG=chrome-os-partner:40969
BRANCH=none
TEST=make buildall
Nothing in the normal EC usage sends these messages. I have a
test/example program coming soon.
Change-Id: I77fe434cbd9151e4c2c22bc36d1ed6063d3bf940
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/283070
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Add a description for the USB HID interface, neaten a bit of
console output. No new functionality.
BUG=none
BRANCH=none
TEST=make buildall
Change-Id: Ie85a0192bc4ab9fa87afb4be41d496545a3b548a
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/283051
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Concurrent SPI transactions are not possible, however in case of external SPI
and flashrom update scenario both host command and vhash trigger transactions.
This adds mutex for the SPI transcation
BRANCH=None
BUG=chrome-os-partner:38103
TEST=on Cyan, run hundreds of flashrom cycles to make sure there are no read,
erase or write errors
Change-Id: If346ebe635387d477dcea5f406a5c31579142e2d
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/282113
Reviewed-by: Shawn N <shawnn@chromium.org>
Commit-Queue: Bernie Thompson <bhthompson@chromium.org>
Tested-by: Bernie Thompson <bhthompson@chromium.org>
Reset cause was recorded / corrected only in RO/RW images.
lfw still has old implementation.This caused sysjump RO/RW to
not jump appropriately.
BRANCH=None
BUG=chrome-os-partner:38103
TEST=on Cyan,sysjump RO and sysjump RW console commands
nd make sure it jumps to the right image.
Change-Id: I37138f552fdd385c98d770d242d896ffc014697c
Signed-off-by: Divya Jyothi <divya.jyothi@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/282210
Reviewed-by: Shawn N <shawnn@chromium.org>
Commit-Queue: Bernie Thompson <bhthompson@chromium.org>
Tested-by: Bernie Thompson <bhthompson@chromium.org>
"RO" is a workaround for GP base instructions.
And now we have added "-mno-gp-direct" option in the NDS32 toolchain.
So the compiler would not generate GP base instructions directly,
and we can remove this "RO".
Signed-off-by: Dino Li <dino.li@ite.com.tw>
BRANCH=none
BUG=chrome-os-partner:24378
TEST=console "version" and "gpioget"
Change-Id: I23cb6374fb8eb57081d713bf5c70b80a87dd2fb5
Signed-off-by: Dino Li <dino.li@ite.com.tw>
Reviewed-on: https://chromium-review.googlesource.com/281862
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Alec Berg <alecaberg@chromium.org>
DP Alternate mode specification defines two bytes in the DP
capabilities payload with respect to pin configs. One that governs
the DFP and the other the UFP. The one that the DP source needs to
examine depends upon whether the UFP is a receptacle or a plug.
Previously we just examined the DFP pin config which was correct for
all UFP plugs but not UFP receptacles. This change fixes that by
examining bit <6> of capability message to determe plug vs receptacle
and in case of receptacle choosing the UFP ping config instead.
Signed-off-by: Todd Broch <tbroch@chromium.org>
BRANCH=samus
BUG=chromium:505652
TEST=manual, hoho & apple (UFP_D plugs) still work.
While I don't have a test for UFP_D receptacle partner device reports
following for its DP caps which should now decode correctly.
<31:24> 00 Reserved/SBZ
<23:16> 1C UFP pin config == C, D, E
<15:08> 00 DFP pin config zero
<07:00> C5 <6> == 1 == receptacle
Change-Id: Ib9e3a808828ff6b8c062baf0fc3c23b3da33c2c3
Reviewed-on: https://chromium-review.googlesource.com/282621
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Commit-Queue: Todd Broch <tbroch@chromium.org>
Tested-by: Todd Broch <tbroch@chromium.org>
When RO/RW sysjump is made watchdog is not disabled. Since LFW needs to
load firmware image into SRAM over SPI, there is a certain chance watchdog
counter will fire in the middle of it.
BRANCH=None
BUG=chrome-os-partner:38103
TEST=on Cyan, run hundreds of flashrom cycles and make sure there is no
watchdog reset
Change-Id: Idafcc6a1c9fb35f04be398a68e3ec05bb2b1425d
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/282112
Reviewed-by: Shawn N <shawnn@chromium.org>
Commit-Queue: Bernie Thompson <bhthompson@chromium.org>
Tested-by: Bernie Thompson <bhthompson@chromium.org>
If flash is being written, any pending hash calculation is likely to
be invalid.
BRANCH=None
BUG=chrome-os-partner:38103
TEST=on Cyan, run hundreds of flashrom cycles to make sure there are no
read, erase or write errors
Change-Id: I915f8db7998c56fc12e7d85173232882fb7ed80d
Signed-off-by: Divya Jyothi <divya.jyothi@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/282211
Reviewed-by: Shawn N <shawnn@chromium.org>
Commit-Queue: Bernie Thompson <bhthompson@chromium.org>
Tested-by: Bernie Thompson <bhthompson@chromium.org>
flashrom on target issues a salvo of flash read commands with small
buffer size (128 bytes). Since there is no yield this starves other
tasks/events including hooks and as result watchdog is never reloaded.
This change makes read function yield to other tasks. In addition,
spi_enable()/disable chaining leads to situations where a SPI can be
disabled in the middle of transcation. This is addressed by keeping
SPI permanently enabled in LFW entry function, as well as in RW/RO
early init functions.
BRANCH=None
BUG=chrome-os-partner:38103
TEST=manual on Cyan, run flashrom -p ec -w xx in cycles, swaping xx so that
flashrom does flash. Make sure there is no watchdog triggered
Change-Id: Id5c50239a1d5c64054d7c660dd03b2be4678221c
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/282111
Reviewed-by: Bernie Thompson <bhthompson@chromium.org>
Commit-Queue: Bernie Thompson <bhthompson@chromium.org>
Tested-by: Bernie Thompson <bhthompson@chromium.org>
When the USB2.0 port is used in device mode, having the D+/D- lines
connected just before resetting the PI3USB9281 (for the 2nd detection
used a BC1.2 debouncing) triggers a misdetection where DCP chargers are
seen as Apple 2.4A chargers.
To avoid this, disconnect the D+/D- lines and let them relax before
triggering the PI3USB9281 reset.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=smaug
BUG=chrome-os-partner:42048
TEST=connect and disconnect a DCP charger to the Smaug type-C port
with the AP running, see it constantly detected as DCP and no Pericom
interrupt storm.
Change-Id: I8f6043439c2c6b52f2689b4947baffe51f62eba8
Reviewed-on: https://chromium-review.googlesource.com/282594
Reviewed-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Trybot-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
Take profit of the hardware input current ramping/back-off integrated
in the BQ2589x charger by setting the current limits higher for BC1.2
USB modes and letting the hardware adjust to the actual charger
limitation depending on the VBUS voltage droop.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=smaug
BUG=chrome-os-partner:42045
TEST=Connect a Nexus 9 DCP charger to Smaug and see the input current
adjusted to 1650mA without brown-out, read back the value properly from
the AP:
$ ectool usbpdpower
Port 0: SNK Charger DCP 4958mV / 1650mA, max 5000mV / 1650mA / 8250mW
Change-Id: I348e5ee4980a5652f72f279ab4e3a7126583b093
Reviewed-on: https://chromium-review.googlesource.com/282584
Trybot-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
Use the new TCPC initialization complete bit in alert register to
signal TCPC readiness instead of checking for USB VID to be set.
BUG=none
BRANCH=none
TEST=load on glados, make sure we can boot without battery.
Change-Id: I4b25c973ece0de6dd3f419c5901cff1d8d05ed95
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/282593
Reviewed-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
add GPIO_SEL_1P8V flag for 1.8v/3.3v selection.
Signed-off-by: Dino Li <dino.li@ite.com.tw>
BRANCH=none
BUG=none
TEST=1. To configure 1.8V/3.3V pin to 1.8V,
set GPIO_SEL_1P8V flag in gpio.inc.
2. The corresponding bit will be set as default value if the pin
is not listed in gpio.inc.
Change-Id: Ica02aabe40b83fcb4d33bd28d717a0633bdef5f3
Reviewed-on: https://chromium-review.googlesource.com/281842
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Commit-Queue: Dino Li <dino.li@ite.com.tw>
Tested-by: Dino Li <dino.li@ite.com.tw>
Add support for pericom mux (port 0) and parade mux (port 1).
BUG=chrome-os-partner:41696
TEST=Verify set() and get() functions set and return consistent values.
Verify that DP and USB are only activated when proper modes are set.
BRANCH=None
Change-Id: I9d42108688a9070b982ae77f77633654bc6505ed
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/282281
Reviewed-by: Alec Berg <alecaberg@chromium.org>
This enables a presubmit hook to check for missing configuration
options. All CONFIG_* options should be defined in include/config.h
along with a brief description of what the config option does.
BUG=chrome-os-partner:26304
BRANCH=none
CQ-DEPEND=CL:281626
TEST=Create a commit modifying a source file with a new CONFIG_* option
and watched the preupload process fail illustrating the error with the
CONFIG_* option.
TEST=make -j buildall tests
Change-Id: I7240b386b4981dcab66811a4829d7d6ebfbf7cb1
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/281826
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Commit-Queue: Aseda Aboagye <aaboagye@chromium.org>
Trybot-Ready: Aseda Aboagye <aaboagye@chromium.org>
Initial support for Parade PS8740 Type-C redriving switch.
BUG=chrome-os-partner:41696
TEST=Manual on Glados in subsequent commit. Verify set() and get()
functions set and return consistent values. Verify that USB SS device
functions when muxes are set to dock or USB.
BRANCH=None
Change-Id: Iedbe53cc76f30ecd969c2ca99a7377ed3b193729
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/282280
Reviewed-by: Alec Berg <alecaberg@chromium.org>
In preparation for adding support for additional USB-C mux chips, add a
new high-level USB-C mux interface usb_mux.c. usb_mux functions are now
called from pd code instead of board-level functions. usb_mux calls down
into a mux chip-specific driver (currently pi3usb30532) or
board-specific drivers which toggle GPIOs (for legacy boards).
BUG=chrome-os-partner:41696
TEST=Manual on Glados in subsequent commit. Verify set() and get()
functions set and return consistent values. Verify that USB SS device
functions when muxes are set to dock or USB. Also, verify that DP
dongle and USB SS device are functional on both PD ports on samus_pd.
BRANCH=None
Change-Id: Ib6477f489310f3be1430585ea09fea26f57e3752
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/281435
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Refactor the tcpm/tcpc split such that the tcpm driver implements
the alert functionality since it may be unique for different tcpc
chips.
BUG=chrome-os-partner:41842
BRANCH=none
TEST=make -j buildall. run on samus and glados.
Change-Id: I23f2d7f8627d5337b8d001a09bf27622be24fe33
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/281631
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
The suspend signal from SoC of oak should be kept at least 50ms.
Add a debounce time for suspend singal detection, to avoid transient
state during SoC boot up.
BUG=chrome-os-partner:42023
BRANCH=none
TEST=plug PD power adaptor to type-c port C1,
The keyboard should be worked (Ensure EC communication is oaky)
Change-Id: I4a6bb4e8ba9d417fe2a3045846d38b2129516d78
Signed-off-by: Ben Lok <ben.lok@mediatek.com>
Reviewed-on: https://chromium-review.googlesource.com/282471
Reviewed-by: Rong Chang <rongchang@chromium.org>
Commit-Queue: Nicolas Boichat <drinkcat@chromium.org>
Updated the VDM information to handle properly the DisplayPort alternate
mode.
Switch to 2+2 (DP+USB3.0) if mode D is entered else use 4 lanes of DP
for mode C.
Set the Multi-Function Preferred bit, so laptops select the mode D.
BUG=none
BRANCH=none
TEST=Tested with samus. Verified we get 36W of power + USB2.0 key +
USB3.0 key + external DP display.
Change-Id: I95e3b3640fd5952faeb24312e387468aed6266c7
Signed-off-by: Scott Collyer <scollyer@chromium.org>
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/267688
Reviewed-by: Todd Broch <tbroch@chromium.org>
There are several cases in the EC code base where a CONFIG_* option is
used somewhere, but not defined within the include/config.h file. This
script aims to fix that. Eventually, it will become a presubmit hook to
actively prevent future offenses.
BUG=chrome-os-partner:26304
BRANCH=none
TEST=cros lint --debug util/config_option_check.py
TEST=Ran script and found offending config options.
TEST=make -j buildall tests
Change-Id: I999d32ebacc636b3fff9e857f3cc46feee475e80
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/281626
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Commit-Queue: Aseda Aboagye <aaboagye@chromium.org>
Trybot-Ready: Aseda Aboagye <aaboagye@chromium.org>
In S3, the EC isn't expecting AP host commands, so it's safe to enable
sleep.
BRANCH=Ryu
BUG=chrome-os-partner:36918
TEST=Check sleep mask in S0 and S3.
Also check sleep mask after sysjump with AP on and with AP off.
Change-Id: I67f0634631f62ee571e18d2870cd4a6926d4e090
Signed-off-by: Vic Yang <victoryang@google.com>
Reviewed-on: https://chromium-review.googlesource.com/251750
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Get the USB hub out of reset only when there is a USB host,
same thing for the DisplayPort hardware.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=none
BUG=chrome-os-partner:37078
TEST=Plug and un-plug Honeybuns to Samus. See both the USB devices
connected and the external display.
Change-Id: Iabbeb0650d18c4c0c3324f47d99f9aaa35601c16
Reviewed-on: https://chromium-review.googlesource.com/281927
Trybot-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
Add npcx_evb_arm board-level driver for arm-based platform.
Add header.c: for booting from NPCX5M5G A3 Booter.
Remove lfw folder due to those functionalitie have been replaced with Booter
Modified drivers for
Patch Set 1:
1. flash.c: Implement UMA lock, tri-state and selection register lock functionalities
2. hwtimer.c: Add ITIM32 for hwtimer
3. lpc.c: Add checking for LRESET
4. system.c: Modified CODERAM_ARCH functions for NPCX5M5G A3 Booter.
5. uart.c: Add support for module 2
Patch Set 2:
6. lpc.c: Modified lpc_get_pltrst_asserted() func
Patch Set 3:
7. minimize the changes for CONFIG_CODERAM_ARCH in common layer
8. comments of Patch Set1/2
Patch Set 4:
9. Modified CONFIG_RO_MEM_OFF point to ro image and keep header as a part of ec.RO.flat.
10. Fixed RO_FRID and RW_FRID issues which caused by CONFIG_CODERAM_ARCH.
Patch Set 5:
11. Modified system.c in common folder for supporting *_STORAGE_OFF.
12. Use *_STORAGE_OFF in firmware_image.lds.S to indicate flat file layout in flash.
Patch Set 6:
13. rebase to newest version
14. system.c: Modified for the newest include/system.h
Patch Set 7:
15. Merge from version 0625
BUG=chrome-os-partner:34346
TEST=make buildall -j; test nuvoton IC specific drivers
BRANCH=none
Change-Id: Ifd7c10b81b5781ccd75bb2558dc236486976e8ed
Signed-off-by: Ian Chao <mlchao@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/272034
Reviewed-by: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Commit-Queue: Shawn N <shawnn@chromium.org>
Switch it to a source-only PD device (as it is)
and add the voltage selection code.
For now, output 12V only for 20V request as the 5V->20V transition is
not monotonic, triggering disconnection detection.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=samus
BUG=chrome-os-partner:37078 chrome-os-partner:41860
TEST=connect to Samus and see it negotiate 5V then 20V,
then manually switch to 12V.
Change-Id: I4fc198245999ff9ce8fec929f305681043d72965
Reviewed-on: https://chromium-review.googlesource.com/259113
Trybot-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
mutex_lock() is called from MEC1322_IRQ_ACPIEC0_IBF
interrupt context, causing deadlock and assertion
in __wait_evt().
In the interrupt context it now checks for mutex lock first.
If the mutex is already locked,, it will disable ACPI
interrupts and defer the memmap mutex lock.
Added LPC interrupt disable/enable functions as needed.
Increased deferred function count where needed.
BRANCH=None
BUG=chrome-os-partner:40820
TEST=Test for suspend-resume, cold, warm reboots and
other general stability.
Change-Id: I3dda0d4635a6b6281faf200c8c7b6fcba8877254
Signed-off-by: Chiranjeevi Rapolu <chiranjeevi.rapolu@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/280418
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
Commit-Queue: Divya Jyothi <divya.jyothi@intel.com>
Tested-by: Divya Jyothi <divya.jyothi@intel.com>
This change enables tmp432 thermal sensor. Enter "tmp432"
or "temps" in ec console and get temperature information.
BRANCH=none
BUG=none
TEST=manual
Enter "tmp432" to get temperature information.
Connect the battery and enter "temps" to get temperature
information.
Change-Id: Ie7a9fb4541c5cb3cfa6a26e95f99fe4aacb3a3d3
Signed-off-by: YH Huang <yh.huang@mediatek.com>
Reviewed-on: https://chromium-review.googlesource.com/280956
Reviewed-by: Rong Chang <rongchang@chromium.org>
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Add the console command "power on/off" for AP power on/off.
BRANCH=none
BUG=none
TEST=manual
enter "power on/off" in the ec console to turn AP power on/off.
Change-Id: I16d2af72bc1bf045e7672acd9471dff0a672aff5
Signed-off-by: YH Huang <yh.huang@mediatek.com>
Reviewed-on: https://chromium-review.googlesource.com/280957
Reviewed-by: Alec Berg <alecaberg@chromium.org>
