There is probability to fail in firmware_ECWatchdog FAFT test by using
CONFIG_WATCHDOG_PERIOD_MS period for check timer. Use
CONFIG_AUX_TIMER_PERIOD_MS instead can fix it.
Modified drivers:
1. watchdog.c: change watchdog check timer period from
CONFIG_WATCHDOG_PERIOD_MS to CONFIG_AUX_TIMER_PERIOD_MS.
BUG=chrome-os-partner:34346
TEST=make buildall -j; test nuvoton IC specific drivers
BRANCH=none
Change-Id: I93e700968751ecd58f032c2f5866cf4f2eb0ffe4
Signed-off-by: CHLin <chlin56@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/324712
Commit-Ready: CH Lin <chlin56@nuvoton.com>
Tested-by: CH Lin <chlin56@nuvoton.com>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
EMBEDDED_MODE was missing from code compiled under
cr50/tpm2, which resulted in code under third_party/tpm2
and cr50/tpm2 inferring differing declarations for
a given type.
BRANCH=none
TEST=tests under test/tpm2 pass
BUG=chrome-os-partner:43025,chrome-os-partner:47524
Change-Id: I56935f5ae8fc45e6b7f71eb239b3e0c325086795
Signed-off-by: nagendra modadugu <ngm@google.com>
Reviewed-on: https://chromium-review.googlesource.com/325471
Commit-Ready: Nagendra Modadugu <ngm@google.com>
Tested-by: Nagendra Modadugu <ngm@google.com>
Reviewed-by: Vadim Bendebury <vbendeb@google.com>
Resetting our state to default without also resetting the power role may
lead to a state / role mismatch.
BUG=chrome-os-partner:49563
TEST=Verify kunimitsu correctly detects charger at either polarity on
sysjump.
BRANCH=glados
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: I239df9793773429e9b84a847e55d6753577fab32
Reviewed-on: https://chromium-review.googlesource.com/325385
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
The makefile is missing an explicit dependency which ensures that the
signer utility is available by the time the RW_B image is built. This
works most of the time, but once in a while RW_B gets ahead in the
race and the build fails.
Adding explicit dependency will prevent this from happening.
BRANCH=none
BUG=chromium:578761
TEST=make buildall -j still succeeds.
Change-Id: I7f5223f51e71b1d78de012bf5d934f1a17c86cc0
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/325031
Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
gcc 5.2 bails out on an inline declaration that isn't followed up with
a definition in the same compilation unit.
BRANCH=none
BUG=chrome-os-partner:49517
TEST=compile tested with coreboot's toolchain. samus, oak and others
that failed now build.
Change-Id: Ic9c28fc12c80e24ea0dbf85f35846fd6a0b56a2d
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://chromium-review.googlesource.com/324970
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
Enable the config option for S0IX power control and set the GPIO to
use power_signal_interrupt_S0.
BUG=chrome-os-partner:49274
BRANCH=glados
TEST=echo freeze > /sys/power/state
Unfortunately currently SLP_S0_L is not asserting so this is difficult
to actually test the EC behavior
Change-Id: I302da7735c9622975e0386a0b4542f41c7231df9
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/324567
Reviewed-by: Shawn N <shawnn@chromium.org>
Charger Low_VSYS_Prochot# threshold voltage assertion is set to
6V hence increased the minimum battery voltage to 6.1V to avoid
unwanted Prochot# assertions.
BUG=none
TEST=Drained the battery to 6.1V, Prochot# pin did not assert.
BRANCH=glados
Change-Id: Ie5d4decf3327a45d64638771dd8a5fc7017db261
Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/324564
Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
Stirring the random pool on CR50 is not currently
supported, so just implement as a no-op.
TEST=none
BRANCH=none
BUG=chrome-os-partner:43025,chrome-os-partner:47524
Change-Id: I32b0144737139e524d4f71a11cc9d4ad939cd9cb
Signed-off-by: nagendra modadugu <ngm@google.com>
Reviewed-on: https://chromium-review.googlesource.com/324620
Commit-Ready: Nagendra Modadugu <ngm@google.com>
Tested-by: Nagendra Modadugu <ngm@google.com>
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
Shut down all PMIC-supplied power rails rather than initiating EC / PD
hibernate. This results in considerable power savings.
BUG=chrome-os-partner:48835
BRANCH=glados
TEST=Manual on chell. Run "hibernate" on EC console, verify that 3.3V EC DSW
rail goes to 0V, and the EC powers up on zinger insert, lid open or power
button press.
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: I7bf0c494ea240183240f5a6abc3d611df8efb45a
Reviewed-on: https://chromium-review.googlesource.com/324087
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Allow boards to take action (such as entering a custom low-power
hibernate-like state) before putting the chip into hibernate state.
BUG=chrome-os-partner:48835
BRANCH=glados
TEST=Manual with subsequent commit on chell. Verify board-level
hibernate callback is called when "hibernate" is run on EC console.
Change-Id: Ie1da044037a74ff8bce5c822f28ce837c62ceec0
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/324086
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
The implementation for sha256_hash() copied
and incorrect number of bytes to the output.
This change provides a fix and a test.
TEST=added test case
BRANCH=none
BUG=chrome-os-partner:43025,chrome-os-partner:47524
Change-Id: I74e98c6f5005a14dd5c0ca19ea7540622dd6c7d7
Signed-off-by: nagendra modadugu <ngm@google.com>
Reviewed-on: https://chromium-review.googlesource.com/324391
Commit-Ready: Nagendra Modadugu <ngm@google.com>
Tested-by: Nagendra Modadugu <ngm@google.com>
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
Adds the the code necessary to support muxed inout peripherals on
cr50 like SPS and SPI0 by adding a new signnal to pin connection
flag. Note these are for direct wired peripherals where no muxing
is necessary, the input pads just need to be enabled.
BRANCH=none
BUG=none
TEST=verified pinmux registers through m3
Change-Id: I1a375a3a14fb44fc4f9ced764fd2c54bb2b91e22
Signed-off-by: Ewout van Bekkum <ewout@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/323848
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
Adds a JEDEC SFDP v1.* compatible Serial NOR Flash driver to control
multiple Serial NOR Flash devices (NOR EEPROMs, etc.). The SFDP tables
are used to discover parts' page sizes and capacities.
This driver only supports parts with capacities under 4GiB. If the
parts are larger than 16MiB, then the 0xB7 4-Byte addressing mode
entry opcode and 0xE9 4-Byte addressing mode exit opcode are required.
This driver also assumes that a 4KiB erase opcode of 0x20 is always
available.
BRANCH=none
BUG=none
TEST=Tested on cr51 with multiple EEPROMs with various SFDP revs
Change-Id: I5c2b757267e23c4f22ac89c6d5048a54b04de0c3
Signed-off-by: Ewout van Bekkum <ewout@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/321922
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
of the two RW images if set.
Imported the Haven "signed_header.h" file into chip/g and fixed prior
references to the util/ copy.
BUG=none
BRANCH=none
TEST=Went through a full update. Simulated a botched update.
Change-Id: I1e4c006ef391270a7e350fea6f43cc1a1b057d0e
Signed-off-by: Nadim Taha <ntaha@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/324109
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
Adds a header with JEDEC SFDP v1.0 (JESD216) & v1.5 (JESD216A)
encoding and decoding support to enable a part agnostic Serial NOR
Flash driver.
BRANCH=none
BUG=none
TEST=Tested through the spi_nor driver
Change-Id: I00b3f0434bfb8582aebad7cd0682445980b57773
Signed-off-by: Ewout van Bekkum <ewout@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/321921
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
We have a limitation for EC interrupt vector registers.
System may read incorrect interrupt number in ISR so we need to add
a workaround to prevent it.
The following is a example that got incorrect interrupt number:
1. REG IVCTx = 0x10. (no interrupt pending)
2. EC INT6 interrupt occurs (IVCTx = 0x16) and jump to ISR.
3. Read interrupt vector register to determine interrupt number.
4. Higher priority interrupt of same interrupt group occurs
(for example: INT134, IVCTx = 0x96) while the system is reading the
interrupt vector register for EC INT6, we may end up with an incorrect
interrupt number between 0x16 and 0x96.
Signed-off-by: Dino Li <dino.li@ite.com.tw>
BRANCH=none
BUG=none
TEST=1. EC interrupts work normally: WUI (GPIO interrupt), timer, uart,
LPC, I2C, and PECI.
2. Console command 'taskinfo'.
Change-Id: I54e61f417ad506eb3b4cd5d0652f64eed9a28a17
Reviewed-on: https://chromium-review.googlesource.com/322097
Commit-Ready: Dino Li <dino.li@ite.com.tw>
Tested-by: Dino Li <dino.li@ite.com.tw>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
This commit updates the cr50 watchdog and hwtimer drivers to use the
hardware header specified regdefs to determine the frequencies for
the cr50 device.
BRANCH=None
TEST=Verified gettime and watchdog behavior on cr51
BUG=chrome-os-partner:46737
Change-Id: Iec7dc56b160dbec1b71077cecfd5561436d6f3ab
Signed-off-by: Ewout van Bekkum <ewout@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/321867
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
The TCPCI specification defines ane optional register
18h 'CONFIG_STANDARD_OUTPUT' providing a standardized way
of steering the high-speed muxes.
Implement the feature as a usb_mux_driver, under the conditional flag
CONFIG_USB_PD_TCPM_MUX.
The USB PD port index should be set in the port_addr field of the
'usb_mux' structure.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=none
BUG=chrome-os-partner:49605
TEST=run pdeval-stm32f072 connected to a Parade PS8751 board and test USB/DP
muxing.
Change-Id: I7e5f0b8ec70b1910b2cff9d106514baca8c899e5
Reviewed-on: https://chromium-review.googlesource.com/322956
Commit-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
After talking with Simon Glass about this we concluded that this was an
optimization that is not needed, as such, and since it is only used in
one location and only available from one chip family I'm removing it.
This further simplifies the GPIO API and removes more uses of port/mask
pairs.
Signed-off-by: Anton Staaf <robotboy@chromium.org>
BRANCH=None
BUG=None
TEST=make buildall -j
Change-Id: I40754a385e0a4fa3a56d67fca1dd59fc8f3cc85a
Reviewed-on: https://chromium-review.googlesource.com/323827
Commit-Ready: Anton Staaf <robotboy@chromium.org>
Tested-by: Anton Staaf <robotboy@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
The new gpio_reset function simplifies the pattern used in this code,
that of returning a GPIO to its original configured state. It also
removes a few instances of using port/mask pairs.
Signed-off-by: Anton Staaf <robotboy@chromium.org>
BRANCH=None
BUG=None
TEST=make buildall -j
Change-Id: I6e411aaf2f0fbc18aca0ed8742c400a0efe5690d
Reviewed-on: https://chromium-review.googlesource.com/324059
Commit-Ready: Anton Staaf <robotboy@chromium.org>
Tested-by: Anton Staaf <robotboy@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
In rare case, executing i2c_interrupt function will generate unnecessary
START condition if START bit is 1 in SMBCTL1.
Please see the layout of SMBCTL1 register below.
Bit [7] - STASTRE
Bit [6] - NMINTE
Bit [5] - GCMEN
Bit [4] - ACK
Bit [3] - EOBINTE
Bit [2] - INTEN
Bit [1] - STOP
Bit [0] - START
In order to set or clear bits of INTEN and NMINTE, we need to read SMBCTL1,
or the bit2,6 and write back to register. But we will issue unnecessary
START condition if bit 0 is 1. (ie. Start condition is not sent yet)
Then FW will receive unexpected SDAST interrupt and sometime it collapses
state machine when i2c receives NACK condition.
The solution is enabling these two bits in i2c_init_bus function. Using
task_enalble/disable_irq (NVIC register) to enable or disable i2c interrupts
instead.
Modified sources:
1. i2c.c: Fixed the bug of i2c caused by writing START bit in SMBCTL1.
2. i2c.c: Add more debug messages for unexpected bus state.
BUG=chrome-os-partner:34346
TEST=make buildall -j; test nuvoton IC specific drivers
BRANCH=none
Change-Id: I37dbb0e5b61f4a5ba12f0638535f8031522c1711
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/322883
Reviewed-by: Randall Spangler <rspangler@chromium.org>
1. The previous EC2I module does not meet section
'7.17.5 EC2I Programming Guide'. We need to correct it to prevent
conflict with H2RAM (LPC I/O cycles 800h ~ 9ffh) which cause LPC keeps
long wait states.
NOTE:
If EC is using EC2I internal bus to access PNPCFG registers while host
accessing EC ram through H2RAM interface at the same time,
the symptom will appear.
2. Remove 'CONFIG_IT83XX_PNPCFG_HOST_ACCESS'.
We don't allow the host access PNPCFG registers.
Signed-off-by: Dino Li <dino.li@ite.com.tw>
BRANCH=none
BUG=none
TEST=1. To use console command 'rwreg' to r/w PNPCFG registers and
there is no error code return.
2. To create a stress test for this change.
- EC use 'ec2i_read()' and 'ec2i_write()' to access PNPCFG
registers per-10ms.
- run ectool 'version' command per-100ms.
Before the change was made, LPC will keep in long wait states
immediately.
After the change, we run the test of ectool 'version' command
over 20000 times.
Change-Id: I84e86fc17ef624d4a60a1a051bc301ebdf56a3da
Reviewed-on: https://chromium-review.googlesource.com/323563
Commit-Ready: Dino Li <dino.li@ite.com.tw>
Tested-by: Dino Li <dino.li@ite.com.tw>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Convert some uses of gpio_set_flags_by_mask to plain gpio_set_flags.
The result is usually more readable due to being able to use the
GPIO_* enum names, and it removes more instances of port/mask
implementation details leaking outside the gpio.c chip specific code.
Signed-off-by: Anton Staaf <robotboy@chromium.org>
BRANCH=None
BUG=None
TEST=make buildall -j
Change-Id: I06a7ad8a53e553a8e432a6abb5b38c25a98df6c6
Reviewed-on: https://chromium-review.googlesource.com/323815
Commit-Ready: Anton Staaf <robotboy@chromium.org>
Tested-by: Anton Staaf <robotboy@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
This adds a temporary secure storage interface for the EC to be able
to store small amounts of data from the host that is locked until the
chipset resets. This is used by pre-memory verified boot on x86 systems
where we need to know which RW slot to boot and what the hash is to
ensure that we can resume from S3 safely.
BUG=chrome-os-partner:46049
BRANCH=none
TEST=tested on glados and samus
Change-Id: I5fa91046437479bcae69a8fca4c989b0ef554bbf
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/315222
Commit-Ready: Aaron Durbin <adurbin@chromium.org>
Tested-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
There are hooks for chipset power sequencing but not one to indicate
that the system has reset at runtime. Add a hook for this and
implement for lm4 and mec1322. The hook is notified on any platform
reset, including those that happen on the way into S3/S5 state.
There is a new config variable added because the hook is notified in
the interrupt handler and needs a deferrable function that needs to
be added to every board.
BUG=chrome-os-partner:46049
BRANCH=none
TEST=tested on glados and samus
Change-Id: I3be639414e18586344e0ec84632a50dfc1df586b
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/315221
Commit-Ready: Aaron Durbin <adurbin@chromium.org>
Tested-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
Configuring all GPIOs to INPUT / PULL_UP in hibernate is not a good
idea:
- INPUT / PULL_UP is not necessarially the lowest-power state (for
example, if there is an onboard pull-down).
- Most GPIOs should already be in lowest-power state when we're in S5.
- For the few GPIOs that need to be in a different state for hibernate,
we can use a board-level callback.
In addition, remove mec1322 code related to restoring from hibernate
state, since we always reset coming out of hibernate.
BUG=chrome-os-partner:49608
BRANCH=glados, strago
TEST=`hibernate` on chell console when in S5 and AC removed. Verify that
EC power is roughly equivalent to low-power idle power. Attach Zinger,
verify that device wakes and boots, and charges from charger.
Change-Id: Ib00ef035bec32cea3847eb38d743f5c0cec896ca
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/322937
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Todd Broch <tbroch@chromium.org>
the third_party tpm library, part 2.
This is a continuation of commit 5496242945 ("Move platform
independent stub calls back to the third_party tpm library.")
and moves _cpri__EccGetCurveCount() over to third_party/tpm2.
TEST=compilation succeeds
BRANCH=none
BUG=chrome-os-partner:43025,chrome-os-partner:47524
CQ-DEPEND=CL:323416
Signed-off-by: nagendra modadugu <ngm@google.com>
Change-Id: I03fa2125060cdef013e403e37414e4a559f29617
Reviewed-on: https://chromium-review.googlesource.com/323352
Commit-Ready: Nagendra Modadugu <ngm@google.com>
Tested-by: Nagendra Modadugu <ngm@google.com>
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
If we are doing a cold reset or if Deep S5 is disabled we will go into S5
and need to be able to power up again, but we do not have enough information
to know what direction the sequencing may go from S5 (to G3 or up to S0).
So limit the RTCRST check to just the explicit G3->S5 path and let the normal
checking of SLP_S4 signal happen otherwise.
BUG=chrome-os-partner:49564
BRANCH=glados
TEST=pass FAFT testing finally
Change-Id: I202234e58281e6b007ad2b98396994222d0831b2
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/323087
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Since battery pin 5 is the voltage across internal 10Kohm
thermistor and is not either 0V or 3.3V, typically 330mV
with external 100Kohm.
Using GPIO configuration to detect this pin causes extra
power consumption and this pin is reconfigured as ADC.
BUG=cros-bug-49610
BRANCH=glados
TEST=check if battery is detected. Use 'adc' console command
and check if it shows 'BATTPRES' with volatage in mV.
Change-Id: I907b94629b0581a6a27e6f0cecda12ddef09a4f0
Signed-off-by: Kyoung Kim <kyoung.il.kim@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/322771
Commit-Ready: Kyoung Il Kim <kyoung.il.kim@intel.com>
Tested-by: Kyoung Il Kim <kyoung.il.kim@intel.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
The power state machine goes through POWER_S5 state both when
sequencing up and down, but we only should check for it to
time out on the way up. In order to know what direction it
is going add a variable to indicate the direction.
On samus where this was done before it did not go through
POWER_S5 on the way down, instead going directly to POWER_S5G3
so I did not run into this same issue.
BUG=chrome-os-partner:49564
BRANCH=glados
TEST=successfully power down without the EC thinking it is
timing out and trying to reset RTC.
Change-Id: I1f53f3a252bdc2ec8c656e30b3de7f98aaa661a0
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/322898
Reviewed-by: Shawn N <shawnn@chromium.org>
Each pair of protect bits locks 4K, so for parts with 64K flash, don't
bother checking STM32_OPTB_WRP23.
BUG=chrome-os-partner:49354
TEST=Run flashrom to protect PD MCU (see repro steps on linked crbug),
reboot and verify system boots into dev mode with all_at_boot and
all_now protect flags set on PD MCU.
BRANCH=glados
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: Ic375d97c30bfd68940350641c44d5535b0402a2f
Reviewed-on: https://chromium-review.googlesource.com/322823
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
To reduce the boot & resume time in EC, set the power button
debounce time to zero in PMIC PBCONFIG Register.
BRANCH=glados
BUG=None
TEST=Put the device in S3. Press the power button and observe
SLP_SUS_S3 is getting released 30ms earlier than the previous
configuration
Change-Id: I184fa056b9b6aed1bcccae9f38eaff3f3bb4e2bb
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/321341
Commit-Ready: Kevin K Wong <kevin.k.wong@intel.com>
Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Kevin K Wong <kevin.k.wong@intel.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
When the device is discharging, but has a battery percentage greater
than 97 show a solid green LED.
BUG=chrome-os-partner:48661
BRANCH=none
TEST=make BOARD=lucid
Change-Id: Ia5c0946fbc47e37a295db3419a0edf925aacf484
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/322738
Reviewed-by: Shawn N <shawnn@chromium.org>
Enable CONFIG_BOARD_HAS_RTC_RESET and add a board_rtc_reset() function
to assert RTCRST to the PCH that will be called if the board fails to
sequence out of the S5 state.
This does not do anything on EVT devices but will be present in DVT.
BUG=chrome-os-partner:49564
BRANCH=glados
TEST=manually tested on chell
Change-Id: If0be091349a7ef7e8e1335ade029570c5f97a30e
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/322725
Reviewed-by: Shawn N <shawnn@chromium.org>
In order to pulse RTC reset to the PCH when power sequencing exit fails we
need to watch for SLP_S4 to deassert and if it does not then assert RTCRST
using a board specific method. This is attempted up to 5 times before giving
up and staying in G3.
On skylake the RSMRST passthru needs to be honored when the task is woken up,
so while waiting call handle_rsmrst() if woken up early. This is needed
because it is RSMRST that actually tells the PCH to try and wake.
This is all wrapped in a config option and board specific method because not all
boards have a GPIO to control RTCRST and if they do they may not all use the
same method to assert it.
BUG=chrome-os-partner:49564
BRANCH=glados
TEST=manually tested on chell EVT:
First, ensure board sequences properly if everything is OK for a normal boot.
Next, modify handle_rsmrst() to not pass through the signal in order to
simulate being stuck in S5, and ensure that the EC attempts to assert RTCRST
and power up again 5 times before giving up and staying in G3.
Change-Id: Ia3c13069c92762b51beb682a19e5a074194a3c26
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/322724
Reviewed-by: Shawn N <shawnn@chromium.org>
We found the deviation of 115200 UART baud-rate is too large when core
clock is 16 or 12MHz. It causes failure during FAFT since sometime EC
could not receive correct commands to proceed test. We adjusted core
clock from 16/12 to 15/13 to reduce the deviation of 115200. Both of
them have run FAFT and stress tests for weeks and no UART issues were
found.
Since the lowest source clock of i2c is 6.5MHz, we modified tSCLL, tSCLH
and hold time directly for better i2c timing when freq is 400K. And if
freq is 100K, we introduced normal mode to handle it.
Modified sources:
1. clock.c: Adjust core clock from 16/12 MHz to 15/13 MHz.
2. clock_chip.h: Set target core clock as 15 MHz.
3. uart.c: Add baud-rate support for 15/13 MHz.
4. register.h: Add new register definitions of SMBus.
5. i2c.c: Modified tSCLL, tSCLH and hold time directly for better i2c
timing.
BUG=chrome-os-partner:34346
TEST=make buildall -j; test nuvoton IC specific drivers
BRANCH=none
Change-Id: Ie5d22e87875c064b49338046c99a178f8fadf32b
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/322320
Reviewed-by: Shawn N <shawnn@chromium.org>
If we're asked to compute a hash of an image on a region of storage, we
may find that the region actually contains no image. In that case, we
need to compute a hash of zero bytes. Properly handle this case from
image size detection to hash computation to hash invalidation.
BUG=chrome-os-partner:49529
TEST=Manual on chell. `dd conv=notrunc if=/dev/zero of=ec.bin bs=131072
count=1`, then write ec.bin and verify SW sync occurs, RW hash is
computed correctly, and the system boots into dev mode.
BRANCH=glados, strago
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: Ie5a023d13d2521f9c224615666950aea8fbc22bb
Reviewed-on: https://chromium-review.googlesource.com/322750
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Previously there were only two uses of gpio_config_pins, one was
gpio_config_module, which passed in GPIO_CONFIG_ALL_PORTS (the only
place this is used), the other was the common I2C code when it needs to
return the SDA and SCL lines to their alternate function after unwedging
the bus.
These uses are so different that it doesn't make much sense to keep a
single API for them. This change adds a gpio_config_pin that is
simpler to use as it just takes a gpio_signal enum to select the GPIO
to configure and makes gpio_config_pins and GPIO_CONFIG_ALL_PORTS
internal to gpio.c
Signed-off-by: Anton Staaf <robotboy@chromium.org>
BRANCH=None
BUG=None
TEST=make buildall -j
Change-Id: I92bfb0b520b0aa2165655b2ff5076e428c88631f
Reviewed-on: https://chromium-review.googlesource.com/322437
Commit-Ready: Anton Staaf <robotboy@chromium.org>
Tested-by: Anton Staaf <robotboy@chromium.org>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
