In order to help correlate EC logs with those from the kernel, it was
suggested that the EC could periodically print the RTC time. This
commit prints out the RTC time when changing power states.
BUG=chrome-os-partner:57731
BRANCH=gru
TEST=Build and flash kevin. Boot system up and suspend. Verify that
RTC times are logged to the EC console.
Change-Id: Ia1ee1ec88c6733f863a703fb3f841ab74b80fcb9
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/388802
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
In order to help correlate EC logs with those from the kernel, it was
suggested that the EC could periodically print the RTC time. This
commit prints out the RTC time when a chipset reset is requested.
BUG=chrome-os-partner:57731
BRANCH=gru
TEST=Build and flash kevin. Trigger watchdog from kernel and verify
that RTC time is printed when the chipset is reset.
Change-Id: Idc9a815c3337f720d41d16e0d844b4c1ea6728d8
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/388857
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
This commit adds a function that allows the real-time clock to be
printed on the EC console. This could be helpful in trying to correlate
events between the EC's log and the kernel's.
BUG=chrome-os-partner:57731
BRANCH=gru
TEST=make -j buildall
Change-Id: I5e20692a173bddea3dc5c20cc0f2061cc170ce7d
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/388856
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
Added i2ctest console command to test the reliability of the I2C.
By reading/writing to the known registers this tests provides the
number of successful read and writes.
BUG=chrome-os-partner:57487
TEST=Enabled the i2ctest config on Reef and tested the
i2c read/writes.
BRANCH=none
Change-Id: I9e27ff96f2b85422933bc590d112a083990e2dfb
Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/290427
Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
The AP UART is used to detect if the device is in s0. When it is cr50
should not be in deep sleep for any reason. This change makes DIOA5 a
wake pin before entering deep sleep.
BUG=chrome-os-partner:56100
BRANCH=none
TEST=make buildall
Change-Id: Icb57824c0ca1421f5f508fce7cf5609010b91e32
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/388793
Reviewed-by: Scott Collyer <scollyer@chromium.org>
Added unlocked versions of register access,
modified RMW functions to use unlocked versions
and made them locked themselves.
BRANCH=master
BUG=chrome-os-partner:49182
TEST=DUT boots successfully
Change-Id: Ifd16abc349cc731aeed78b12989595214e65cea2
Signed-off-by: Victor Prupis <vprupis@google.com>
Reviewed-on: https://chromium-review.googlesource.com/377151
Commit-Ready: Shawn N <shawnn@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
This change sets UART_FIFO_RXILVL to 3 for the AP and EC UART. With this
change RXINT will only be triggered when 4 characters are received
instead of for every character.
The change also flushes the RX FIFO whenever console input is received
through usb make sure to the user can see their input as they are typing.
BUG=none
BRANCH=none
TEST=run taskinfo after the system finishes booting.
Before Change the IRQ count for 181 should be around 20000.
After the change it should be around 5000.
Use the AP and EC console over USB and verify there is no
noticeable change in their usability.
Change-Id: I134ea0d2bc254038dad6c341b94f822adb90c000
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/387175
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
BUG=chrome-os-partner:54332
BRANCH=none
TEST=verify only zinger is detected in sink mode (G3/S5), and both
zinger and hoho is detected in dual role mode (S0).
Change-Id: Ifce0009908acc4b1849723ce807ca1b4c8e26020
Signed-off-by: Kevin K Wong <kevin.k.wong@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/387260
Reviewed-by: Shawn N <shawnn@chromium.org>
Previously, there was no way to identify which flash chip was used by
the EC, for ECs using an external SPI flash. Now, 'ectool flashinfo'
will print more information about the SPI flash chip in these cases.
BUG=chrome-os-partner:56765
BRANCH=any EC with MEC1322 or NPCX still going through factory
TEST=define CONFIG_HOSTCMD_FLASH_SPI_INFO, then
'ectool flashspiinfo' on samus indicates no SPI flash info,
and prints additional info on chell and kevin. Without
the config defined, all platforms report no spi flash info.
CQ-DEPEND=CL:386368
Change-Id: I3c162f7ad12ed4b30ab951c03f24476683382114
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/385702
Reviewed-by: Shawn N <shawnn@chromium.org>
For TPM operation with Intel chipset APs, the signal PLT_RST_L needs
to trigger a TPM reset. For current Reef boards, this signal is
connected to DIOA13. The next version will have it on DIOM3.
This CL adds support for platform reset connected on DIOA13 and uses a
new board property so that it doesn't affect Kevin/Gru.
BRANCH=none
BUG=chrome-os-partner:55115
TEST=manual
Used H1 dev board configured as Reef. Created high to low transisition
on to verify that platform reset was detected. Tested on Kevin to
ensure that resets were not occurring.
Change-Id: I58f02b7ffa644a9197f4303ae6e640df181040bd
Signed-off-by: Scott <scollyer@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/380336
Commit-Ready: Scott Collyer <scollyer@chromium.org>
Tested-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
The reset line to the charger IC isn't hooked up to the cold_reset
circuitry. This commit makes the EC reset the charger at init time.
BUG=chrome-os-partner:57524
BRANCH=gru
TEST=Enable power save mode. Toggle cold reset. Verify that power save
mode is still enabled. Flash kevin with this patch. Verify that power
save mode is disabled.
TEST=Enable power save mode, reboot, verify power save mode is disabled.
TEST=Enter G3. Enter hibernate. Insert zinger and verify that EC wakes
up. Repeat 20 times.
TEST=Verify system powers successfully with no battery, and wakes
successfully from battery cut-off.
Change-Id: Ib1362aefc71056e7c2b212a4fbdd6f979c57e20f
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/384320
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
Before performing a sysjump, ensure that:
1. LPC interrupts are disabled : Ensures interrupts are not taken until
next enable.
2. LPC window is closed by writing 0xfffffff8 to window base addresses:
Prevents any memory corruption by host.
BUG=chrome-os-partner:57642
BRANCH=None
TEST=Verfied that LPC communication works after sysjump to RW.
Change-Id: I7b7826b2544f1c94cfa9c96b6ac82bc3517b1820
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/388755
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Mulin Chao <mlchao@nuvoton.com>
1. interrupt enabling should be the last thing done when lpc_init
completes required intialization
2. memset to 0 of static uninitialized variables is not required. Remove
that.
BUG=chrome-os-partner:57642
BRANCH=None
TEST=Verified that LPC communication is fine after sysjump to RW.
Change-Id: Ib8891dccf2b301590ebca41b75680d954d88a4d3
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/388752
Tested-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Mulin Chao <mlchao@nuvoton.com>
Don't require GPIO_USB2_ENABLE to be defined if we have only one port.
BUG=None
TEST=Redefine CONFIG_USB_PORT_POWER_SMART_PORT_COUNT to 1 for reef,
remove GPIO_USB2_ENABLE definition, verify build is successful.
BRANCH=None
Change-Id: I5bfbee48ceabd87bbbd45cb120fda320d5eb1897
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/387926
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Cr50 monitors UART1 RX to sense the state of the AP. This signal can be
used to tell if it is in S0. If the signal is pulled up then the AP is
on. If it is not pulled up then the AP is not in S0. This change
notifies HOOK_CHIPSET_SUSPEND when UART1 RX is not pulled up, and then
notifies HOOK_CHIPSET_RESUME when the signal is high again.
The AP usb can be disabled during suspend, so this change changes the
hook that triggers disabling the AP usb to be attached to
HOOK_CHIPSET_SUSPEND instead of HOOK_CHIPSET_RESUME.
BUG=chrome-os-partner:55747
BRANCH=none
TEST=buildall
Change-Id: I47fb38a4bbcd72424ec2535d61e87f820cf1bcd7
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/383978
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
Except the CHIP_ID and charger name code is common between BD99955
and BD99956. Hence renamed the code to BD9995X so that valid
output is printed from console commands.
BUG=chrome-os-partner:57519
BRANCH=none
TEST=Manually tested on Reef. 'charger' console command prints
charger name as 'bd99956'
Change-Id: I3c995757941bcc5a6a8026dd807d76a7a47c9911
Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/387119
Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
If charge_manager has not decided on a current limit, don't set a
minimum current limit, since we may brown-out in the no / low-battery
case.
BUG=chrome-os-partner:56139
BRANCH=None
TEST=Manual on kevin, attach cut-off battery, attach OEM charger, verify
system doesn't brown-out due to OC.
Change-Id: Id53eb32c4a8ac9c6d9a0d3f1d700f089a50fcb0f
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/386793
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
The typical power consumption in sleep mode is 65uA.
IT83xx uses deep doze mode for low power idle task. The typical power
consumption in this state is 280uA (depends on EC tasks, it should be more)
and the wake up time is in microsecond. We are using deep doze mode for
low power idle task instead of sleep mode is because the wake up time
will be 6ms more.
While in system hibernate (EC sleep mode), EC won't wake up frequently so
we can keep the power consumption at 65uA.
Signed-off-by: Dino Li <dino.li@ite.com.tw>
BRANCH=none
BUG=none
TEST=- hibernate 0 [1|999999]
- hibernate [1|5|10|600]
- hibernate then press power button.
- hibernate then lid open.
Change-Id: I94884c010264f01ede4950c6bb1b0a444d7b1e6d
Reviewed-on: https://chromium-review.googlesource.com/383332
Commit-Ready: Dino Li <dino0303@gmail.com>
Tested-by: Dino Li <dino0303@gmail.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
We no longer depend on this directory, so there's no need to
include its sha1sum in the version string.
BUG=chrome-os-partner:54101
BRANCH=none
TEST=make buildall; try on Cr50 hardware
Before
> version
Chip: g cr50 B2
Board: 0
RO_A: * 0.0.9/0088a3eb
RO_B: 0.0.3/8fe06b9e
RW_A: * 0.0.6/DEV/cr50_v1.1.5333-cca986c
RW_B: 0.0.6/DEV/cr50_v1.1.5334-115b338
Build: 0.0.6/DEV/cr50_v1.1.5333-cca986c
private-cr51:v0.0.87-24457f2
tpm2:v0.0.264-5e5aaa3
cryptoc:v0.0.4-5319e83
2016-09-16 21:59:31 wfrichar@wintermute.mt
>
After
> version
Chip: g cr50 B2
Board: 0
RO_A: * 0.0.9/0088a3eb
RO_B: 0.0.3/8fe06b9e
RW_A: 0.0.6/DEV/cr50_v1.1.5333-cca986c
RW_B: * 0.0.6/DEV/cr50_v1.1.5334-36b2cee
Build: 0.0.6/DEV/cr50_v1.1.5334-36b2cee
tpm2:v0.0.264-5e5aaa3
cryptoc:v0.0.4-5319e83
2016-09-19 17:48:17 wfrichar@wintermute.mtv.corp.google.com
>
Change-Id: I785dff86e6b970219da87c8674f2a324fa074987
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/387238
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
The interrupts on all of the gpios detecting if the device is on were
edge triggered. If the rising edge happened in between when the gpio
level was read and when the interrupt was enabled, then the device state
could be falsely detected as off for a short period of time. This change
changes them to GPIO_INT_HIGH.
BUG=none
BRANCH=none
TEST=buildall
Change-Id: I9aa3cff14047cf4f6473c32f2cdc4724afca3414
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/385164
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
The interrupts to detect when the falling edge on the UART signals are
currently disabled and never reenabled. Power off is detected by polling
and not through interrupts. This change removes all of those falling
edge interrupts.
BUG=none
BRANCH=none
TEST=cr50 can detect when the EC, AP, and Servo are off or on
Change-Id: I0fd8a0d970f3235b26af6b90dd395ea7c75e0c17
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/385192
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
We should clear STASTR to release SCL only after NACK/STOP bits are set.
If an interrupt which priority is higher than i2c's issues at this moment,
i2c hardware might not generate NACK since SCL is already released by
clearing stall's pending bit.
Modified sources:
1. i2c.c: Fixed bug i2c sometime cannot generate NACK during Read Byte.
BRANCH=none
BUG=chrome-os-partner:34346,chrome-os-partner:57452
TEST=make buildall; passed "while(1); do; ectool i2cread 8 0 0x50 0x44;
done;" on reef.
Change-Id: I68ee5bf3d703cbe4fceefcfcc9afab9cb14bc2dc
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/386586
Commit-Ready: Kevin K Wong <kevin.k.wong@intel.com>
Tested-by: Kevin K Wong <kevin.k.wong@intel.com>
Reviewed-by: Kevin K Wong <kevin.k.wong@intel.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
Removed power LED support.
In case of discharging, if below critical level, LED should blink;
otherwise, will show power state;
In case of charging, will show charging/battery state.
BUG=chrome-os-partner:56932,chrome-os-partner:57025
BRANCH=none
TEST=Verified on EVT with <10% and <3% battery, LED is blinking
amber at proper duty cycle.
Also verified ectool led command works as expected.
Change-Id: I903396a9a1dc5e08618683f7124b09678678e233
Signed-off-by: li feng <li1.feng@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/383880
Commit-Ready: Li1 Feng <li1.feng@intel.com>
Tested-by: Li1 Feng <li1.feng@intel.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
- Use 1200KHz DCDC clock.
- Set reverse current threshold to -50mV.
- Set internal gain to 2x.
BUG=chrome-os-partner:57118,chrome-os-partner:56255
TEST=Manual on kevin and reef, verify charging w/ zinger.
BRANCH=None
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: Ib7188764206743543fb873f303acb7b62977dc3d
Reviewed-on: https://chromium-review.googlesource.com/382451
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Enable the SHI interrupt only after we have received and begun
processing our host command. Disable the SHI interrupt once our
transaction is complete (with either success or error status). This will
prevent the SHI interrupt from being asserted at the same time as the CS
interrupt, which can lead to the SHI interrupt being serviced first.
Also, it avoids needless, non-useful SHI interrupts during error
transactions.
BUG=chrome-os-partner:55710,chrome-os-partner:55795,chrome-os-partner:56254
BRANCH=None
TEST=Manual on gru. Stress test flashrom w/ unpowered Donette attached
(for host command spam), verify no errors encountered after 100 minutes.
Also verify host command interface functions properly after sysjump.
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/384583
Reviewed-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
(cherry picked from commit 668763721aab31a102ead348d7cfe1c72f50cb71)
Change-Id: I7292d1b34d3e1c71628a8b5d663ce9fd865493f4
Reviewed-on: https://chromium-review.googlesource.com/386447
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
Some chargers with valid VBUS advertise as Pull-up ports. Hence,
added code to support these kind of chargers as non-standard
BC1.2 chargers.
BUG=chrome-os-partner:57163
BRANCH=none
TEST=Manually tested on reef. Used a Pull-up port non-standard
BC1.2 charger and observed it can ramp to its maximum
current ratings.
Change-Id: I33c4c3a64e9c7176c909a48f6fbc49e04d529541
Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/385239
Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Tested-by: Rachel Nancollas <rachelsn@google.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
When cr50 connects to the AP usb it should only initialize the usb when
it knows that the AP is on. If usb is incorrectly initialized it can
prevent cr50 from going to sleep. In this change the AP usb will be
initialized when suzyq is disconnected or on HOOK_CHIPSET_RESUME and it
will be released on HOOK_CHIPSET_SHUTDOWN.
BUG=chrome-os-partner:55747
BRANCH=none
TEST=manual
On reef run apreset and verify the AP can communicate with cr50
over usb after it boots up.
Run poweroff and verify cr50 has released the usb.
power the AP back on and check that it can communicate with cr50
again
Change-Id: Id35010525e2354ee140d3b7220fb5ea434a0993f
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/383979
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
On CHIPSET_SHUTDOWN set the idle_action to deep sleep. If sleep is
enabled it will go into deep sleep. If not it will wait until sleep is
sleep is enabled.
This change also sets the idle_action to IDLE_DEFAULT when resuming from
deep sleep or during init. Before cr50 kept track of the previous idle
state in a PWRDN register and then used that state during the next
resume. If we went into deep sleep, on resume we want the idle action to
be reset to sleep and then only enter deep sleep if we have detected the
AP is off.
BUG=chrome-os-partner:56100
BUG=chrome-os-partner:55747
BRANCH=none
TEST=manual
run 'poweroff' on the AP and see that cr50 enables deep sleep
verify that even if the ap is powered off it doesn't prevent ccd
from working and when suzyq is unplugged cr50 will go into deep
sleep
After running poweroff on the AP wait a while and run powerbtn
on the EC. Verify the system can boot up fully without going
into recovery.
Do this on gru and reef.
Change-Id: I07f5a9d85dd0467cd22e499d4261c75caf653563
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/373139
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
When generating the RSA endorsement primary key, use the
CR50 vendor specific template. Doing so generates the
RSA key corresponding to the certificate issued at manufacture.
Also, always start the RSA key generation counter at 1. Doing
so matches the certificate generation process at manufacture;
and there is no harm in always starting at 1, since the key
generation process remains deterministic.
BUG=none
BRANCH=none
TESTED=generated key matches endorsement cert;
checked via attestation_client
Change-Id: I6a5c329e99292e32f880c0c5ea364d511cb6ea82
Signed-off-by: nagendra modadugu <ngm@google.com>
Reviewed-on: https://chromium-review.googlesource.com/386279
Commit-Ready: Nagendra Modadugu <ngm@google.com>
Tested-by: Nagendra Modadugu <ngm@google.com>
Tested-by: Andrey Pronin <apronin@chromium.org>
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
We found the api utility in ROM doesn't enable burst mode of GDMA. It
influences the performance of FW download a lot. The CL modified GDMA
for moving the code of the other region from flash to ram. And move a
function that kicks off GMDA transactions to suspend ram in case this
utility is erased by itself. This issue will be fixed in our next
generation.
Modified sources:
1. system.c: Implement GDMA bypass.
2. system_chip.h: Import flash addresses for GDMA bypass code.
3. registers.h: Add GDMA register definitions.
4. cortex-m/ec.lds.S: Add lowpower_ram2 section in linker script.
BRANCH=none
BUG=chrome-os-partner:56794
TEST=make BOARD=npcx_evb; test sysjump and measure download time
Change-Id: I8490f8f2e5a8cdcb6fd10511878c4a4af8073bbf
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/381779
Commit-Ready: Shawn N <shawnn@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The argument is mHz not ms.
BUG=chrome-os-partner:57117,b:27849483
BRANCH=reef
TEST=Using frequency sysfs parameter check the returned value is close
to the requested value. It will be greater than the requested frequency.
It maxes out at 76Hz when frequency is greater than 13.5Hz.
Check Androsensor reports pressure.
Change-Id: Ie40ac0f0a83d1578b5b66097d85a9124ec8e4c54
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/385083
Reviewed-by: Divya S Sasidharan <divya.s.sasidharan@intel.com>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
- Enable MKBP events:
Allow EC to send sensor event to the kernel sensor stack.
- Disable APCI message display, to avoid overwhelming the console.
- Set the rotation matrices to match Android requirement.
BUG=b:27849483
CQ-DEPEND=CL:384341
BRANCH=reef
TEST=Check we can receive sensor events for ARC++.
Check the acceleromter axis are correct.
Change-Id: I5fa58e22167f027bd1b84e72f002060d15d882c4
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/385082
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
The g i2c slave controller does not support clock stretching, so it is
necessary to flow control the AP by some other means. Luckily there is
an interrupt line which g can toggle and the AP can watch.
This patch adds generating a pulse on the AP interrupt line once g
finished processing the i2c transaction. In case of the read
transaction the pulse is generated after the data to read is put in
the i2cs transmit buffer.
BRANCH=none
BUG=chrome-os-partner:57338
TEST=with this patch and the AP firmware synchronizing on the
interrupt pulse, the TPM initialization succeeds in coreboot and
depthcharge.
Change-Id: I16c09b59b7d772624baa9d1f5258aaff26f91ff9
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/385256
Reviewed-by: Scott Collyer <scollyer@chromium.org>
