Cortex-m0 we supports 2 bit priorities for the NVIC, yet we clear with 0x7 (3
bits). Change so we now clear with 0x3
Also limited priority to the max available (so we don't set extra bits we don't
want or modulus the priority, otherwise setting priority 8 will actual give you
priority 0) in both cortex-m and cortex-m0.
BUG=None, discovered while looking at the code
TEST=Should be no functional change, NVIC priorities should still work the same.
BRANCH=None
Change-Id: I31ba041449cae96983753b297e2631c310a406c4
Signed-off-by: Alexandru M Stan <amstan@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/236086
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Add a rate limiter to host commands so that a host that is continuously
sending host commands doesn't watchdog the EC.
BUG=chrome-os-partner:33905
BRANCH=samus
TEST=loaded onto samus and tested remote update of zinger 10 times.
also tested EC + PD software sync.
Change-Id: Ia024179c46b2180ee97ea1902de343306142311c
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/235530
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
In order to reduce flash size on some constrained boards this CL
modifies the GPIO macro in gpio_list.h to change the name field from
that listed 'name' to the concat of 'port' and 'pin'.
Signed-off-by: Todd Broch <tbroch@chromium.org>
BRANCH=samus
BUG=chrome-os-partner:34489
TEST=manual
1. build with and without CONFIG_COMMON_GPIO_SHORTNAMES
See 897 bytes savings with config option
2. See reduced names for gpioget
> gpioget
0 E6
0 F2
1 B0
Change-Id: Ife1e1e2bcfa620ba87fe6c1ce2b47fe258c46514
Reviewed-on: https://chromium-review.googlesource.com/234587
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Commit-Queue: Todd Broch <tbroch@chromium.org>
Tested-by: Todd Broch <tbroch@chromium.org>
Change backboosting workaround into a new extpower task. This
new task runs exactly what used to be run in a deferred function,
but at higher priority than charger task, which means that i2c
transactions from this new task will occur before charger task
i2c transactions.
This fixes the EC watchdog when writing PD device firmware
because the hooks task is no longer blocked on trying to grab
the i2c mutex for talking to BQ.
BUG=chrome-os-partner:33905
BRANCH=samus
TEST=loaded onto samus and tested remote update of zinger 10 times.
Change-Id: I01d259857aefc6bf456ab217bf46536237bc4008
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/235862
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
.config is a file in build/$BOARD that contains all defined config
variables. It is used by external programs to know what features
have been compiled for a specific board.
BUG=chrome-os-partner:33908
TEST=Check .config is generated properly. Check content, check
it updates when new .bin are created.
BRANCH=none
Change-Id: If93c2a393867a9fcb60841e282d8e6b933f3dfec
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/233888
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Ryu sensor hub has asymectric RO/RW images. The first one is very limited
(not i2c master, no sensor drivers, gesture recognition).
Image size is alter to offer more space for the RW firmware image,
compiled with ryu_sh board.
To write RO image and basic RW image:
flashrom -V -p ec:type=sh,block=0x800 --fast-verify -w /tmp/ryu_sh_loader/ec.bin
To write the expected RW image:
flashrom -V -p ec:type=sh,block=0x800 --fast-verify -w -i EC_RW:/tmp/ryu_sh/ec.bin
BRANCH=ToT
BUG=chrome-os-partner:33908
CQ-DEPEND=CL:231970,CL:233233
TEST=load on Ryu, confirmed limited operation.
Change-Id: Ib976e2b048935adfb9b2b072c071db5be2bc1c09
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/231984
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Add high (and low) battery temperature warning which sends host
event to AP. After 30 seconds of out of range temp readings force
shut off AP and hibernate the EC.
BUG=chrome-os-partner:27641, chrome-os-partner:33111
BRANCH=samus
TEST=make buildall, and write unit tests to test this condition.
Change-Id: I95b7d9d753c17e4b76218a9845aa63dd1b96a500
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/235645
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
On samus it is possible to have AC plugged in but have the battery
discharging. So, add a new variable to charge state machine for
battery charging status and use that where necessary. For example,
the low battery shutdown code should now be based on whether or
not battery is charging rather than if AC is present.
This also changes the hibernate behavior when battery is low. The
change is to wait 30 seconds in G3 of low battery with no charging
before hibernating because for some chargers, like a USB PD charger,
the charger may increase it's current limit after a little bit of
time.
BUG=chrome-os-partner:34485
BRANCH=samus
TEST=test on samus. use low power charger and make sure that
ectool battery shows the "DISCHARGING" flag. use zinger and see
"CHARGING" flag. also use power_supply_info to make sure that
the battery state accurately reflects reality.
Change-Id: I8ac0267dd393071c4ca1fa24fbc9a13bf27848a9
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/235491
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
burn_my_ec is an utility that flash an image embedded in its code.
We can not compile it as part of ec-[dev]utils, because we have
devices that firmware should be build as part of chrome-ec package.
Remove burn_my_ec, barely used.
Split the makefile to build just the host utility when requested.
BRANCH=ToT
BUG=chrome-os-partner:32025,chromium:408713
TEST=Check that files are stil built when needed and
not when utils-host is invoked.
Change-Id: I3fabe16067d57c74ae36b05138f4c6fd2483c7c4
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/233347
Fix bug where if we have a non-PD aware charger, we constantly send
host events to notify EC of an input current limit change. This was
unintentionally broken when adding code to constantly monitor the
CC line pull-up strength and adjust the current limit accordingly.
BUG=none
BRANCH=samus
TEST=plug in a non-PD aware charger and make sure it sets the correct
input current limit and that it is not constantly sending host events
that the limit has changed.
Change-Id: I7d835769ebc768043a9a46f50721987dce0384f5
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/235414
Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
For the transmitter to clear CHARGE_DONE, charging must be enabled.
Therefore, we should always enable charging when the lid is just closed.
BRANCH=ryu
BUG=None
TEST=Test on Ryu p1.
Signed-off-by: Vic Yang <victoryang@chromium.org>
Change-Id: I44f3d7c9e413a63be66ccf9695fea5411b2067b6
Reviewed-on: https://chromium-review.googlesource.com/231121
Reviewed-by: Randall Spangler <rspangler@chromium.org>
After receiving more info from the manufacturer, it appears that
since we're using closed-loop feedback to drive the fan we can
turn it at whatever speed seems to work.
While we're bikeshedding over the startup noise, let's put the
start/min speed back to 1000RPM to help distinguish the startup
chirp from the fan-is-running-now noise.
BUG=chrome-os-partner:32757
BRANCH=ToT,Samus
TEST=make buildall -j
Watch fan speeds while doing things. It still makes noise, but it's
quieter.
Change-Id: I5c21bf9021e4110f31c6dded78852347c4eb6119
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/234755
Reviewed-by: Sameer Nanda <snanda@chromium.org>
Reviewed-by: Eric Caruso <ejcaruso@chromium.org>
If a PD charger is attached and immediately becomes our charge port, we
will request PD_REQUEST_MAX twice. Remove this needless re-request by
storing the previous request, and only re-requesting from
PD_STATE_SNK_READY if the request has changed.
BUG=chrome-os-partner:34168
TEST=Manual on Samus. Plug Zinger as lone charger, verify that 20V @ 3A
is requested only once. Plug second Zinger in second port, verify that
5V @ 3A is correctly requested.
BRANCH=samus.
Change-Id: Ife6fa9788e97a045edbca5d83933af57cd0ea91d
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/234701
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Remove common code across all PD policy layers to select the requested
voltage and build a Request Data Object (RDO).
BUG=none
BRANCH=samus
TEST=Load onto samus and connect zinger. Make sure we request the right
voltage (first 5V, then after initial contract is made, 20V). Make
sure input current limit is set appropriately by checking limit on EC
console using charger command.
Change-Id: Ic6bda5e23b2d7b7d710ffdf085e7fbc1b0c3add9
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/233673
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Commit-Queue: Shawn Nematbakhsh <shawnn@chromium.org>
Tested-by: Shawn Nematbakhsh <shawnn@chromium.org>
Turn on PP5000 when AC is plugged in in G3 so that the PD
MCU can accurately measure the CC voltage.
BUG=chrome-os-partner:33909
BRANCH=samus
TEST=test with various type-C chargers. verify that in G3 the
pp5000 rail is on when AC is plugged in, but off when AC is
unplugged
used reported battery current to estimate that turning on
PP5000 rail in G3 consumes an extra 30mW of power, but that
shouldn't matter much when AC is connected.
Change-Id: I3cdd2aaf3e7688d69a65e5d11e38e5b9cf16e703
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/233734
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
The new board will move AC_PRESENT to another pin in order to avoid the
[1.052524 Overriding AC_PRESENT with KB_IN00 on EXTI8] problem.
BUG=chrome-os-partner:34024
TEST=EC should react to AC events
BRANCH=None
Change-Id: I5c1110f10a3ed2704593c749cef35ab73fceb3e8
Signed-off-by: Alexandru M Stan <amstan@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/234586
Reviewed-by: Chris Zhong <zyw@rock-chips.com>
Reviewed-by: Jerry Parson <jwp@chromium.org>
This exposes the pd_exchange_status() function and lets it
return the charge port that the PD reports, so that the lightbar
TAP sequence can decide which direction to display.
BUG=chrome-os-partner:32227
BRANCH=ToT, samus
TEST=make buildall -j
Change-Id: I78b57fbeaaf38fee15c86eca4d90abce77e2f722
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/232092
Reviewed-by: Alec Berg <alecaberg@chromium.org>
The power sequence doesn't meet the spec from Intel.
We should delay about 10ms between VccSUS3_3 and RSMRST.
BUG=chrome-os-partner:34411
BRANCH=samus
TEST=build and boot on samus
Change-Id: Ib35e9dfdcfa4cfde2440f85fbeae6ee878465949
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/234404
Reviewed-by: Alec Berg <alecaberg@chromium.org>
If override charge is selected on a port currently acting as a charge
source, but the attached device is also capable of acting as a source,
request a charge role swap and initiate a pending delayed port override.
If the role swap completes successfully and a charge source is found,
the selected port will become the override port. If the role swap fails
or no charge source is found within 2 seconds, the delayed port override
will be lost.
BUG=chrome-os-partner:28343,chrome-os-partner:31195
TEST=Manual on Samus. Connect two Samus units together through charge
ports.
"pd 1 swap power" - put port on test device into source role
"chgoverride 1" - set charge override, verify that role swap takes
effect and charge manager selects PD charge source, 900mA @ 5V
Disconnect charge cable, verify that charge manager goes back to not
charging.
BRANCH=Samus
Change-Id: Iadcc4dc98631661f254245eeff18973df517f652
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/231900
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Samus USB ports can't actually act as UFPs, so open switches when in
UFP mode.
BUG=chrome-os-partner:32003
TEST=Manual on Samus. Connect two Samus units, run `pd 1 swap data`,
verify that switches are opened on switch to UFP. Unplug samus and
connect a USB 2.0 device instead, verify that ports are again closed.
BRANCH=samus
Change-Id: I9e1ca58089caf29e419698c8426bf8b72500833a
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/233711
Reviewed-by: Alec Berg <alecaberg@chromium.org>
The new hard reset recovery state was endlessly sending hard resets.
Added in hard reset counter to cap the number of hard resets for
a sink.
BUG=none
BRANCH=samus
TEST=test with non-PD type-C charger and verify that we only send
two hard resets and set the appropriate input current limit after
the hard resets.
Change-Id: I95a3739be28ad2a5fed245aad021bcd6d51d94b1
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/233754
Reviewed-by: Todd Broch <tbroch@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
When we receive source capabilities packet from a source, if we are already
the active charging port, then we know we can request max power, otherwise
request vSafe5V. Normally, when you first attach a charger, the port won't
already be the active charge port when we receive source cap. But, if we
already have a power contract with a source and the source sends us new
source capabilities, then this comes in to play.
BUG=chrome-os-partner:34168
BRANCH=samus
TEST=test with plankton. when you press the 5/12/20 V buttons on plankton
it changes the source capabilites of plankton and sends a new source cap
packet to samus. thus, without this change, when you press one of the buttons
twice, the second button press causes us to negotiate to vSafe5V instead
of the max power. with this change, the requested power stays constant
when plankton re-issues source capabilities.
Change-Id: I3cc1e6b109117566f59de07762fd1af9adec05bf
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/233753
Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Do not allow remote PD firmware update of a device that is providing
us power when we have no battery (or else we will lose power).
BUG=none
BRANCH=samus
TEST=attach a zinger that has an old FW to samus with no battery and
see that host attempts to update FW but PD MCU does not allow it.
Change-Id: Iaf816dc44017d9c65a2b248ea8536d7c03898910
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/233752
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
The task based approach made sense when it looked like
there would be a case closed debugging task to handle
multiple bridges (SPI/I2C/USART...). I'm not convinced
anymore that that task will be needed, so this
simplification seems good.
Signed-off-by: Anton Staaf <robotboy@chromium.org>
BRANCH=None
BUG=None
TEST=make buildall -j
Change-Id: Ic431c287c28d10252246fe9f507d9c5fcc64a077
Reviewed-on: https://chromium-review.googlesource.com/232733
Tested-by: Anton Staaf <robotboy@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Commit-Queue: Anton Staaf <robotboy@chromium.org>
This allows the USB SPI bridge to be controlled from the
host at a larger timescale than a single SPI transaction.
This allows the host to signal that many transactions
will take place and that the device should keep the SPI
bridge enabled across them. This allows the device to
hold the AP or other possible user of the SPI bus in
reset while the bridge is enabled.
Signed-off-by: Anton Staaf <robotboy@chromium.org>
BRANCH=None
BUG=None
TEST=make buildall -j
Change-Id: Ifd6f96b0ff47f35d853735d44e255a205b0e677a
Reviewed-on: https://chromium-review.googlesource.com/232732
Tested-by: Anton Staaf <robotboy@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Commit-Queue: Anton Staaf <robotboy@chromium.org>
Before sysjump we need to send a soft reset to any attached devices
and then disable PD communication so that we don't re-negotiate again
before the sysjump. This will guarantee expected message ID is cleared
for after the sysjump.
This also moves executing soft reset from before sending the soft reset
command to after the port partner accepts a soft reset.
BUG=none
BRANCH=samus
TEST=test on samus. without this change, when sysjumping the PD MCU
has time to re-negotiate (at least partially) before the sysjump, which
causes various problems. with this change, when sysjumping, the PD
MCU sends soft reset, and then does not send anything else.
Change-Id: Id7a60c62c8908ee4ab33dfbe995ef136b0aa83de
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/233751
Build the hardware version string from the register definitions,
so I no longer forget to update it.
Check it at runtime against the build version registers.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=none
BUG=none
TEST=On the console command line,
type "version" and see the following string:
"Chip: g cr50 A1 20141203_224409"
Change-Id: I6d902780d42f2dd18a57ccc08fd4ba4fee5ebc7c
Reviewed-on: https://chromium-review.googlesource.com/233582
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
Trybot-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
- record and display reset cause
- add the hard reset option
- add the scratchpad to store values across reboots.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=none
BUG=chrome-os-partner:33818
TEST=On the console command line, chech the "[Reset cause: xxx]" string
- for the initial reset cause
- use "waitms 4000" to trigger a watchdog reset
- use "reboot soft"
- use "reboot hard"
The "utils" test is now building and passing.
Change-Id: I68c7096e5b7bfd102be89fd8eef6fe20da37a6f8
Reviewed-on: https://chromium-review.googlesource.com/233581
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
Trybot-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Implement a driver to trigger a watchdog reboot if we are stuck
somewhere. Also display a nice warning when we reach half of the
watchdog period.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=none
BUG=none
TEST=On the console, type "waitms 500" and see nothing,
type "waitms 2000" and see the watchdog warning.
Type "waitms 4000" and see the warning, the platform rebooting.
Change-Id: Iac5d0100febd5eab1ae6cfac5a47ff728ebda3a6
Reviewed-on: https://chromium-review.googlesource.com/233430
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Trybot-Ready: Vincent Palatin <vpalatin@chromium.org>
We were losing timer events because usecs_to_ticks(deadline) was
clipping the value when deadline was larger than 0x08888888 (deadline is
a timestamp rather than a delay).
The computation of the timer deadline has been modified to avoid the
clipping issue.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=none
BUG=chrome-os-partner:34347
TEST=run on Cr50 with the watchdog activated and no longer see watchdog
warnings.
Run the "timer_calib" test and see that the 1s sleep is 1000038 us :
make BOARD=cr50 tests
fhl ../build/cr50/timer_calib/timer_calib.RO.hex
Change-Id: Id2200a89eb1b72099e536291af321609b24b4777
Reviewed-on: https://chromium-review.googlesource.com/233531
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
Trybot-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
CL to migrate the flashing VDMs from zinger's custom vdm to
common/usb_pd_flash.c such that other updateable type-C devices can
share.
Additionally adds gaskets to call standard runtime flashing facilities
for USB-PD devices using it.
Signed-off-by: Todd Broch <tbroch@chromium.org>
BRANCH=samus
BUG=chrome-os-partner:31192,chrome-os-partner:31193
TEST=manual,
Try following:
1. From samus_pd console w/ zinger in port 1
pd 1 flash version
pd 1 flash reboot
pd 1 flash info
2. From samus linux prompt w/ zinger in port 1
ectool --name cros_pd flashpd 1 1 <zinger RW payload>
Reading 16384 bytes from
/usr/local/zinger_v1.1.2528-d809e42.ec.RW.bin...
Erasing expected RW hash
Rebooting
Erasing RW flash
Writing RW flash
Rebooting PD into new RW
Complete
3. Repeat 1&2 above on hoho & dingdong.
Change-Id: I018055fa9de128f937c57debdc21dea026137bcf
Reviewed-on: https://chromium-review.googlesource.com/231835
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Tested-by: Todd Broch <tbroch@chromium.org>
Commit-Queue: Todd Broch <tbroch@chromium.org>
dingdong/hoho have no capability to measure VBUS which is advantageous
in determining what timeouts to honor. Previously we simply assumed
vbus was on and that made things happy until,
e0c80ac pd: on hard reset go to a hard reset recovery state
which introduced proper handling around sink & source reset recovery.
With VBUS assumed 'on' this leads to short timeouts chosen
(PD_T_SAFE_0V) which in turn causes sink to resend hard resets before
source has had time (PD_T_SRC_RECOVER) to handle request.
This change creates config CONFIG_USB_PD_NO_VBUS_DETECT for devices
without the capability to account for lack of VBUS detect.
Signed-off-by: Todd Broch <tbroch@chromium.org>
BRANCH=samus
BUG=chrome-os-partner:34090
TEST=manual
from samus_pd 'pd 1 flash reboot' is successful
Change-Id: I9ef9b0115c7be6c56c64556d2ce8c296f95c614e
Reviewed-on: https://chromium-review.googlesource.com/233024
Tested-by: Todd Broch <tbroch@chromium.org>
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Commit-Queue: Todd Broch <tbroch@chromium.org>
EAh is used at the end marker for calculating hash in EC.
The extra EAh make hash calculated by EC different from calculated in host
by sha256sum for the RW image. The RO image is fine.
Fix a comment, no A,B images anymore.
BUG=chromium:438326
TEST=Check sha256sum is similar for Ryu EC image.
On EC console
> hash rw
[28.740271 hash start 0x00010000 0x0000ea24]
> [28.938875 hash done e2c40d0168ce4b20e8320438c7fc719d2188d7f88d9cb7ca694527b3f507e534]
sha256sum of built image:
sha256sum build/ryu_p1/ec.RW.flat
e2c40d0168ce4b20e8320438c7fc719d2188d7f88d9cb7ca694527b3f507e534
build/ryu_p1/ec.RW.flat
TEST=Check firmware upgrade still works:
Using a modify version of coreboot with
- ryu_p1 as main ec firmware
- code to reenable SW sync: CL:233222
Ryu with an older image:
cros_ec_init: CrosEC protocol v3 supported (128, 128)
Google ChromeOS EC driver ready, id 'ryu_p1_v1.1.2570-942248a'
Clearing the recovery request.
VbEcSoftwareSync(devidx=0)
EC hash:e2c40d0168ce4b20e8320438c7fc719d2188d7f88d9cb7ca694527b3f507e534
EC-RW hash address, size are 0x835b4ff8, 32.
Hash = b183cd58d668d3d42a7cec95f2dcbb8ddee33f6a42d873f4b78106f85d341b46
Expected hash:b183cd58d668d3d42a7cec95f2dcbb8ddee33f6a42d873f4b78106f85d341b46
EC-RW firmware address, size are 0x837f9374, 59924.
VbEcSoftwareSync() - expected len = 59924
Computed hash of expected
image:b183cd58d668d3d42a7cec95f2dcbb8ddee33f6a42d873f4b78106f85d341b46
VbEcSoftwareSync() updating EC-RW...
VbEcSoftwareSync() jumping to EC-RW
VbEcSoftwareSync() jumped to EC-RW
VbEcSoftwareSync() in RW; done
Check that at next reboot the firmware is not upgraded:
cros_ec_init: CrosEC protocol v3 supported (128, 128)
Google ChromeOS EC driver ready, id 'ryu_p1_no_version'
Clearing the recovery request.
VbEcSoftwareSync(devidx=0)
EC hash:b183cd58d668d3d42a7cec95f2dcbb8ddee33f6a42d873f4b78106f85d341b46
EC-RW hash address, size are 0x835b4ff8, 32.
Hash = b183cd58d668d3d42a7cec95f2dcbb8ddee33f6a42d873f4b78106f85d341b46
Expected hash:b183cd58d668d3d42a7cec95f2dcbb8ddee33f6a42d873f4b78106f85d341b46
VbEcSoftwareSync() in EC-RW and it matches
BRANCH=ToT
Change-Id: I2db275a16b16fbcea95f53287e95104ba921593e
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/232952
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
Until we implement a proper reset of the microcontroller,
add a reset of the Cortex-M3 CPU core in system_reset() in order to
avoid getting stuck in a weird loop if we get a panic.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=none
BUG=none
TEST=trigger a data abort and verify we are not going into a panic loop.
Change-Id: Ie046379e6a9469bd683fa774cdc9abb10a14e8f1
Reviewed-on: https://chromium-review.googlesource.com/233109
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
