When we tried to go back to sleep immediately after receiving a
spurious USB resume event, the controller would get stuck in an
unrecoverable state. Hopefully we fixed the resume logic, but
this code would catch other cases, and recover the base.
BRANCH=none
BUG=b:35775088
BUG=b:67766202
BUG=b:71688150
TEST=With badly implemented resume logic (e.g. call
usb_resume_deferred directly from usb_resume), with USB
autosuspend enabled on soraka, short D+/D- lines.
Next wake event from staff shows "USB stuck", and then
USB interface recovers.
Signed-off-by: Nicolas Boichat <drinkcat@chromium.org>
Change-Id: I7463a37682723be195bd6a72ea5d76c21bb6cb9a
Reviewed-on: https://chromium-review.googlesource.com/868094
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Sometimes, usb_resume gets called, but the D+/D- lines do not
indicate an actual resume event (e.g. during ESD discharge).
Reference manual tells we should go back to sleep if state is 10 or
11. However, setting FSUSP and LP_MODE in this interrupt routine
seems to lock the USB controller (see b/35775088 and b/71688150).
Instead, we do it in a deferred routine. The host must assert the
reset condition for 20ms, so reading D+/D- after ~3ms should be safe
(there is no chance we end up sampling during a bus transaction).
BRANCH=none
BUG=b:35775088
BUG=b:67766202
BUG=b:71688150
TEST=On staff, with USB autosuspend enabled on soraka, short
D+/D- lines, which causes a spurious wake event. After that
remote wake-up still works.
TEST=Repeat test with ESD discharge.
TEST=Repeat test with plugging/unplugging of USB-C monitor.
Signed-off-by: Nicolas Boichat <drinkcat@chromium.org>
Change-Id: I0f2697d1fa5b68356fd8a4fc16eaab5eadad9086
Reviewed-on: https://chromium-review.googlesource.com/868093
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
In this CL, we add the following changes to support the CHIP_VARIANT
npcx7m6xb and npcx7m7w:
1. Define the code RAM, data RAM, BBRAM base address/size.
2. Initialize the wov.c file for WoV driver development. (It will be
compiled only when CHIP_VARIANT=npcx7m7w in the build.mk and
CONFIG_WAKE_ON_VOICE is defined in board.h)
3. Fix the the incorrect offset of PWDWN_CTRL7 register.
BRANCH=none
BUG=none
TEST=No build errors for make buildall.
TEST=Change CHIP_VARIANT to npcx7m7w/npcx7m6xb in
board/npcx7_evb/build.mk; "BOARD=npcx7_evb make"; Check ec image can be
built. Flash the image on EVB; make sure EVB bootup.
Change-Id: I87bccb9097f8f0a6c67f96a8d90adf201ae9e773
Signed-off-by: CHLin <CHLIN56@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/858637
Commit-Ready: CH Lin <chlin56@nuvoton.com>
Tested-by: CH Lin <chlin56@nuvoton.com>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
STM32_USB_CNTR may be written from both interrupt context, and
usb_wake (not necessarily in interrupt context). Let's disable
interrupts to make sure the operation is atomic.
BRANCH=none
BUG=b:35775088
BUG=b:67766202
BUG=b:71688150
TEST=Flash hammer, hammer can wake from USB autosuspend
Change-Id: I9c2a3259902ecb759a6d0d89c7746c7aa72ae73d
Signed-off-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/744282
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Update the host command support on the STM32 SPI slave for the STM32H7
silicon.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=none
BUG=b:67081508
TEST=with a servo v2 connected to ZerbleBarn,
send host commands v3 through the servo FTDI SPI interface.
Change-Id: I26ff4b6a3a45e446cd16e9da43c6932c24c37256
Reviewed-on: https://chromium-review.googlesource.com/839864
Commit-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
After a call to pthread_create(), it is indeterminate which thread the
caller or the new thread will next execute. Synchronize with the new
thread and allow it to initialize (and print to console, before the
print can potentially interfere with other prints) before proceeding.
BUG=chromium:715011
BRANCH=None
TEST=Run 'make runtests', verify 'Console input initialized' is seen
before '--- Emulator initialized after reboot ---':
====== Emulator output ======
No flash storage found. Initializing to 0xff.
No RAM data found. Initializing to 0x00.
Console input initialized
--- Emulator initialized after reboot ---
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: Ieb622e9b7eea2d11d4a11a98bb503a44534f676c
Reviewed-on: https://chromium-review.googlesource.com/854989
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Add the driver for the new silicon used in STM32H7 SPI controller,
including its bad errata when used with DMA.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=none
BUG=b:67081508
TEST=on ZerbleBarn, do finger image acquisition on the SPI fingerprint
sensor.
Change-Id: Ieaf4a09e961d3e0ef78b58886c409a7dfb63aaf3
Reviewed-on: https://chromium-review.googlesource.com/836617
Commit-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
Start adding support for the STM32H7 family of device and the first
available one the STM32H743.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=none
BUG=b:67081508
TEST=manual, run on stm32h743i-eval and zerblebarn boards
get a stable serial console.
Change-Id: I9ae10f0d843e5318451713c21ed22d455a23758c
Reviewed-on: https://chromium-review.googlesource.com/806168
Commit-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
Boards needs to define GPIO_EC_COMM_PU, which needs to be driven
high during EC-EC transaction. This makes sure that the line does
not go low, even when the base goes away during the transaction.
BRANCH=none
BUG=b:68954760
TEST=EC-EC communication works with this change.
TEST=With signal analyzer, check that UART line is always kept
high while transaction is in progress.
Change-Id: Iad7b26a9a93b674aa4fff0bc3a72a13e6782515d
Signed-off-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/845544
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Typically this routine runs on low priority hook task.
A pre-emption by a higher priority task might be mistaken for timeout.
Double check the transfer done status after the timeout time has passed.
Also clear the TXDONE status before starting a fresh transaction to make sure
we wait for the current transaction to complete; an errand TXDONE status
at start of the transaction will pre-empt waiting for the current transaction
and return stale data.
BRANCH=none
TEST=mn50 stress test fails within minutes vs. now stable.
Main test component is higher priority console task
that does intermittent compute during usb-spi transfers.
Change-Id: Ide4390e42d3957bc45eea8160617a52dd31ed866
Reviewed-on: https://chromium-review.googlesource.com/849662
Commit-Ready: Marius Schilder <mschilder@chromium.org>
Tested-by: Marius Schilder <mschilder@chromium.org>
Reviewed-by: Marius Schilder <mschilder@chromium.org>
Reviewed-by: Nagendra Modadugu <ngm@google.com>
Reviewed-by: Nick Sanders <nsanders@chromium.org>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
The original ec_npcxspiflash lfw is used by the openocd to program SPI
flash via Servo JTAG. In order to support UUT mode to program SPI flash,
this CL modified the lfw with the following changes:
1. Rename the lfw ec_npcxflash to npcx_monitor to unify the naming.
2. The npcx_monitor will read the first 4 bytes from the area of monitor
header. If the monitor identifies the first 4 bytes is a UUT tag, it
will read parameters(SPI_OFFSET/IMAGE_SIZE) from the relative offset of
monitor header. Otherwise, it will read parameter from the general
register r0/r1 which will be restored by openocd script in advance.
3. Add monitor_hdr.c to generate the monitor header binary files
(monitor_hdr_ro.bin/monitor_hdr_rw.bin)) automatically after compiled.
The memory layout to restore the reuqired binaries are listed below:
ec firmware(RO/RW) - the start address of Code RAM area.
monitor header - 0x200C3000
npcx_monitor - 0x200C3020
BRANCH=none
BUG=none
TEST=No build errors for "make buildall".
TEST=Follow instructions in CL:826763; make sure the ec firmware is
updated and ec can boot up.
CQ-DEPEND=CL:828341
Change-Id: I5de997a4dee5449d578972e2f929c6e08c5dff67
Signed-off-by: CHLin <CHLIN56@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/826909
Commit-Ready: CH Lin <chlin56@nuvoton.com>
Tested-by: CH Lin <chlin56@nuvoton.com>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
Some upcoming designs based on the g chip require GPIOs connected to
open drain circuits.
Even though the chip explicitly provides only two open drain GPIOs,
the desired behavior of the rest of the pins when configured as 'open
drain' could be simulated by software if when 'high' is required the
output is disabled instead of driving the pin value.
To make sure there is no fallout from RO driving the pins, also add an
explicit 'disable output' initialization in case a GPIO is configured
for open drain and the initial output value is 'high'.
BRANCH=cr50
BUG=none
TEST=verified that Cr50 booted successfully, also confirmed that on
the test board that GPIOs defined as Open Drain allow we set
output to 1 only if pulled up.
Change-Id: Id2daa19b992bab7fb01148b6fa7b57fd0728b33d
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/848152
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Add Microchip MEC17xx family trace fifo debug
(TFDP) files. TFDP is a MCHP specific two pin,
output only software message port.
Added TFDP module ID.
Change-Id: Ibe2399a8c3618b207a89552450d80b7901e85f23
Signed-off-by: Scott Worley <scott.worley@microchip.corp-partner.google.com>
Add Micorchip MEC17xx family files for
hardware timers, keyboard scan, host
port 80h, UART, and watch dog timer.
BRANCH=none
BUG=
TEST=Review only.
Change-Id: Iac8a912af4d29521964f606637041b06fa7238ee
Signed-off-by: Scott Worley <scott.worley@microchip.corp-partner.google.com>
Add Microchip MEC17xx family PWM and fan
source files for review
BRANCH=none
BUG=
TEST=Review only.
Change-Id: I91439ab999a4662d690b58b0fbbb887f643b3673
Signed-off-by: Scott Worley <scott.worley@microchip.corp-partner.google.com>
Add Microchip MEC17xx family SPI master
controllers and flash files. SPI implements
public interface wrapper for QMSPI and GPSPI.
MEC17xx family uses QMSPI for loading
EC firmware. GPSPI is for general use (sensor).
BRANCH=none
BUG=
TEST=Review only.
Change-Id: I23001e254dd437caa0917949f4dd2eb903f1adb1
Signed-off-by: Scott Worley <scott.worley@microchip.corp-partner.google.com>
BRANCH=none
BUG=
TEST=Review only. Committing small pieces until
all code passes review.
Change-Id: I9d16f95314a7c97b11c4fe61602c6db2621e6024
Signed-off-by: Scott Worley <scott.worley@microchip.corp-partner.google.com>
Add Microchip MEC17xx family little-firmware
(LFW) folder and files.
Change-Id: I9142266d41234574730fadccd5a2cc27fe3d8fd7
Signed-off-by: Scott Worley <scott.worley@microchip.corp-partner.google.com>
Move all the peripheral blocks base addresses in a common block rather
than spread among the register definitions.
This will help making a cleaner STM32H7 implementation whose base
addresses are all different from other families.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=none
BUG=b:67081508
TEST=compare all the ec.bin generated by 'make buildall' and verify
they are bit-identical with and without the change.
Change-Id: I52cafd2f3c9145dbcd585166df3fc78e38573bb4
Nobody is calling the flush function for consumer_ops structure,
so let's remove it to save flash space, until we find a use for it.
CQ-DEPEND=CL:*529221
BRANCH=none
BUG=chromium:795624
TEST=make buildall -j, saves from 40 to 128 bytes on some boards.
Change-Id: Iad18b30f419ccebc54a90914ec46da84b8d19601
Signed-off-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/826905
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
We need to change PLL settings if host apply eSPI operating
frequency higher than 50MHz, because FND clock is required
to be higher than half of operating frequency.
BRANCH=none
BUG=b:70537592
TEST=Change PLL succeed with chip select is low.
Change-Id: Ieba62f33ed024aed7a8e7f4cc48b1398ed781170
Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
Reviewed-on: https://chromium-review.googlesource.com/817717
Reviewed-by: Randall Spangler <rspangler@chromium.org>
In order to make a single hammer image support both base with and
without keyboard backlight. We need a way to dynamically determine if
backlight is present, and send the correct HID descriptors. This is done
through declaring two HID descriptors and return the correct one
depending on whether or not the backlight is present.
BRANCH=none
BUG=b:67722756
TEST=On reworked board with pull-down on backlight pin,
USB descriptor has backlight HID report descriptor, and is
functional.
TEST=On old board with both pull-up and pull-down (equivalent to
having pull-up only, i.e. no backlight)
USB descriptor does not have backlight HID report descriptor
Change-Id: Ie3eac9b3d4cd749308ccfb96a7db469701f9793b
Signed-off-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/770600
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
In some cases, we want to be able to dynamically modify a few bytes
in the USB descriptor (in our case, length of referenced items),
but it could also be other things like flags.
These 2 new functions allow to keep all the USB descriptor in flash, and
modify these few bytes before writing them in the USB buffer.
BRANCH=none
BUG=b:37447752
TEST=Flash hammer, USB descriptors are valid.
Change-Id: I8624255fa43f52a0aaa21d20e963f3974f236912
Signed-off-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/771057
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
For debug, in common code let's log the watchdog PC
and task id as our SW panic params.
BUG=chromium:790006
BRANCH=none
TEST=manually test scarlet rev2 from a1-a3, b1-b2:
(a1) Add 'while(1);' in button ISR
(a2) Boot and press the button
(a3) When watchdog is triggeried, check with 'panicinfo'
that saved R5 is the PC for button ISR.
(b1) 'crash watchdog' in EC console
(b2) Check with 'panicinfo' that CONSOLE task id is saved in
EXCEPTION and PC is saved in R5.
Change-Id: I64d2fcf594dd24b0951e002ab8e80ebcac2d1def
Signed-off-by: Philip Chen <philipchen@google.com>
Reviewed-on: https://chromium-review.googlesource.com/803618
Commit-Ready: Philip Chen <philipchen@chromium.org>
Tested-by: Philip Chen <philipchen@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
us_to_rtcss() could return an invalid value when us approached 1 sec
due to precision loss in the divisor. Change the calculation order to
divide last to eliminate precision loss.
BUG=b:68185182
BRANCH=None
TEST=On scarlet, Verify hw clock closely matches reality w/ low-power idle.
Verify EC doesn't watchdog for 5 hours in S5 / G3 w/ low-power idle. Verify
suspend-stress-test still succeeds to wake device on alarm.
Change-Id: Id40797dd4291e94a54a09bbbdbc1a7f7a00a01b4
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/818332
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Brian Norris <briannorris@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Philip Chen <philipchen@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
stm32f0 / f3 can take up to 40ms to erase a single sector of flash. Also
add a note about instruction fetch being blocked on flash operation
completion.
TEST=`make buildall -j`
BUG=b:70193071
BRANCH=None
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: Icb6c199a975b31f4fa7c73ceb6ad8ec06150abb1
Reviewed-on: https://chromium-review.googlesource.com/815276
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
The PNPCFG (EC2I control module) is used to set I/O port base
address and IRQ number.
On it8320, PNPCFG will be reset while system event PLTRST_L
is asserted. This means we can't decode I/O cycles correctly
until we re-initialize PNPCFG.
We disable this reset source, then we don't need to re-initialize
PNPCFG for each PLTRST_L asserted.
BRANCH=none
BUG=none
TEST=MECC board with it8320 + Intel SKL-Y RVP3 and boot to shell.
Change-Id: I7efe8f726939245424237c1d153df4f83b39ae6b
Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
Reviewed-on: https://chromium-review.googlesource.com/810428
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Even if we set the rtc alarm timeout for more than 86400 secs,
we should not crash the system.
BUG=chromium:768042
BRANCH=none
TEST=on AP console, do 'ectool rtcsetalarm 99999' and
then see 'EC result 3 (INVALID_PARAM)' without crash.
Change-Id: Ic0fa92ff101bce1f4791221c4e1eadaf7a005355
Signed-off-by: Philip Chen <philipchen@google.com>
Reviewed-on: https://chromium-review.googlesource.com/807624
Commit-Ready: Philip Chen <philipchen@chromium.org>
Tested-by: Philip Chen <philipchen@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
After firmware update, cr50 toggles the EC's reset line, expecting
the system will boot. This isn't the case for Chromebox because it
sets AP_OFF flag on a clean shutdown (to restore the previous power
state after power loss & restore).
This patch adds EC_REBOOT_HIBERNATE_CLEAR_AP_OFF to EC reboot
command. It makes EC first clear AP_OFF then hibernate.
BUG=b:69721737
BRANCH=none
TEST=Verify Fizz reboot after cr50 update.
Change-Id: If3207d7284f244ca1adf0d516ef744dbc739a9c1
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/802632
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Also added CONFI_ISH_I2C_PORT0_SPEED, CONFI_ISH_I2C_PORT1_SPEED, and
CONFI_ISH_I2C_PORT2_SPEED to define speed for each ISH I2C port. By
default, those are set to fast mode, 400kbps, I2C_SPEED_FAST.
The values can be modified in board.h.
BUG=None
BRANCH=None
TEST=On Soraka modified board for ISH, set I2C stardard mode, fast mode
and fast mode plus, measured I2C clock freq using scope respectively and
confirmed the freq matched I2C mode.
Change-Id: I426b50dc935c3760903360a50f6069e99bd0abff
Signed-off-by: li feng <li1.feng@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/784091
Commit-Ready: Li1 Feng <li1.feng@intel.com>
Tested-by: Li1 Feng <li1.feng@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
- We have more flash space to use with nds32 toolchain GCC6.3.0,
so we enable a few console commands that were disabled previously.
And we also enable LTO to reduce the size of FW image.
- Put "__wait_evt" function into ram_code section to
fill the gap of flash and improving performance of code-fetch.
BUG=none
BRANCH=none
TEST=boot to kernel on reef_it8320.
Change-Id: I3b745ff80a57ef1163794864c39c22f7e1f86634
Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
Reviewed-on: https://chromium-review.googlesource.com/788712
Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Stalling reset during when CS is asserted is useful to start with, it
was added before out of abundance of caution, but come to think of it,
should the reset happen asynchronously driven be the EC, the AP would
be reset too. And when AP is reset on its own accord, it would not be
transmitting anything on the SPI interface.
On top of that it turns out that in some cases reset on ARM platforms
is accompanied by the CS line driven low, which causes infinite loop
if Cr50 is waiting for CS to deassert before proceeding.
BRANCH=cr50
BUG=b:67008109
TEST=verified that RMA reset operates properly on both ARM and x86
platforms.
Change-Id: I43efd0cefa5d6eb543dfd27e3c9fb3b4bf1a8ea6
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/791818
Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Andrey Pronin <apronin@chromium.org>
This CL fixed the issue that ec cannot enter low power mode, which
increases more power consumption in s5, by not setting ESPIRSTWE bit.
For more detail, please see the npcx5's errata rev1_7, No.2.21.
BRANCH=none
BUG=b:69351155
TEST=No build errors for "make buildall".
TEST=build and flash soraka, run commands to read the power consumption:
dut-control pp3300_dsw_ec_cfg_reg:0x7327k
dut-control pp3300_dsw_ec_mw -t 20 | grep "@@"
the average power consumption measured reduces from 42.x to 10.x mw.
TEST=do cold reboot stress test for 4 hours and no symptom occurred.
Change-Id: Ic6fd7fe14ae8acaefd4e1a99ca1625254f67d708
Signed-off-by: CHLin <CHLIN56@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/778709
Commit-Ready: CH Lin <chlin56@nuvoton.com>
Tested-by: CH Lin <chlin56@nuvoton.com>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
We were using bn_modexp() to perform a simple modular square.
A bn_modexp_word() does this faster.
BRANCH=none
BUG=b:68167013
TEST=generate 128 primes from prng seed and verify they're same as before; tcg_test passes
Change-Id: I411a7d3fe2d68f93dc40bf74b941a637f9aa20ed
Reviewed-on: https://chromium-review.googlesource.com/778057
Commit-Ready: Marius Schilder <mschilder@chromium.org>
Tested-by: Marius Schilder <mschilder@chromium.org>
Reviewed-by: Marius Schilder <mschilder@chromium.org>
Reviewed-by: Nagendra Modadugu <ngm@google.com>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
With the upcoming change to add a new command to get/set/clear host
events and masks, it seems to be the right time to bump up the host
events and masks to 64-bit. We are already out of available host
events. This change opens up at least 32 bits for new host events.
Old EC commands to operate on host events/masks will still deal with
lower 32-bits of the events/mask. On the other hand, the new command
being added will take care of the entire 64-bit events/masks. This
ensures that old BIOS and kernel versions can still work with the
newer EC versions.
BUG=b:69329196
BRANCH=None
TEST=make -j buildall. Verified:
1. hostevent set 0x4000 ==> Sets correct bit in host events
2. hostevent clear 0x4000 ==> Clears correct bit in host events
3. Kernel is able to query and read correct host event bits from
EC. Verified using evtest.
4. Coreboot is able to read correct wake reason from EC. Verified
using mosys eventlog list.
Change-Id: Idcb24ea364ac6c491efc2f8dd9e29a9df6149e07
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/770925
Reviewed-by: Randall Spangler <rspangler@chromium.org>
If the i2c master sends a stop condition before we've buffered the last
Rx byte (eg. due to higher than normal i2c interrupt latency) then we
don't want to drop the last byte on the floor, it's still meaningful.
BUG=b:65711378
BRANCH=glados
TEST=Spam TCPC_REG_ROLE_CTRL commands from caroline to caroline_pd,
verify no errors are observed on either side for 12,000,000
transactions.
Change-Id: I0c4a81d97315cff553a5448c0940746e1ef0ed2c
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/771936
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
EC_IN_RW signal is used to determine if the switch to dev mode can be
safely made. However, EC_IN_RW needs the EC_RST_L line driven low in
order to be reset. In faft tests that utilize crosEcSoftrecPower
method, EC_RST_L is not being driven by servo to fix other test
failures related to keeping EC and AC reboots in sync.
This CL adds a new argument 'wait-ext' to the EC reboot command.
When this option is used, instead of the EC generating a reset via
it's system watchdog, it will wait 10 seconds for EC_RST_L to be
driven.
BUG=b:64603944
BRANCH=coral
CQ-DEPEND=I086687c3dd7591460099267880d56ab8265d2e4b
TEST=Ran "/usr/bin/test_that --board=coral <ip addr> firmware_DevMode"
mutliple times and verified that it passes. Previoulsy, this test
always fails when the EC is in RW before it starts. Also tested
platform_ServoPowerStateController_USBPluggedin and verified it passed.
Change-Id: I614f9156066d5719601ee43e29c7a064f9bba6e2
Signed-off-by: Scott Collyer <scollyer@google.com>
Reviewed-on: https://chromium-review.googlesource.com/737524
Commit-Ready: Scott Collyer <scollyer@chromium.org>
Tested-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
