Commit Graph

8725 Commits

Author SHA1 Message Date
Duncan Laurie
5c611cedbf Add config for boards that cannot distinguish reset type
We have a growing list of boards in chip/npcx/system.c that are
unable to distinguish a reset from a power-on or a reset-pin type.

Instead of being a temporary issue this is now solidified in the
design on some kabylake boards.

Instead of defining board-specific checks in the chip code this
change adds a config option that the relevant boards can define.

BUG=b:76232539
BRANCH=none
TEST=make -j buildall passes

Change-Id: I76e0f011d70ce6f778b1fb6a56c2779c39c3cbd6
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://chromium-review.googlesource.com/979575
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
2018-03-26 02:07:24 -07:00
Duncan Laurie
245b494e14 keyboard: Add config option for refresh key row
The keyboards that have an assistant key also move the row that
the refresh key is on from 2 to 3.   The row is hardcoded and
used by the early boot key detection code to determine if
boot keys should be honored.

The fallout from not having the right refresh row defined was
not seen on Eve because that board has a different quirk where
it does not distinguish reset-pin vs power-on reset types so
the test in check_boot_keys() was not failing.

BUG=b:76232955
BRANCH=none
TEST=manual testing on Eve board

Change-Id: I5b94b4e32024afa1768bdf371a7eb951753014e8
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://chromium-review.googlesource.com/979574
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
2018-03-26 02:07:23 -07:00
Vijay Hiremath
3e12d9af20 intel_x86: Move chipset reset logic to common code
Chipset reset logic chipset_reset() is same for APL, GLK,
SKL, KBL and CNL hence move it to common code.

BUG=b:72426192
BRANCH=none
TEST=make buildall -j

Change-Id: I289e9807d53e397e62d650289e80b6ce25fe399e
Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/974471
Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Jett Rink <jettrink@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
2018-03-25 00:50:40 -07:00
Vijay Hiremath
e94bf79f85 apollolake: Remove AP cold reset logic
In APL & GLK, cold reset code does a AP force shutdown (with board
specific AP shutdown code) by power sequencing the SOC all the way
to S5 and bring it back to S0. However there is no separate GPIO
in APL & GLK for doing AP cold reset hence removed the AP cold
reset logic.

BUG=b:72426192
BRANCH=none
TEST=make buildall -j
     Manually verified on GLKRVP, apreset cold & warm behave same

Change-Id: I6ee5e4c4df94e685acdabe31b8b5554295883792
Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/974107
Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
2018-03-25 00:50:39 -07:00
Furquan Shaikh
286dfbd0c9 yorp: Switch on blue LED on boot-up
This is helpful during early debugging to identify if the EC is up and
running. This will be later cleaned up as part of LED support for
yorp.

BUG=b:74952719
BRANCH=None
TEST=Verified that blue led glows up on booting up EC.

Change-Id: I4670c210045c649a926e7c3f23c5d6097df69e3d
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://chromium-review.googlesource.com/979270
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
2018-03-24 20:53:31 -07:00
Vijay Hiremath
3bd4e0de5e Code cleanup: Rename GPIO PCH_RCIN_L to SYS_RESET_L
Renamed GPIO PCH_RCIN_L to SYS_RESET_L so that all the Intel
chipset variants have same GPIO name for doing SOC internal reset.

BUG=b:72426192
BRANCH=none
TEST=make buildall -j

Change-Id: I931ce136743fa928dd7cf6f005c912db3b2da893
Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/974241
Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Jett Rink <jettrink@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
2018-03-24 07:32:29 -07:00
Philip Chen
f59290878e battery/max17055: Report the raw measured current
BUG=b:74321682
BRANCH=scarlet
TEST=battery command shows current change instantaneously when
AC charger is plugged/unplugged

Change-Id: Ic47efbdfc861355325ee2c69be09fbcfa1394654
Signed-off-by: Philip Chen <philipchen@google.com>
Reviewed-on: https://chromium-review.googlesource.com/977022
Commit-Ready: Philip Chen <philipchen@chromium.org>
Tested-by: Philip Chen <philipchen@chromium.org>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
2018-03-23 17:29:48 -07:00
Aseda Aboagye
8ea61bf52a meowth: Add GPP_B14_STRAP pins for both SKUs.
GPP_B14_STRAP is being moved due to a change in EC SKU.  We're not
currently using this pin, but if we decide to in the future, we can set
up the appropriate one based upon reading the Chip ID register.

BUG=b:71717245
BRANCH=None
TEST=Build and flash on both ECs, verify that they both boot up
normally.

Change-Id: Iaa25d5d77939bf55d6dc3991eec89ad5d6e92abb
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/978677
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
2018-03-23 17:29:47 -07:00
Jett Rink
a63f6a6240 bip: add gpio definitions
BRANCH=none
BUG=b:75972988
TEST=none

Change-Id: I4c20103083dc224d449bdc659a2b359808218cb0
Signed-off-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/976526
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-03-23 14:51:06 -07:00
Jett Rink
ca204befd3 tcpc: rename CONFIG_USB_PD_TCPM_ANX74XX to CONFIG_USB_PD_TCPM_ANX3429
Since all of the uses of CONFIG_USB_PD_TCPM_ANX74XX are actually for
ANX3429, rename the option especially since the ANX7447
driver will not reuse the ANX74XX driver which is being introduced
in CL:956790.

Also adding the CONFIG_USB_PD_TCPM_ANX740X and
CONFIG_USB_PD_TCPM_ANX741X options to advertise which versions of the
ANX chip the anx74xx.c driver applies to.

BRANCH=none
BUG=chromium:824208
TEST=build all

Change-Id: Ib47f4661466e54ff2a0c52d517eb318d3bfd25a2
Signed-off-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/973558
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
2018-03-23 14:50:51 -07:00
Scott Collyer
d1bb1da8e7 yorp: Add config option for VBUS detection
For your VBUS detection will rely on TCPCs since neither the intersil
charger nor the NX20P PPC do VBUS detection.

BUG=b:75975215
BRANCH=none
TEST=make -j BOARD=yorp and verify there are no errors.

Change-Id: I205e4e986e4d01c1098ab62cbccf2ab940f58eed
Signed-off-by: Scott Collyer <scollyer@google.com>
Reviewed-on: https://chromium-review.googlesource.com/977325
Commit-Ready: Scott Collyer <scollyer@chromium.org>
Tested-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Jett Rink <jettrink@chromium.org>
2018-03-23 14:50:48 -07:00
Vadim Bendebury
c3e92e92bb makefile: fix build time warnings
Recently, when building images for Cr50 the following warnings started
being generated by make:

board/cr50/build.mk:98: warning: overriding recipe for target \
     'build/cr50/tpm2/libtpm2.a'
board/cr50/build.mk:98: warning: ignoring old recipe for target \
     'build/cr50/tpm2/libtpm2.a'

The reason for this turned out to be changes under
https://chromium-review.googlesource.com/954444

Let's make sure specific make file is not included in the build twice.

BRANCH=cr50, cr50-mp
BUG=none
TEST='make buildall -j' succeeded. Verified that there is no warnings
     reported in the make output.

Change-Id: I96924752eb91669957d2b514d8926ac843b2bf93
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/977021
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Jett Rink <jettrink@chromium.org>
2018-03-23 12:10:15 -07:00
Vadim Bendebury
4d959e92ca cr50: update manifests for both dev and prod versions
BRANCH=cr50, cr50-mp
BUG=none
TEST=none

Change-Id: I377aab1b5a729a0ca98e2340050300d938e51bd5
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/978541
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
2018-03-23 18:11:27 +00:00
Divya Sasidharan
aa4474d3b1 yorp: Enable lid, base accel and gyro sensor
This is initial configuration changes and
enable motion sensor task.

BUG=b:74129963,b:74132236
BRANCH=none
TEST=Verified "make buildall -j and make BOARD=yorp"

Change-Id: Ia45d6434a2c034c0ec650d7b46d6f664848f9153
Signed-off-by: Divya Sasidharan <divya.s.sasidharan@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/961459
Commit-Ready: Divya S Sasidharan <divya.s.sasidharan@intel.com>
Tested-by: Divya S Sasidharan <divya.s.sasidharan@intel.com>
Reviewed-by: Jett Rink <jettrink@chromium.org>
2018-03-22 20:53:38 -07:00
Mary Ruthven
6e18f8f981 rma_reset: fix ignored return value error
The fread return value was ignored in rma_reset.c. This caused clang
compilation to fail.

This change checks the return value.

BUG=b:76105747
BRANCH=none
TEST=clang compilation no longer fails

Change-Id: I710b367008b2e17a94c875ea3eae92bcc75546b0
Signed-off-by: Mary Ruthven <mruthven@google.com>
Reviewed-on: https://chromium-review.googlesource.com/976555
Commit-Ready: Mary Ruthven <mruthven@chromium.org>
Tested-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
2018-03-22 20:53:26 -07:00
Mary Ruthven
e33c1d8de0 rma_reset: update Makefile to use different compiliers
BUG=b:76105747
BRANCH=none
TEST=compile for bob and reef. make sure it runs on both

Change-Id: I30004c9794c9619698889fecbf8746778ebbb48c
Signed-off-by: Mary Ruthven <mruthven@google.com>
Reviewed-on: https://chromium-review.googlesource.com/976554
Commit-Ready: Mary Ruthven <mruthven@chromium.org>
Tested-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
2018-03-22 20:53:25 -07:00
Jett Rink
8b0f4b55c5 yorp: clean bug comments
Removing old comment and updating another to a more specific bug.

BRANCH=none
BUG=none
TEST=none

Change-Id: I7542b68e590facf9d8f7b98539cc4a161359c213
Signed-off-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/969649
Reviewed-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
2018-03-22 18:16:53 -07:00
Divya Sasidharan
b9fbc80fa3 usb_mux: Fix incorrect revision check at init for ps874x
This patch fixes revision check for ps8xxx usb mux and
thereby removing print "Error initializing mux port(x)"
at bootup.
This is just a cosmetic change and should not affect any
functionality.

BUG=none
BRANCH=glkrvp
TEST=On glkrvp: Boot up the system to verify the
     error message setting mux is gone at init.

Change-Id: I0926077d50e818bd93aaa4214106b2f8067d9710
Signed-off-by: Divya Sasidharan <divya.s.sasidharan@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/846291
Commit-Ready: Divya S Sasidharan <divya.s.sasidharan@intel.com>
Tested-by: Divya S Sasidharan <divya.s.sasidharan@intel.com>
Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Jett Rink <jettrink@chromium.org>
2018-03-22 18:16:50 -07:00
Jett Rink
4c4d80ca5d yorp: update gpio alternate function parameter
The NPCX driver doesn't use anything but >= 0; make everything
consistent as to not imply something is different between UART and
everything else.

BRANCH=none
BUG=none
TEST=none

Change-Id: Ib98f56f7004df2405df7d2cc1847f1ed4b3ec558
Signed-off-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/976524
Reviewed-by: Edward Hill <ecgh@chromium.org>
2018-03-22 18:16:49 -07:00
Elthan_Huang
80c8ed8585 Nami: Add SENSOR_CONFIG_EC_S0 for ALS sensor
EC should sample ALS luminance in S0.
Add SENSOR_CONFIG_EC_S0 to let EC to
sample the ALS luminance in S0.

BUG=b:76115061
BRANCH=none
TEST=Verify ALS(OPT3001) luminance
can be read in S0 via ec console.

Change-Id: I34293c41086ac0228c2bb7f159193a1b59807a63
Signed-off-by: Elthan_Huang <elthan_huang@compal.corp-partner.google.com>
Reviewed-on: https://chromium-review.googlesource.com/974921
Commit-Ready: Gwendal Grignou <gwendal@google.com>
Tested-by: Elthan Huang <elthan_huang@compal.corp-partner.google.com>
Reviewed-by: Raymond Chou <raymond_chou@compal.corp-partner.google.com>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-by: Gwendal Grignou <gwendal@google.com>
2018-03-22 18:16:48 -07:00
Jett Rink
7742e06e45 bip: initial add of bip skeleton
BRANCH=none
BUG=b:75972988
TEST=build all

Change-Id: Ibfadaee3b9584a7e2c87f6f607be4cba20f338b7
Signed-off-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/972142
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
2018-03-22 18:16:47 -07:00
Gwendal Grignou
9304e2ac01 board: Add CONFIG_ACCEL_FORCE_MODE_MASK for ALS when needed
Some board did not configured the ALS in force mode.
We were lucky that their data was collected while scanning other
sensors, but that's not true anymore since CL:959112

BUG=b:75533383
TEST=Compile
BRANCH=poppy

Change-Id: I4c6f744756a90dd9f2d142bb56826e91b806d5dd
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/969627
Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
2018-03-22 15:24:44 -07:00
Vincent Palatin
0f32382760 meowth_fp: enable CONFIG_HOST_COMMAND_STATUS
Seems expected from the kernel side since we are using a SPI interface
for host commands.

Signed-off-by: Vincent Palatin <vpalatin@chromium.org>

BRANCH=none
BUG=b:71986991
TEST=run on Meowth, check kernel logs.
TEST=re-flash meowth_fp RW partition through the host command interface
e.g. flashrom -p ec:type=fp -i EC_RW -w meowth_fp.bin

Change-Id: I8455ba169d0fca7f99dc040c465693c73cebb6b3
Reviewed-on: https://chromium-review.googlesource.com/966022
Commit-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
2018-03-22 15:24:42 -07:00
Wei-Han Chen
aab7366187 usb_update: check touchpad_info size at build time
Current protocol will not work if touchpad_info is more than 50 bytes.
Assert this constrain at build time.

BRANCH=none
BUG=b:70482333
TEST=make BOARD=hammer
Signed-off-by: Wei-Han Chen <stimim@chromium.org>

Change-Id: I9bf163f77f14c7d475fc8a2f422ce596dc89c61e
Reviewed-on: https://chromium-review.googlesource.com/958893
Commit-Ready: Wei-Han Chen <stimim@chromium.org>
Tested-by: Wei-Han Chen <stimim@chromium.org>
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
2018-03-22 10:58:26 -07:00
Wei-Han Chen
9a8e4226c3 util/unpack_ftb.py: a script to convert FTB file into bin file
ST firmwares are released in FTB format, which can't be written to flash
directly.  This python script can convert a file in FTB format into
bin file.  Currently, we only support FTB files of whiskers touchpad
firmware.

BRANCH=none
BUG=b:70482333
TEST=manual
Signed-off-by: Wei-Han Chen <stimim@chromium.org>

Change-Id: I179de12663580881347a31f11b5b10659e00b879
Reviewed-on: https://chromium-review.googlesource.com/918603
Commit-Ready: Wei-Han Chen <stimim@chromium.org>
Tested-by: Wei-Han Chen <stimim@chromium.org>
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
2018-03-22 10:58:26 -07:00
Gwendal Grignou
7dfb352adc board: In motion sensor array, remove more assignment to 0
BUG=none
TEST=Compile
BRANCH=none

Change-Id: I86ccc26d7fb6d482dca3275a4365729ff8644777
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/969626
2018-03-22 05:14:47 -07:00
Jagadish Krishnamoorthy
b073dba72a Eve: Enable usb device mode
For the dual data role, when the state is UFP
assert the otg pins to activate the usb device controller.
This will enable usb gadget mode and the board will act as
usb device instead of host.
For DFP state, de-assert the otg pins to activate the host mode.

BUG=b:74339386
BRANCH=NONE
TEST=Connect two Eve boards with the usb type c cable.
On ec console, type the command usb pd 0 swap data.
pd 0 state should return UFP mode.
Verify that the otg pins are high (USB2_OTG_ID and USB2_OTG_VBUSSENSE).

Change-Id: I0efb08ae3946ff09ce9dfeb89cff049e551fe000
Signed-off-by: Jagadish Krishnamoorthy <jagadish.krishnamoorthy@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/961381
Reviewed-by: Divya S Sasidharan <divya.s.sasidharan@intel.com>
Reviewed-by: Duncan Laurie <dlaurie@google.com>
2018-03-21 23:23:38 -07:00
Jett Rink
a615f3c7d3 yorp: Enabling power in both USB-A ports in S0
BRANCH=none
BUG=b:74388692,b:75986973
TEST=build all

Change-Id: Ief74b3e1a18ca90cb8fbf76c51780f659e4caf61
Signed-off-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/974310
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
2018-03-21 20:48:39 -07:00
Furquan Shaikh
e513b7339a nautilus: Use I2C callbacks to ensure minimum bus free time for battery
Battery on nautilus requires a minimum bus free time of 5ms between
I2C transactions. Use I2C_XFER_CALLBACK mechanism to ensure that this
time is guaranteed before starting a new i2c transaction.

BUG=b:73147310
BRANCH=None
TEST=make -j BOARD=nautilus. Verified on nautilus that no issue is
observed while charging the battery.

Change-Id: Ieba168835190b5d1334e413dc4f74e0248bf5a15
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://chromium-review.googlesource.com/957966
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
2018-03-21 20:48:36 -07:00
Philip Chen
9aee2a19e8 battery/max17055: Implement battery_status()
BUG=b:74841068
BRANCH=scarlet
TEST='/sys/class/power_supply/sbs-9-000b/status' shows
discharging/charging/full status correctly

Change-Id: I4216ba2d95ac82a9f600d8685d993cb5b37206d8
Signed-off-by: Philip Chen <philipchen@google.com>
Reviewed-on: https://chromium-review.googlesource.com/969747
Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com>
Tested-by: Philip Chen <philipchen@chromium.org>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
2018-03-21 13:25:57 -07:00
Scott Collyer
6e92603e06 yorp: Include NXP203483 PPC driver
This CL fills out the ppc_chips and config options required to support
the NX20P3483 PPC. On Yorp for port 0 SNK/SRC control is driven by the
TCPC, while on port 1 it's driven by the EC.

BUG=b:74206647,b:74127309
BRANCH=none
TEST=make -j BOARD=yorp and verify there are no errors.

Change-Id: I41920be0bf4d9232101d8e1840714ca0c70f1bc5
Signed-off-by: Scott Collyer <scollyer@google.com>
Reviewed-on: https://chromium-review.googlesource.com/966927
Commit-Ready: Scott Collyer <scollyer@chromium.org>
Tested-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Jett Rink <jettrink@chromium.org>
2018-03-20 22:21:39 -07:00
Scott Collyer
261afe62f3 ppc: Add driver for NX20P3483
The NX20P3483 is a USB PD and Type C high voltage sink/source combo
switch. This CL adds support for this PPC variant. Unlike the TI
SN5S330, the NX20P3483 does not support VCONN and does not need to be
informed of CC polarity by the TCPM. To account for these differences,
2 new PPC config options are added and the driver for the TI SN5S330
was modified to include these new options.

The SNK/SRC switch mode for the NX20P3483 is controlled by 2 GPIO
signals which may be connected the EC or directly to the TCPC. To
handle both cases, the ppc_chips structure was modified with a flags,
snk_gpio, and src_gpio elements.

BUG=b:74206647
BRANCH=none
TEST=make -j buildall and verified there are no build errors.

Change-Id: Ic4415ab7571b80e7661ea673434eaf4cf1f1fd2d
Signed-off-by: Scott Collyer <scollyer@google.com>
Reviewed-on: https://chromium-review.googlesource.com/966926
Commit-Ready: Scott Collyer <scollyer@chromium.org>
Tested-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
2018-03-20 19:30:17 -07:00
Furquan Shaikh
699838c0c1 i2c: Add option for calling board-specific functions before and after every i2c transaction
This change adds a new config option CONFIG_I2C_XFER_CALLBACK that
makes i2c_xfer callback into board-provided functions before the start
and after the end of every I2C transaction. This can be used by boards
to implement any I2C device-specific quirks e.g. requiring minimum
bus-free time between every I2C transaction when the slave device
cannot actually do clock stretching.

BUG=b:73147310
BRANCH=None
TEST=make -j buildall

Change-Id: I452de4f22a81ffd97ca4944e1b940a3537637df9
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://chromium-review.googlesource.com/956934
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
2018-03-20 19:30:14 -07:00
Jeff Andersen
228430afdd Add vsnprintf function.
This function enables variadic functions to take advantage
of functionality provided by snprintf.

Signed-off-by: Jeff Andersen <jeffandersen@google.com>

BRANCH=none
BUG=b:72360575
TEST=make buildall -j

Change-Id: I0095a96339b374ef8030b87b5184fa4678b439eb
Reviewed-on: https://chromium-review.googlesource.com/971761
Commit-Ready: Jeff Andersen <jeffandersen@google.com>
Tested-by: Jeff Andersen <jeffandersen@google.com>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
2018-03-20 19:30:06 -07:00
Jett Rink
50da99d5d4 power: create CONFIG_CHIPSET_GEMINILAKE
Geminilake uses the same power sequencing code as Apollolake. Instead
of the board specifying the wrong chipset, we will make the correct
chipset reuse the existing power code.

This also gives us flexibility in the future if GLK needs to vary from
ALK in any of shared code.

BRANCH=none
BUG=b:74020444
TEST=build all

Change-Id: Icd00286ac4f0612d1bda56677c4141957480c6bf
Signed-off-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/969613
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
2018-03-20 14:38:42 -07:00
Daisuke Nojiri
b5fddbbe26 Fizz: Log DP mode entry and exit
This helps us tell whether a monitor lost picture because the EC
exited the DisplayPort mode or other reason.

BUG=b:75288273
BRANCH=none
TEST=boot Fizz

Change-Id: I2da6a27c66f03ef780a0ed6f60a597a01f248942
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/966993
Reviewed-by: Todd Broch <tbroch@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
2018-03-20 12:16:08 -07:00
Vincent Palatin
fed441c689 fpsensor: add enrollment and matching interface
Add the state machine and the interfacing to the enrollment and matching
algorithm providing by the private driver part.

Implement the host commands interface for it (based on MKBP event) along
with the console debug commands to exercise it.

Signed-off-by: Vincent Palatin <vpalatin@chromium.org>

BRANCH=none
BUG=b:72360575
TEST=On ZerbleBarn console, use 'fpenroll' then 'fpmatch' for several
fingers.
TEST=With ZerbleBarn and a servo-v2, retrieve and upload templates with
'ectool_servo fptemplate'.
TEST=On Meowth, exercise with the prototype of biod
CrosFpBiometricsManager.
CQ-DEPEND=CL:*555078

Change-Id: I10b0d76d3faa898a682cf9a2eb7fc7e212b0c20c
Reviewed-on: https://chromium-review.googlesource.com/886401
Commit-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
2018-03-20 07:24:25 -07:00
Furquan Shaikh
bb48421c98 poppy: Lower VCCIO from 0.975V to 0.850V
CQ-DEPEND=CL:*591042
BUG=b:75978856
BRANCH=poppy
TEST=No regressions observed.

Change-Id: I3c481ac46bd9005df05f7be13bee8799959fb282
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://chromium-review.googlesource.com/969786
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
2018-03-20 02:21:59 -07:00
Aseda Aboagye
84f8f46851 meowth: Add support for base detection.
Meowth has two analog detection pins with which it monitors to determine
the base status: the attach, and detach pins.  When the voltages cross a
certain threshold, after some debouncing, the base is deemed connected.
Meowth then applies the base power and monitors for power faults from
the eFuse as well as base disconnection.  Similarly, once the voltages
cross a different threshold, after some debouncing, the base is deemed
disconnected.  At this point, Meowth disables the base power.

BUG=b:69140200
BRANCH=None
TEST=Verify that we can detect a base attach and detach.
TEST=Verify that when base is attached, tablet mode goes to 0, and goes
to 1 when the base is detached.
TEST=Connect base, take a paper clip and short the attach pin to ground
to trigger a fault 4 times in a row.  Verify that base power is disabled
yet base detect state machine still reports attached.  Wait at least 1s,
physically detach and reattach base, verify that base power is
re-enabled.

Change-Id: I2a069fc450c2232c7eae02b8e7459d38a049668a
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/923396
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
2018-03-20 00:00:31 -07:00
Vadim Bendebury
48d6891db8 cr50 signer: allow to use directory to specify source files
In most cases when Cr50 signer script is invoked, the input elf files
are stored in the same directory and named ec.RW.elf and ec.RW_B.elf,
the way they produced by the EC makefile.

Let's allow create_released_image.sh to accept a directory name
instead of two elf file names.

BRANCH=none
BUG=none
TEST=verified that the script properly handles both old and new
     command line options (allows to pass individual elf files and a
     directory name).

Change-Id: I40bb8983fd97e6cd82e235308622ba2f20119ce5
Signed-off-by: Vadim Bendebury <vbendeb@google.com>
Reviewed-on: https://chromium-review.googlesource.com/963618
Commit-Ready: Vadim Bendebury <vbendeb@chromium.org>
Tested-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-by: caveh jalali <caveh@chromium.org>
2018-03-19 21:34:30 -07:00
Nick Sanders
831d2b2597 servod: add command muxing in ec3po
This creates a second pty for pty_driver to open, to prevent the
need for freezing the user pty. This also allows the user pty to
fully log and print all output.

BRANCH=None
BUG=b:74023102,b:73310923
TEST=servod is fast now, recovery works
CQ-DEPEND=CL:958127

Change-Id: Ib369a5e64838ded98719d76f8159d71a97fe08ad
Signed-off-by: Nick Sanders <nsanders@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/958128
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
2018-03-19 19:21:25 -07:00
Gwendal Grignou
ad275d5fb9 board: meowth: add ST LSM6DSL sensors
Add LSM6DSL accel + gyro support to meowth.

FIFO and gesture support will be added later.

BUG=b:69140267,b:73546254
BRANCH=master
TEST=use accelinfo to get sensor data.

Change-Id: I4362fe5dd568fb5d696c460432b5c0a6a80be83e
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/924411
2018-03-19 19:21:22 -07:00
Gwendal Grignou
3d3a009f49 driver: lsm6dsm: fix units
Units must be reported in according to the range.
2g means 1<<15 should be returned when accel is 2g.
Actually accelerometer report units in mg.

BUG=b:73546254
BRANCH=master
TEST=Check with accelinfo with 2g gain Z ~= 1<<14.

Change-Id: I218210ca8305ecbe76a681b535f3d75f3a6bea52
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/924408
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
2018-03-19 19:21:21 -07:00
Gwendal Grignou
94f5413159 driver: lis2dh: fix gain units
Accelerometer reports accelerating in mg. Fix gain to that full range
(2g, 4g or 8g) returns 2<<15.

BUG=b:73546254
BRANCH=master
TEST=compile

Change-Id: I2873a641985fa800709a2d30b031c2b6e3fcb39e
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/924407
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
2018-03-19 19:21:21 -07:00
Gwendal Grignou
b87bea3289 driver: lsm6dsm: Add ectool support.
BUG=b:73546254
BRANCH=master
TEST=compile

Change-Id: If914dfbf7bb30e934b711d8f89c46af2787f917c
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/924406
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
2018-03-19 19:21:20 -07:00
Gwendal Grignou
88613a3aa2 driver: accel_lis2dh: Fix interface
Add support in ectool, expose min/max ODR.

BUG=b:73546254
BRANCH=master
TEST=compile

Change-Id: Ib09c06e17d7d73aaab91680672de4d5267299c7f
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/924405
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
2018-03-19 19:21:19 -07:00
Gwendal Grignou
47f344713e driver: lsm6dsm/lsm6dsl/lis2dh: Use STM MEMs common functions
LSM6DSM now use STM MEMs common functions already
used by LIS2DH12 device. Added st_raw_read_n_noinc
function to read i2c data not using auto increment
protocol.

BUG=b:73546254
BRANCH=master
TEST=Tested on discovery BOARD with LSM6DSM sensor connected on
I2C master bus interface of target board.
Using motion sense console commands is possible to enable, set data
rate, set full scale and show data from sensor (acc and gyro).
Commons function works properly for LSM6DSM.

Change-Id: I7a987306135a85abcfa9c1d3ba596fb70598fadc
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/465376
2018-03-19 19:21:18 -07:00
Vadim Bendebury
1f4d4f8a4e cr50: update version numbers to match Cr50 branches
This reflects version changes in Cr50 branches.

BRANCH=none
BUG=none
TEST=none

Change-Id: I121c65797a30595a58d0b55774e80147692bda38
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/969340
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
2018-03-19 17:05:03 -07:00
Scott Collyer
4db1ab4d6f yorp: Enable CONFIG_VBOOT_HASH
CONFIG_VBOOT_HASH needs to be set in EC config

BUG=b:75276859
BRANCH=none
TEST=make -j BOARD=yorp and verify there are no errors.

Change-Id: Ief7adb8afe40fda02aa6b84a3f81971a3c64e455
Signed-off-by: Scott Collyer <scollyer@google.com>
Reviewed-on: https://chromium-review.googlesource.com/966934
Commit-Ready: Scott Collyer <scollyer@chromium.org>
Tested-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Jett Rink <jettrink@chromium.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
2018-03-19 17:05:00 -07:00
Yidi Lin
7640df67aa driver: kionix: Add software reset flow for KX022
Kionix suggests that it is recommended to issue the Software Reset
command after the device was powered. This is effective against
dynamic or non-linear behavior of a power supply or unexpected
noise above normal on the power rail during a power up.

BRANCH=eve
BUG=b:62607555
TEST=kx022:
     1. press power button 10 second to power off.
     2. power on the DUT
     3. refresh + power button to cold reboot the DUT
     4. Check the g-sensor by 'ectool motionsense'
     kxcj9:
     eve: sensor kxcj9 found.

Signed-off-by: Yidi Lin <yidi.lin@mediatek.com>
Reviewed-on: https://chromium-review.googlesource.com/536723
Reviewed-by: Gwendal Grignou <gwendal@chromium.org>
(cherry picked from commit 5a52614b8c87ab1de84c461b7bbd0b4a14dc7fdb)
 Conflict in init routine in accel_kionix.c.
 By moving WHOAMI after reset, we expect the test to work the first
 time.)
Change-Id: I362f2af59253519aa35b72cfb6b666c49e425777
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/753969
2018-03-19 17:04:54 -07:00