This change adds a ccd console command to control the usb endpoints.
The uart console command is moved into this command so 'ccd uart
[enable|disable]' controls the AP and EC TX signals instead of the
'uart' console command. CCD can be enabled using 'ccd enable'. This
switches the PHY used by the USB controller to be the external PHY.
Changing the PHY exposes the cr50, AP, and EC consoles as well as the
upgrading mechanisms for the AP, EC and cr50. The AP and EC consoles
will be read only until 'ccd uart enable' is called. Cr50 can be updated
using the usb upgrade endpoint. The EC and AP can be updated using the
USB SPI endpoint.
When CCD is disabled the usb controller will switch to using the AP PHY.
None of the endpoints will be visible to the host.
The USB SPI endpoint can be used to flash the EC or AP using
'flashrom -p raiden_debug_spi:target=[AP|EC]'. If CCD is not enabled
running flashrom using the raiden_debug_spi programmer will fail. Cr50
will not forward the commands to the external AP or EC ROM, so flashrom
will not be able to find the chip.
The UART TX signals are now controlled by the 'ccd uart' console
command instead of the 'uart' console command. The UART TX is enabled
separately from CCD, because we want to be able to enable CCD while
servo is connected, and having the cr50 UART TX pins wired directly to
the Servo TX lines could damage both devices. The AP and EC consoles
are be read only until 'ccd uart enable' is called. 'ccd uart disable'
disconnects the AP and EC TX pins from the UART peripheral.
When RDD becomes reliable on cr50, ccd_set_mode will select the PHY
being used by the g chip USB controller.
BUG=chrome-os-partner:49960,chrome-os-partner:52281
BRANCH=none
TEST=manual
TEST SERVO
power cycle the DUT
connect servo and check that the AP and EC consoles still work
check that both the AP and EC can be flashed using servo.
TEST SUZY Q
Attach Suzy Q
Connect to the all three consoles. Check that the cr50 console
is in read-write mode and the EC and AP consoles are read only.
Attach Servo.
Verify all of the servo functionality described above still
works with suzy q attached and ccd enabled.
Disconnect Servo.
run 'ccd uart enable' on the cr50 console and check both the AP
and EC consoles can be written to.
Check that the AP and EC can be programmed using the
raiden_debug_spi programmer.
Change-Id: I96db2a72fc95086871c9e4c778c19ebd01efb851
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/342563
While in CCD, cr50 can be used to flash the AP and EC through USB. This
change adds an endpoint that can be used to read, erase, and write to
the AP and EC spi rom.
Currently CCD is not enabled on cr50, so usb_spi access has to be
enabled manually through the cr50 console.
BUG=chrome-os-partner:50701
BRANCH=none
TEST=manual
On EC console run 'flash_tristate true'
On cr50 console run 'usb_spi enable'
Use 'flashrom -p raiden_debug_spi:target=EC' and
'flashrom -p raiden_debug_spi:target=AP' to interact with
the AP and EC flash
CQ-DEPEND=CL:342144
Change-Id: I9c31dab252a8bfbc498eaf64ac5c2f53ec9dde30
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/342511
Update power sequencing as per Rachel's recommendation. We currently
wait for PP5000_PG and PP3300_PG before enabling the PMIC. This changes
the order so that we don't wait for PP3300_PG before setting the PMIC
enable.
BUG=chrome-os-partner:51323
BRANCH=none
TEST=see scope shots mentioned in the BUG
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Change-Id: I022a9ab21c1bcb70dc72f358dbf89acb656851b8
Reviewed-on: https://chromium-review.googlesource.com/349291
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
add a new config flag to support active low power control signal
BUG=chrome-os-partner:53665
BRANCH=none
TEST=Use multimeter to check for voltage present on the WiFi slot.
Use gpioget to check GPIO state in S0 (on) and S5 (off).
Change-Id: Ibeca88d16f39eadd7f29589cd3cd15aeef0dd524
Signed-off-by: Kevin K Wong <kevin.k.wong@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/347085
Commit-Ready: David Hendricks <dhendrix@chromium.org>
Tested-by: David Hendricks <dhendrix@chromium.org>
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Previously CONFIG_USB_PD_TCPM_VBUS had two uses which were independent:
- When operating as a TCPC, it indicated that the VBUS level should be
tracked (through GPIO inputs) and sent to the external TCPM when
appropriate.
- When operating as a TCPM, it indicated that the VBUS level should be
obtained by querying the TCPC.
These two independent uses have been split into
CONFIG_USB_PD_TCPC_TRACK_VBUS and CONFIG_USB_PD_VBUS_DETECT_TCPC, which
sould be more clear.
In addition, CONFIG_USB_PD_VBUS_DETECT_* CONFIGs have been added for
other means of VBUS detection.
BUG=chromium:616580
BRANCH=None
TEST=Verify kevin continues to boot + charge.
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: I936821481d6577e17e3e9c61ff97c037574d6923
Reviewed-on: https://chromium-review.googlesource.com/348950
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
move PRECHARGE_TIMEOUT to config.h so that we can customize precharge time to
meet client's spec.
BUG=none
BRANCH=master
TEST=`make -j buildall`, precharge time is set to 300s in elm.
Change-Id: I5c3bf0d5c5240b9c087e6cdb7c6e97301efa9f84
Signed-off-by: Ryan Zhang <Ryan.Zhang@quantatw.com>
Reviewed-on: https://chromium-review.googlesource.com/348151
Reviewed-by: Shawn N <shawnn@chromium.org>
Add tests for RSA-1024, and created partner CRBUG/53893
to track issue discovered with 1024-bit modinv.
1024-bit RSA support being added in preparation
for a forthcoming hardware based implementation.
BRANCH=none
BUG=chrome-os-partner:43025,chrome-os-partner:47524,chrome-os-partner:53893
TEST=all tests in test/tpm_test/tpmtest.py pass
Change-Id: I6b5aaeffc9df1cbbe403535fd21cdd377b42c38e
Signed-off-by: nagendra modadugu <ngm@google.com>
Reviewed-on: https://chromium-review.googlesource.com/348490
Commit-Ready: Nagendra Modadugu <ngm@google.com>
Tested-by: Nagendra Modadugu <ngm@google.com>
Reviewed-by: Nagendra Modadugu <ngm@google.com>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Port SHA and P256 code to depend on third_party/cryptoc.
Remove config options CONFIG_SHA1, and CONFIG_SHA256 as
these are provided by third_party/cryptoc.
Also remove unused config options CONFIG_SHA384, CONFIG_SHA512.
Crypto functions prefixed by dcrypto_ (declared in internal.h ),
DCRYPTO_ (declared in dcrypto.h) are implemented under
chip/g/dcrypto, and otherwise are implemented under third_party/cryptoc.
BRANCH=none
BUG=chrome-os-partner:43025,chrome-os-partner:47524,chrome-os-partner:53782
TEST=all tests in test/tpm_test/tpmtest.py pass
Change-Id: If7da02849aba9703573559370af5fae721d594fc
Signed-off-by: nagendra modadugu <ngm@google.com>
Reviewed-on: https://chromium-review.googlesource.com/340853
Commit-Ready: Nagendra Modadugu <ngm@google.com>
Tested-by: Nagendra Modadugu <ngm@google.com>
Reviewed-by: Nagendra Modadugu <ngm@google.com>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
GPIO_USB_C0_VBUS_WAKE_L is used to show VBUS status on elm.
If VBUS is present, pd sends soft reset on boot.
So it can boot without battery.
BUG=chrome-os-partner:53496
BRANCH=none
TEST=test on elm.
Remove battery and boot up successfully only with AC.
Use "sysjump rw" command and ec won't reboot by pd hard reset.
Change-Id: I1cdb12894c7b6bc41d7a16802b8c0ef14e2aa426
Signed-off-by: YH Huang <yh.huang@mediatek.com>
Reviewed-on: https://chromium-review.googlesource.com/346261
Tested-by: Koro Chen <koro.chen@mediatek.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
It is important to be able to wipe out the non-volatile memory for
various reasons. This patch adds this ability for both when NV memory
is kept in SRAM and in flash.
Also a minor clean up to eliminate some code duplication and to have
normal flow messages printed out with time stamps.
BRANCH=none
BUG=chrome-os-partner:44745
TEST=just makeall at this time.
Change-Id: I59c1909669aeaa9e8ffb3d8ef81b02fa0facb6ab
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/348291
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
This change enables configs for:
CONFIG_USB_SERIALNO: a programmable serial number for servo_v4
CONFIG_CMD_GPIO_EXTENDED: ability to change GPIO functions on the command line.
BUG=chromium:571476
BRANCH=None
TEST=serialno set abcdef; serialno load; reboot; gpioget/gpioset
Change-Id: I0e871d256e41022d3bb9985e590864a6c4cdf6a4
Signed-off-by: Nick Sanders <nsanders@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/348391
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Initialize the charge suppliers after change manager is initialized,
otherwise charge supplier current & voltage values will be overwritten
to -1 by the charge manager ini function.
BUG=chrome-os-partner:53788
BRANCH=None
TEST=Observed there are no "CL: p(port) s(supplier) i-1 v-1" prints
on the EC console.
Change-Id: Id0212c502d5833c016ac79ee15d21304d6d7ceb2
Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/347896
Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
This moves PP5000 and PP3300 enable early into board_init() and
increases priority of board_init() so that it runs before any TCPC
or PD init hooks which communicate with the TCPCs via I2C.
This hack also makes it so we don't shut off PP3300 for the time
being, at least until we get the proper sequence down and can avoid
I2C errors.
This probably is not the permanent solution, but for now it prevents
a lot of I2C errors from occurring.
BUG=chrome-os-partner:53549
BRANCH=none
TEST=booted on reef, no longer see I2C wedge error messages
Change-Id: I87e2e99aa3e1152cd10a2bfdd749d6e0dbd981a8
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/346633
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Kevin K Wong <kevin.k.wong@intel.com>
Move power rail and pmic enable control to be handled at
board level due to specific board design.
Modify rsmrst where assertion is pass-through at all time
and de-assertion is only pass-through at power up.
BUG=chrome-os-partner:53666
BRANCH=none
TEST=amenia is able to handle apreset warm/cold, pmic shutdown,
soc reset/shutdown.
Change-Id: I7ff819d88d0e194073bee8f02b1e3fa70ca44ba7
Signed-off-by: Kevin K Wong <kevin.k.wong@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/347370
Commit-Ready: David Hendricks <dhendrix@chromium.org>
Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Tested-by: David Hendricks <dhendrix@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Divya Jyothi <divya.jyothi@intel.com>
When the AP or EC is off, the RX line is low. Holding the UART RX line
low causes an interrupt storm. This change disables the UART TX and RX
on the peripheral when the device is powered off so the interrupts wont
be triggered.
BUG=chrome-os-partner:53514,b:28885578
BRANCH=none
TEST=run taskinfo on cr50 and make sure the IRQ count for 181 is a
reasonable number.
Change-Id: I42c779253860a2b1dd27ab41fb7097c887cc23ff
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/347355
Use the power and servo connection states to enable and disable the
EC and AP UART output. Contention between the cr50 and servo
can prevent either uart from working, and possibly damage kevin or
servo. If both UARTs are enabled, then cr50 cant know if servo is
connected, so it is best if the UARTs are disabled before connecting
servo.
If servo is connected or if a device is not powered on then the UART
output wont be enabled. The two UARTs are enabled separately and one can
be enabled without the other. Any disabled UART will be monitored for a
servo connection. If servo is detected, then all UARTs will be disabled.
BUG=chrome-os-partner:52056,chrome-os-partner:52322
BRANCH=none
TEST=manual
Power on the EC only. Check only the EC UART is enabled.
Without disabling the uarts power on the AP and verify both are
now enabled.
Turn of the AP. run 'uart enable. Verify only the EC UART is
enabled. Then attach servo and check that the AP and EC UART
are disabled.
Change-Id: Ife27c9360e91b07f86ff8bfcec7f4fd423c31d25
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/342828
There are a couple of issues that cr50 has when it cannot know the state
of servo, the EC, and the AP. This change adds support so we can detect
when the AP or EC has been powered on and when servo has been connected.
It uses the UART RX signals to monitor the power state of the AP and EC.
The TX signals are used to monitor the state of servo.
BUG=chrome-os-partner:52056,chrome-os-partner:52322
BRANCH=none
TEST=verify device states are correct when the AP and EC are powered on
or off and when Servo is attached or detached
Change-Id: Id0a2281b65cb367ecc8d0ca2f9a576672318a5fb
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/344019
Used #define CONFIG_FLASH_NVMEM to have functions in
/board/tpm2/NVMem.c utlitize on chip Nvmem functions.
On chip NV Memory availability is tied to an internal nvmem
error state which itself only depends on finding at least one
valid partition.
Added nvmem_is_different and nvmem_move functions which were
needed to complete the tpm2 platform interface. In addition,
added unit tests to support these two new functions.
BUG=chrome-os-partner:44745
BRANCH=none
TEST=manual
make runtests TEST_LIST_HOST=nvmem and verify that all tests pass.
Tested with tcg_test utility to test reads/writes using the
command "build/test-tpm2/install/bin/compliance --ntpm
localhost:9883 --select CPCTPM_TC2_3_33_07_01".
Change-Id: I475fdd1331e28ede00f9b674c7bee1536fa9ea48
Signed-off-by: Scott <scollyer@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/346236
Commit-Ready: Scott Collyer <scollyer@chromium.org>
Tested-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
Enabled CONFIG_FLASH_NVMEM and its associated configs. Added
user definitions along with buffer lengths. Added board
specific functions for sha computation and getting user
buffer lengths required by the NvMem module.
This CL does not include calls from cr50/board/tpm2/NVMem.c.
Those calls will be modified in a subsequent CL.
BUG=chrome-os-partner:44745
BRANCH=none
TEST=manual
The only call to any NvMem functions is nvmem_init().
Loaded code and verified via console that it boots
up properly. Also executed 'make runtests', but
that really only tests regression and not the new
board specific changes.
Change-Id: Iddc8d05703707247d26a8f22dca3ac9cc3c6ad1e
Signed-off-by: Scott <scollyer@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/345633
Commit-Ready: Scott Collyer <scollyer@chromium.org>
Tested-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
This change provides a console command for setting,
and loading a usb serial number from flash. This
feature adds CONFIG_USB_SERIALNO, and currently only
has a useful implementation when PSTATE is present.
BUG=chromium:571477
TEST=serialno set abcdef; serialno load; reboot
BRANCH=none
Change-Id: I3b24cfa2d52d54118bc3fd54b276e3d95412d245
Signed-off-by: Nick Sanders <nsanders@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/337359
Reviewed-by: Randall Spangler <rspangler@chromium.org>
The counter used for prime generation should be
incremented after each success / failure. Not doing
so results in duplicate primes being picked when
a label is explicitly specified.
BRANCH=none
BUG=chrome-os-partner:43025,chrome-os-partner:47524
TEST=all tests in test/tpm_test/tpmtest.py pass
Change-Id: Ib2fd0e7fa6255b04946e6d2808e8c67a2199fb55
Signed-off-by: nagendra modadugu <ngm@google.com>
Reviewed-on: https://chromium-review.googlesource.com/346056
Commit-Ready: Nagendra Modadugu <ngm@google.com>
Tested-by: Nagendra Modadugu <ngm@google.com>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
These must be initialized in order for charge_manager to select a port +
input current limit.
BUG=chrome-os-partner:53578
BRANCH=None
TEST=Attach 5V USB-C charger on Reef, verify "New chg" print is seen
along with "CL: p0 s1 i3000 v5000]" print.
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: Ia6139d9e9c6acd17ac587b32280f11927741672d
Reviewed-on: https://chromium-review.googlesource.com/347043
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: David Hendricks <dhendrix@chromium.org>
The gpio settings for the USB_PD_RST_ODL signal had the default
state high while the power enable, EN_USB_TCPC_PWR, was low. This
is combination of settings is invalid for the part. Therefore,
keep USB_PD_RST_ODL low until board_set_tcpc_power_mode() is called
to bring the pd chip online.
BUG=chrome-os-partner:53035
BRANCH=None
TEST=Rachel confirmed things still working.
Change-Id: I8b6b54a474c00165a4d0af944fb60f2923b9ef5c
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/347000
Reviewed-by: Shawn N <shawnn@chromium.org>
The USB_C0_PD_INT signal is actually at 3.3V levels. Don't mark
the voltage sensitivity to 1.8V.
BUG=chrome-os-partner:53035
BRANCH=None
TEST=Rachel ran with resulting image. Nothing bad observed.
Change-Id: I36bc3f911b715dc967cc8f23dfc70c3d0e5023d2
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/346734
Reviewed-by: Shawn N <shawnn@chromium.org>
board_reset_pd_mcu() was provided to ensure a microcontroller USB PD
implmenetation was reset. However, performing this sequence without
coordinating with the analogix driver results in a mismatch of
expectations regarding the internal polarity. The driver already
sets the expected interrupt polarity, but performing this reset
in chipset_pre_init() changes the expected setting which results
in occasional power sequence state machine hangs since
tcpc_get_alert_status() was always returning true. Lastly, added
comment to board_reset_pd_mcu() indicating how that sequence is likely
not needed if it's only invoked in the EC reset path.
Getting the analogix chip out of reset works in conjunction with the
default gpio settings for USB_PD_RST_ODL as well as the implementation
of board_set_tcpc_power_mode().
BUG=chrome-os-partner:53035
BRANCH=None
TEST=Rachel tested with change. Consistent power sequencing completes
without any hangs.
Change-Id: I9ffabaf85f33d6a361caef631e3e6d86c4cf8081
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/346733
Reviewed-by: Shawn N <shawnn@chromium.org>
updated the following based on amenia 1.2 hardware change:
gpio change
invert kbd col 2
g782 temp sensor
adc ch0, 2 reading
kx022 base accel
lid gyro/accel/mag i2c port change
bd99955 charger
bc1.2 support (CL:341030)
tcpc support (CL:341535)
BUG=none
BRANCH=none
TEST=make buildall
Change-Id: I178baf326c8edd8e0dadac6a6480625177d90a09
Signed-off-by: Kevin K Wong <kevin.k.wong@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/341534
Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
Enabled CONFIG_CMD_RTC_ALARM. EC_HOST_EVENT_RTC
is enabled when the rtc_alarm goes off,
alerting the AP to transition from S3->S0.
BUG=chrome-os-partner:52218
BRANCH=None
TEST=rtc_alarm <num> and see event set in ec console
after <num> seconds. Also, check if new bit set
through hostevent command in ec before/after
rtc_alarm goes off.
Change-Id: I53b1705ce0925000f35b9f80752035d198db3310
Signed-off-by: Shelley Chen <shchen@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/345474
Reviewed-by: Shawn N <shawnn@chromium.org>
This adds the basic framework for Reef including full GPIO listing,
board config file, and rudimentary functionality. It has not been
fully tested and still has several TODOs/FIXMEs. For now we just need
something that will build and can be incrementally improved.
BUG=chrome-os-partner:53035
BRANCH=none
TEST=EC and AP both boot, seems reasonably stable for now
Change-Id: I4934ad00917e251dd1d7eb759207a92c45a36136
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/339292
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
LPC access interrupt only enabled when EC entering deep doze mode. This
will reduce interrupt of LPC access. Also, this interrupt is always
enabled for LPC platform to support "CONFIG_LOW_POWER_S0".
Signed-off-by: Dino Li <dino.li@ite.com.tw>
BRANCH=none
BUG=none
TEST=Tested ectool command 'version' x 10000.
Change-Id: I9053c4018b38a8a852c3c6254e1fcde625f3fa3a
Reviewed-on: https://chromium-review.googlesource.com/336112
Commit-Ready: Dino Li <dino0303@gmail.com>
Tested-by: Dino Li <dino0303@gmail.com>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Update battery parameters to match the batteries actually present on
these devices.
BUG=chrome-os-partner:53002
BRANCH=None
TEST=Manual on kevin. Verify battery successfully charges and discharges
from AC.
Change-Id: I84579c23fe9fec1aecf133887a2d5b880047772f
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/344935
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
The EC code expects console commands to be no longer than 14
characters, otherwise the alignment of the help command output breaks.
This patch replaces flash_spi_sel_lock with flash_spi_lock and
fake_disconnect with fakedisconnect to make sure the command names
fit.
BRANCH=none
BUG=none
TEST=the 'help' command output is not misaligned any more
Change-Id: Ia65f1535850a07adccbef0812c8a0922c0264cea
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/345570
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Mulin Chao <mlchao@nuvoton.com>
Some axes of base and lid accelerometers on EVT needs to be reversed
to match the standard reference frame.
BUG=chrome-os-partner:52776
BRANCH=none
TEST=accelinfo on and check the lidangle reported is correct when I am
changing the lid angle
Change-Id: Id340d28a740d00c7ff4508f5f804fe90fd8ba18c
Signed-off-by: Koro Chen <koro.chen@mediatek.com>
Signed-off-by: Ricky Liang <jcliang@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/343490
