This will be used as part of case closed debugging configuration.
Currently, this only adds the state machine, and a test command which
is available when CR50_DEV=1. It also adds a new sleep mask flag for
physical presence detect, instead of oveloading FORCE_NO_DSLEEP.
The physical presence state machine supports both short (tap 5 times
in 15 seconds) and long (short, followed by 4 more taps 1-5 minutes
apart) sequences. It will call a callback function at the end of the
sequence, so that multiple things can each request physical presence
in turn. This will be used by ccdopen / ccdunlock / testlab commands
for CCD V1.
Eventually, CCD config will replace the unlock sequence handling in
wp.c. But for now, we don't touch that.
See go/cr50-ccd-wp for more information.
BUG=b:62537474
BRANCH=none
TEST=manual
Short sequence:
pp short
pp
pp
pp # See "Physical presence good"
Timeout
pp short
pp # 15 sec later, get timeout error
Long sequence:
pp long
pp
pp
pp
(wait 2 sec)
pp
(wait 2 sec)
pp # See "PP good"
Long sequence, presses too fast:
pp long
pp
pp
pp
pp # See "PP L too soon"
(wait 2 sec)
pp
(wait 2 sec)
pp # See "Physical presence good"
Abort:
pp short
pp abort # See "Physical presence aborted"
Change-Id: I09da81ad11d328e7d7740c3fe838a5f67d7b8708
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/568796
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
This commit adds support for the virtual wire signals over eSPI.
Additionally, the SLP_S0_L signal is added for the board and some minor
changes are made to some GPIOs.
BUG=None
BRANCH=None
TEST=flash zoombini image on npcx7 EVB with some modifications. Verify
no panics or asserts are hit.
Change-Id: I6ada270b3e3fc7e24b28a8da6ee9dcde707414fc
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/577054
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
Instead of having to pass in both the board and the arch used there
(which might be complicated in the light of different ECs with different
arches), allow passing in the board and a set of cross compilers.
The core/*/build.mk then pick the compiler that is responsible for them.
The current method works just the same: If you've already set
CROSS_COMPILE, no override happens. If you set neither CROSS_COMPILE nor
CROSS_COMPILE_$arch, the same default as before this CL is set.
BUG=none
BRANCH=none
TEST=emerge-{samus,kevin} chromeos-ec behave reasonably with adapted
ebuild
Change-Id: Icf1866f296412dd92ecfe134394224c49f7c3df5
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://chromium-review.googlesource.com/549344
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Stefan Reinauer <reinauer@google.com>
RCIN# signal is known to not work properly for performing a warm reset
when the CPU is in a bad state. This results in the common key combo
(Alt-Volup-r) not working to reset the host. Thus, use SYS_RESET
signal instead to trigger both cold and warm chipset reset.
BUG=chromium:721853
BRANCH=None
TEST=make -j buildall
Change-Id: I38663db96767d0aa03cd1aea0fe2a0cc5b771cd2
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/575947
Reviewed-by: Duncan Laurie <dlaurie@google.com>
In deep S3, SLP_SUS# goes low which results in power to base being
cut. For such cases, PMIC needs to be configured so that it keeps the
power to base up. Use VREN register to keep PP5000_A rail enabled in
deep S3.
BUG=b:63251418
BRANCH=None
TEST=make -j buildall. Verified that wake from base works in deep S3.
Change-Id: Ice3ba56f1a7e52275c3afa332c29b5b252dded4d
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/574619
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
We need to add __keep to the USB descriptors, otherwise they
get thrown away.
Also, for some reason the optimized RWSIG task uses a little bit
more stack space, so account for that:
1 RWSIG 00000000 0.264350 1096/2048
BRANCH=none
BUG=b:63610290
TEST=make BOARD=hammer -j
make newsizes
build/hammer/RO/ec.RO.flat shrank by 2052 bytes: (37336 to 35284)
build/hammer/RW/ec.RW.flat shrank by 3172 bytes: (50508 to 47336)
Flash hammer, touchpad, keyboard, update all still work fine.
Change-Id: I39ffd320dae883596ce481efc4adec6e3c23000b
Reviewed-on: https://chromium-review.googlesource.com/567909
Commit-Ready: Nicolas Boichat <drinkcat@chromium.org>
Tested-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
With the bd99954 charger we do not need to discharge when full,
so remove this config option and the setting of 94% for "full"
battery.
Note that this only affects the battery reporting state, the
EVT systems (board <= 4) will still discharge when full (in order
to prevent the charger noise) but they will now indicate that they
are discharging in this state instead of appearing full.
Newer boards (version > 4) will behave as expected.
This is a compile time option so it isn't something I can easily
support old boards with, but I think it is more important to do
the right thing for new boards.
BUG=b:35585628
BRANCH=eve
TEST=test charge behavior when full on board version 6
Change-Id: I3dd46ae305107b17b3bf8e3ce71578d3400b0f79
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://chromium-review.googlesource.com/573091
Reviewed-by: Shawn N <shawnn@chromium.org>
Eve does not use PECI so disable it and remove from the resulting binary.
BUG=b:35581264
BRANCH=eve
TEST=build EC for Eve and ensure peci module is not included
Change-Id: Ie87d789226b2b5f2162ea96cb001a5cb62359213
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://chromium-review.googlesource.com/573083
Reviewed-by: Shawn N <shawnn@chromium.org>
This CL adds CHIP_VARIANT_NPCX7M6G to support another npcx7 ec SKU.
Please note that the default setting in npcx7_evb is npcx7m6f.
For the EVB using the 128-pins EC package, please change CHIP_VARIANT
from npcx7m6f to npcx7m6g in build.mk.
BRANCH=none
BUG=none
TEST=No build errors for make buildall; Set CHIP_VARIANT=npcx7m6g in
board/npcx7_evb/build.mk; Build the image and test on EVB.
Change-Id: I2f857e4f6524eab45930bac3cc209409d4a53ee8
Signed-off-by: CHLin <CHLIN56@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/569320
Commit-Ready: Jun Lin <riverq@gmail.com>
Tested-by: Jun Lin <riverq@gmail.com>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Mulin Chao <mlchao@nuvoton.com>
Current LED color changes are abrupt. This CL adds a new function
which steps from one color (some RGB combo) to another gradually. When
the new or old color is white, then precomputed steps computed from
HSI space are used. Other transisions involving either just red/green
use linear steps computed dynamially based on the total change.
This CL also creates a new task for the LED code so that the color
transitions won't hold off other hook tasks for too long a period of
time. Changed the LED tick time to be 500 msec as it's no longer tied
to the hook tick.
BUG=b:35584895
BRANCH=eve
TEST=Using EC console command 'battfake', changed reported battery
charge level and verified that the LED patterns still work as
expected. In addition, had debug code which printed to the console
what the R, G, B duty cycle levels were for each transition and
verified the expected values were achieved. Visually compared version
with transitions to the previous version which changed abruptly.
Change-Id: I4e7c19556db9ed6037f2afa05cf348d19aeb18bb
Signed-off-by: Scott Collyer <scollyer@google.com>
Reviewed-on: https://chromium-review.googlesource.com/562543
Commit-Ready: Scott Collyer <scollyer@chromium.org>
Tested-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
In particular, highlight more clearly cr50/common code differences,
describe update over USB state machine, and common code commands.
Also, replace all cr50/CR50 instances with Cr50.
BRANCH=none
BUG=b:36375666
TEST=~/chromium/src/tools/md_browser/md_browser.py -d docs
Change-Id: I45e26a87c3455e1c67be186b403b1d4c4acade91
Reviewed-on: https://chromium-review.googlesource.com/558537
Commit-Ready: Nicolas Boichat <drinkcat@chromium.org>
Tested-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Problem was detected while using ccprintf to debug a data role swap
requests issue. To prevent errors similar to this, surround the API call
as follows:
ifndef VIF_BUILD
ccprints("I won't generate an undefined reference when building genvif");
endif
BUG=b:63664511
BRANCH=None
TEST=`make -j buildall`
Change-Id: Ieab9eaa638320cae67995a67c843d08b54acfbcb
Signed-off-by: Sam Hurst <shurst@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/570820
Commit-Ready: Sam Hurst <shurst@google.com>
Tested-by: Sam Hurst <shurst@google.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
This patch clears RESET_FLAG_AP_OFF on recovery boot so that the
system boots immediately regardless of the previous power state.
BUG=b:63669512
BRANCH=none
TEST=Verify the followings on reworked Fizz:
1. Press RB and PB in S0: FAIL(*1)/PASS
2. Press RB and PB in S5: FAIL(*1)/PASS
3. Unplug AC in S0 then press RB and plug in AC: PASS/PASS
4. Unplug AC in S5 then press RB and plug in AC: PASS/PASS
(*1: b:63668669)
Change-Id: If300fc9ec28ff0f7833e84a02e174e501b6a5016
Reviewed-on: https://chromium-review.googlesource.com/570948
Commit-Ready: Daisuke Nojiri <dnojiri@chromium.org>
Tested-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This change makes EC run vboot in the HOOK task. The vboot routine
requires battery and charger info. It waits in a deferred call
loop until the charge manager is initialized.
BUG=b:63586051
BRANCH=none
TEST=Verify the following cases:
A. Hardware reboot (type-c/BJ)
1. Unplug AC in S0 then plug in AC: BOOT/BOOT
2. Unplug AC in S5 then plug in AC: S5/S5
3. Unplug AC after A.2 then plug in AC: S5/S5
4. Press PB in S5: BOOT/BOOT
B. Software reboot (type-c/BJ)
1. Run EC reboot command in S0: BOOT/BOOT
2. Run EC reboot command in S5: BOOT/BOOT
3. Run EC reboot ap-off command in S0: S5/S5
4. Run EC reboot ap-off command in S5: S5/S5
5. Run host reboot command: BOOT/BOOT
6. Run host shutdown command: S5/S5
C. Recovery tests
1. Press RB and PB in S0: FAIL(*1)/PASS
2. Press RB and PB in S5: FAIL(*1)/PASS(*2)
3. Unplug AC in S0 then press RB and plug in AC: PASS/PASS
4. Unplug AC in S5 then press RB and plug in AC: PASS(*2)/PASS(*2)
*1: b:63668669
*2: b:63669512. Requires one more PB press.
Change-Id: I28f37fdad7f83d0d44570b9003e8c6a4b83b832f
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/568699
Reviewed-by: Randall Spangler <rspangler@chromium.org>
1. Fix a issue that user can't use type-c adapter and type-c device at
the same time. ex. Plug in adapter in port1 and then plug in device in
port2. Port1 will stop charge.
2. Update the vbus status when AC change to correct the charge source.
3. We use the typc adapter with capacity 5V/3A, 9V/3A, 15V/3A,
20V/2.25A. Add PD_PREFER_HIGH_VOLTAGE define to request voltage to 20V.
BRANCH=None
BUG=None
TEST=Plug in type-c adapter and device to test
Signed-off-by: Cloud Lin <cloud_lin@compal.com>
Change-Id: I1927008a13651b8fa137d8d1a5000efd7db2e79f
Reviewed-on: https://chromium-review.googlesource.com/485380
Commit-Ready: Lin Cloud <cloud_lin@compal.com>
Tested-by: Lin Cloud <cloud_lin@compal.com>
Reviewed-by: Martin Roth <martinroth@chromium.org>
This patch moves the code which can be shared with other data
verification schemes (e.g. RWSIG) under common/vboot. It also
adds unit tests for it.
BUG=b:38462249
BRANCH=none
TEST=make run-vboot. Verify verification succeeds on Fizz.
Change-Id: Icab4d96dd2c154a12b01c41ebe9b46286b4b590e
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/563463
Reviewed-by: Randall Spangler <rspangler@chromium.org>
This patch gives EC the capability of verifying and jumping to
RW_A or RW_B. EC tries the slot stored in a persistent storage
(e.g. BBRAM). If verification fails due to invalid contents, EC
tries the other slot. AP's expectation and its reaction to the
state of the slots and the currently running image are summarized
below.
Since the system is still unlocked (CONFIG_SYSTEM_UNLOCKED), EC
won't try to verify or jump to RW yet.
| AP expects X
----------+---------------------------
SLOT_A=X | proceed
SLOT_B=X | proceed
----------+---------------------------
SLOT_A=X' | reboot to B
SLOT_B=X | proceed
----------+---------------------------
SLOT_A=X | proceed
SLOT_B=X' | reboot to A
----------+---------------------------
SLOT_A=X' | write X to B, reboot to B
SLOT_B=X' | write X to A, reboot to A
BUG=b:38462249
BRANCH=none
TEST=Lock the system and boot Fizz on barrel-jack and type-c.
Change-Id: I51e3abd4d9af44ab3d531561cb9bfa2e8d775f6a
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/556286
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reduce maximum frequency of BMM150 compass to 80Hz, 800Hz is a typo.
Reduce SI1141 maximum frequency to 50Hz: 100Hz is too high when polling
mode is used.
Fix up of CL:482703
BRANCH=eve, glados
BUG=chromium:615059
TEST=On eve, check CTS test
android.hardware.cts.SensorBatchingTests#testMagneticField_fastest_flush
passes. Observed that dumpsys sensorservice returns compass maxRate at
80Hz instead of 200Hz.
Change-Id: If4e688ab59aa53c402d34714b6bb33ccd4a4ab96
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/570482
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
The Simplo_a50 battery had voltage_max = 8750 mV, which is not correct
and it should be 8800. Since the voltage_max parameter is used with
-0.5% margin, the 8750 mV value resulted in a charger setting of 8704
and does not provide enough of a voltage delta between the charger and
the battery to fully charge packs that exceed the design capacity.
In addition, had the tables for both battery types reviewed by the HW
team and updated some of the temperature parameters.
BUG=b:62483321
BRANCH=eve
TEST=Tested with a dogood unit that was failing to reach 100% charge
and showing very long "time to full" values as the battery charge
approached 90%. After adjusting the voltage_max param, tested and
verified that the battery reached 100% charge. In addition, verified
the bd9995x 0x1A register had the correct voltage setting.
Change-Id: I40e7bc111b048986e824fcb7843e57433a1def84
Signed-off-by: Scott Collyer <scollyer@google.com>
Reviewed-on: https://chromium-review.googlesource.com/570380
Commit-Ready: Scott Collyer <scollyer@chromium.org>
Tested-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
This commit increases the precision used in the noisy magnitude
deviation check by multiplying the scaled sensor data by 8 in the
intermediate calculations. Prior to this, due to some bits being lost,
certain devices would determine the lid angle as unreliable in specific
angles, even though the device was at rest.
BUG=b:63148973
BRANCH=eve,gru,reef
TEST=Flash bob, set DUT on desk, run `while true; do ectool motionsense
lid_angle; sleep 0.1; done`, slowly move the lid from 15 degrees until
~350. Verify that no particular angle results in a unreliable lid angle
reading.
TEST=Run `evtest` and examing cros-ec-buttons, fold screen all the way
back to make tablet mode, shake device for at least 30s. Verify that
there are no spurious transitions of the tablet mode switch.
TEST=Repeat above tests on kevin.
Change-Id: Iff06c1df2dd33c60e26a59183f62f29b71548729
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/567050
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
This CL adds support for updating FW to the internal spi flash in
npcx ec by enabling gang programmer mode. We also added a new array,
BOARDS_NPCX_INT_SPI, to indicate which boards will update FW through
this mechanism. The preliminary of testing is listed below.
Step 1: Connect npcx7 evb and servo v2 with following pins.
NPCX796F Servo V2
-----------------------------------------
GP_SEL# --> (Pin 7, J7) FW_UP#
VCC1_RST#--> (Pin 4, J7) DUT_COLD_RESET#
GP_CS# --> (Pin 1, J11) DUT_SPI1_CS
GP_SCLK --> (Pin 2, J11) DUT_SPI1_CLK
GP_MISO --> (Pin 5, J11) DUT_SPI1_DO
GP_MOSI --> (Pin 6, J11) DUT_SPI1_DI
-----------------------------------------
Step 2: Npcx ec is powered up by PPDUT_SPI1_VREF (Pin 8, J11).
Step 3: Add external PU on FW_UP#.
Step 4: Execute "sudo servod --vendor 0x18d1 --product 0x5002".
BRANCH=none
BUG=none
TEST=Move npcx7_evb from BOARDS_NPCX_7M6X_JTAG to
BOARDS_NPCX_INT_SPI. Prepare two different ec images.
Use following script "while :; do ./util/flash_ec
--board=npcx7_evb --image=../ec1.bin; sleep 1; ./util/flash_ec
--board=npcx7_evb --image=../ec2.bin; sleep 1; done" to test
gang programmer mode. No errors occur over 2 hours.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Change-Id: Ie813bf0191c06bb6e30a5e0dccb824f9f79ada53
Reviewed-on: https://chromium-review.googlesource.com/564742
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
This patch defines load addresses of regions using macros to increase
readability.
BUG=none
BRANCH=none
TEST=Diff firmware_image.lds before and after the change.
Change-Id: I24a13f4676b194efb748522f03c3134d1568f5ae
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/566940
Reviewed-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
When usb_udpater reads board ID information from a binary blob, in
case the ID field can be represented as a 4 character ASCII string the
updater transposes the characters, resulting in a reversed string
printed.
Fix the transposition to verify that the result is printed properly.
BRANCH=none
BUG=b:63597142
TEST=ran the following commands:
$ make BOARD=cr50
$ CR50_BOARD_ID='TEST:ff00:ff00' H1_DEVIDS='0x0169c181 0x04656742' \
./util/signer/bs
$ ./extra/usb_updater/usb_updater -b build/cr50/ec.bin
read 524288(0x80000) bytes from build/cr50/ec.bin
RO_A:4919.0.0 RW_A:0.0.21[TEST:0000ff00:0000ff00] RO_B:-1.-1.-1 ...
Change-Id: I852cf9505d6b8b9e7133ca1008be1b22081a9d88
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/567681
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
The `brdprop` command simply returned board_properties, however,
board_properties is just a cache of the properties from init time. When
the `brdprop` command was issued, it would only return the cached value.
This commit changes the functionality of the `brdprop` command to always
query the LONG_LIFE_SCRATCH1 register.
BUG=b:63456150
BRANCH=cr50
TEST=Flash bob. Unplug and plug in battery, verify that
BOARD_WP_ASSERTED is set when running the `brdprop` command.
Change-Id: I0a7feb5e63f3e528b554ed0820924ac0705f5517
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/566240
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
The LED pattern for lowest battery level is supposed to indicate that
there isn't enough battery present to boot the AP. The pattern_tbl
array had this value set to 2. However, it's better to tie this to the
constant defined in board.h so that it's consistent with when the AP
will be allowed to boot. In addition, adjusted the battery level
ranges to work correctly with the <= check.
BUG=b:35584895
BRANCH=eve
TEST=Used 'battfake' console command to verify that the patterns
changed at the expected battery charge levels.
Change-Id: Ie85a448ad4803be7e612c382b8e60fa42356d257
Signed-off-by: Scott Collyer <scollyer@google.com>
Reviewed-on: https://chromium-review.googlesource.com/562542
Commit-Ready: Scott Collyer <scollyer@chromium.org>
Tested-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Todd Broch <tbroch@chromium.org>
This commit adds support for the PS8805, another Parade Tech TCPC with
integrated superspeed muxes. This also creates a generic Parade Tech
TCPC driver which supports the PS8xxx series.
The current supported TCPCs are:
- PS8751
- PS8805
BUG=b:63508740
BRANCH=None
TEST=`make -j buildall`
Change-Id: I78383af414996e0e8d6220985d286f95267136f8
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/564799
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
There needs to be a way to set a board ID fields in the Cr50 RW
header. This patch adds this capability to the board signer and
release image creator scripts.
create_released_image.sh is being modified to include chrome OS
command line option parsing bash library, and a new command line
parameter is defined, --cr50_board_id. Its value is a string of three
colon separated fields, <board id>:<board id mask>:<board id flags>,
where
<board id> is a 4 character ASCII string, the RLZ board code
<board id mask> and <board id flags> are two hex values, without
preceding 0x.
This value is passed to the bs script through environment variable
CR50_BOARD_ID (to be in sync with the bs script taking already
optional parameters like H1_DEVIDS from the environment).
The bs script is slightly refactored, code modifying the manifest to
splice in the device ID nodes is put into a function, and code adding
the board ID nodes to the manifest is also included in the new
function.
The three fields of the CR50_BOARD_ID string are converted to integers
and added to three nodes in the manifest (board_id, board_id_mask, and
board_id_flags respectively).
BRANCH=none
BUG=b:62294740
TEST=created a released image image using
create_released_image.sh --cr50_board_id RXXX:ffffff00:ff00 \
<rest of parameters>
using the modified usb_updater (under a different patch) verified
that the header fields have been created as expected.
Change-Id: I8374024de347f341ac16b72c2fa4a774e8385466
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/562918
Reviewed-by: Randall Spangler <rspangler@chromium.org>
This clean up is based on the review of a branch cherry-pick patch
(https://chromium-review.googlesource.com/c/556184).
Most of the comments apart from the suggestion of creating main() and
'workforce'() have been addressed.
BRANCH=cr50
BUG=b:62294740
TEST=verified that images created by running
H1_DEVIDS='xxx xxx' ./util/signer/bs elves elf.1 elf.2
H1_DEVIDS='xxx xxx' ./util/signer/bs
are still bootable on a Cr50.
Change-Id: I370526be060e11b8c640d35b1409a631233b0672
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/557997
Reviewed-by: Randall Spangler <rspangler@chromium.org>
This patch adds code to interpret the contents of the Cr50 image's RW
headers board ID fields.
Board ID fields are added to the RW and RW_B version strings, as a
three field colon separated value.
The actual board ID is likely to be a 4 symbol ASCII string, if it
is, the 4 ASCII characters are displayed. If it is not - the 8
character hex value is printed. The rest of the fields are displayed
as 8 characters hex values.
BRANCH=none
BUG=b:62294740
TEST=tried the new option on various Cr50 images:
$ ./extra/usb_updater/usb_updater -b build/cr50/ec.bin
read 524288(0x80000) bytes from build/cr50/ec.bin
RO_A:4919.0.0 RW_A:0.0.21[00000000:00000000:00000000] ...
$ ./extra/usb_updater/usb_updater -b cr50.bin.dev
read 524288(0x80000) bytes from cr50.bin.dev
RO_A:0.0.10 RW_A:0.0.21[XXXR:00000004:00000001]...
Change-Id: I5a92a600d24e4a7d6d615f256b5979414e883d77
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/562919
Reviewed-by: Randall Spangler <rspangler@chromium.org>
STM32 I2C frequency can be computed as such:
tSCL = tSYNC1 + tSYNC2 + { [(SCLH+1) + (SCLL+1)] x
(PRESC+1) x tI2CCLK }
The default values we use come from the datasheet, which assume,
for 400 kHz setting, that tSYNC1 + tSYNC2 = 750 ns, and therefore
set tSCLH as 500 ns and tSCLL as 1250ns.
On hammer, we measured a total tSCL of ~2150 ns (465 kHz) with
these settings, so we can easily slow it down to ~2500 ns (400 kHz)
by increasing tSCLH to 750 ns (SCLH = 0x5).
As highlighted in 48b2edf031
"stm32f0/i2c: adjust the 100kHz setting to never go above 100kHz"
this has the disadvantage of slowing down other boards where
the RC value on the I2C bus are different, but slowing down should
always be safe, and is the best we can do without adding config
defines for the fall/rise time.
BRANCH=none
BUG=b:36172041
TEST=Flash hammer, measure SCL frequency to be about 400 kHz
Change-Id: Ia2cac9fb09228abd8a318d57335855be529485c2
Signed-off-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/563219
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Running lsusb (to get iSerial) and openocd requires a privilege.
This patch makes cts.py run these commands as a root. Opening
ttyACM0 requires a privilege as well but it'll be done by asking
a user to add themselves to dialout group.
BUG=chromium:664309
BRANCH=none
TEST=Run cts.py on a freshly set up cros_sdk chroot.
Change-Id: Ib9d007459c4b1322b15f521a5253d833e2304c3c
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/558804
Reviewed-by: Randall Spangler <rspangler@chromium.org>
For hammer, we do not want to require finalization in factory, so
we just protect RO whenever WP GPIO is set.
BRANCH=none
BUG=b:63378217
TEST=Enable CONFIG_FLASH_PSTATE_LOCKED, flash hammer,
check with flashinfo that RO protection matches WP status.
Change-Id: I902ee478c00a3c932277d2a7d0622c070654a5eb
Reviewed-on: https://chromium-review.googlesource.com/563217
Commit-Ready: Nicolas Boichat <drinkcat@chromium.org>
Tested-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
GPO32 is "PU [30K] during reset, then Hi-Z", so change to GPIO27
avoiding USB-C (P0) LED shortly light up during EC reset.
BRANCH=none
BUG=b:63048710
TEST=Rework poppy board by wiring EC_CHG_LED_Y_C0 to TP38
Change-Id: I91e3dd58849ce15f9a85408aec94fd3f94acf038
Reviewed-on: https://chromium-review.googlesource.com/558785
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
Tested-by: Tony Lin <tonycwlin@google.com>
Commit-Queue: Nicolas Boichat <drinkcat@chromium.org>
