When charge manager safe mode is enabled, it prevents us from selecting
CHARGE_PORT_NONE if we have a battery which is disconnected/cutoff. The
cutoff reporting code was essentially making the assumption that if AC
is not present, then we must be running off of battery power. However,
AC presence is debounced and can take some time to be reported to the
system. Therefore, we may wrongly assume that we are running off of
battery power and cut off our AC power source.
This commit simply removes that assumption and still consults the
battery regarding the cutoff/disconnect state.
BUG=b:74125001
BRANCH=stabilize-meowth-10444.B
TEST=flash meowth; cutoff battery, insert AC, verify system comes up.
Verify that CHARGE_PORT_NONE is not selected until battery wakes up.
Change-Id: I79a27bd2d5f09c2ffe65df98402c0ae0182fdba2
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/957888
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
The TCPC of the left USB-C port is being swapped with Anx7447. This
patch temporarily disables the port so that the boot is not inhibited
by running a wrong driver on the port.
BUG=b:73793947
BRANCH=none
TEST=Boot Nami with/without battery. Verify it can be charged through
the right port.
Change-Id: I30b63f87cb3669c38a04e908b6556eef1424fbd7
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/957814
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
In practice, ADC conversion rarely takes more than 35ms.
However, according to the datasheet, ADC conversion may take
up to 200ms. But we can't wait for that long, otherwise
host command would time out. So here we set ADC timeout as
50ms. If ADC times out, we just return the last read vbus_mv.
BUG=b:70641844, chromium:780364
BRANCH=scarlet
TEST=test 'ectool usbpdpower' for 50k cycles
w/o seeing host command timeout
Change-Id: I09c3abf729e96b113f7a0f64a67cd35906da9e3e
Signed-off-by: Philip Chen <philipchen@google.com>
Reviewed-on: https://chromium-review.googlesource.com/956900
Commit-Ready: Philip Chen <philipchen@chromium.org>
Tested-by: Philip Chen <philipchen@chromium.org>
Reviewed-by: Alexandru M Stan <amstan@chromium.org>
Reviewed-by: Brian Norris <briannorris@chromium.org>
yorp measures each port's vbus separately on a deticated ADC.
Also, add config to take care of ADV_VBUS -1 case too.
BRANCH=none
BUG=b:74127309
TEST=none
Change-Id: I6f4df96caffc3b527b69e67358631dd448172cde
Signed-off-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/956555
Reviewed-by: Edward Hill <ecgh@chromium.org>
To prevent invalid timestamping, call load_fifo only when we get a FIFO
interrupt.
In consequence, remove load_fifo entry point and only process fifo
inside the IRQ.
Add helper function to know when we are in forced mode (the EC needs to
periodically read sensor data or interrupt driven).
BUG=b:73557414
BRANCH=master
TEST=compile
Change-Id: I959e476f3f7215be95424c07223f7421e8b13da1
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/938146
Commit-Ready: Alexandru M Stan <amstan@chromium.org>
Tested-by: Alexandru M Stan <amstan@chromium.org>
Reviewed-by: Alexandru M Stan <amstan@chromium.org>
Set the sensor side fifo watermark to interrupt the EC as soon as
there's any data in there, that way we get more frequent accelerometer
interrupts (which is handy when you want to mark down the time of each
sample accuratelly).
BUG=b:67743747
TEST=Sensor should still be working normally, the ec will probably start
recieving sensor interrupts (before this was probably not the case).
BRANCH=master
Change-Id: I726550e68447a74bbfed88b703d2f68b6967ac93
Signed-off-by: Alexandru M Stan <amstan@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/956626
Commit-Ready: Gwendal Grignou <gwendal@chromium.org>
Tested-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-by: Gwendal Grignou <gwendal@chromium.org>
The exact behaviour still needs to be optimized based on actual
power consumption (for example, it might be worth providing power
to base without charging it, or charge it a bit more, then let
it slowly discharge).
BRANCH=none
BUG=b:71881017
BUG=b:74414928
TEST=Low base battery, check that lid provides power to it in S0 or
suspend.
TEST=Check that lid stops providing power in S5.
Change-Id: Idf198ab1b4358827f9db6c0898234b6e2be45808
Signed-off-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/956982
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
When the base battery is low, we need to provide it with some power,
to make sure the battery does not fully deplete.
Instead of relying on a separate configuration value, we simply
reuse min_base_system_power. Also, we fix a bug that incorrectly
used a power value as current.
BRANCH=none
BUG=b:71881017
BUG=b:74414928
TEST=With a critically low wand (3%), lux is able to provide
enough power to charge wand battery a little (44mA), even
when backlight is fully on, and touchpad is in use.
Change-Id: I3174ac273712eeb83ce1283dda3d786ad503e6f3
Signed-off-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/956661
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
If the I2C port is completely broken then there is no point in trying to
continue with the transaction. This can happen if the pull-ups on the bus
are not working because they are in a power domain which is not currently
enabled.
Check the return value from i2c_unwedge() and return if it doesn't work.
Tidy up a few comments at the same time.
BUG=b:72129419
BRANCH=none
TEST=manually remove the check AP being off in sb_tsi_get_val() and see
that it quickly fails now, rather than hanging the EC for a while trying
the transaction.
Change-Id: I66ab52943459726537dfc74355f8aeaa5817dba5
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/956017
Reviewed-by: Edward Hill <ecgh@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@google.com>
Without this patch, requesting 100mA or output current would be
rounded down to zero.
This would also cause other issues when doing base/lid and lid/base
power transfers on lux/wand, as the input current has a much finer
grain control, which could lead the input charger to brown out
the output charger.
BRANCH=none
BUG=b:67920792
TEST=Flash lux/wand, lux can provide as little as 100mA of current
successfully.
Change-Id: Ibf170a6ee3c2dfbdbbc03948c3b0e6ab878eee47
Signed-off-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/956660
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
If wand ever reaches low enough battery level (<3%), it should
hibernate, instead of cutting off the battery, as the latter will
disable all the switches, and lead lux to redetect the base.
BRANCH=none
BUG=b:74414928
TEST=Discharge wand as much as possible, then put lux in S0ix (no
power transfer currently), discharge wand further (using
pwm 0 100 to activate backlight to draw a bit more power),
see that wand goes into hibernate.
Change-Id: I9edb517aada7d21fbcddbce4ad06ab7fbcafce38
Signed-off-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/956659
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Since we only enable power to the base in the charger task (we
can't enable power before OTG/power allocation is setup properly),
there is a potential race when we quickly plug/unplug the base.
Fix this by only allowing the enable power when the detection
code knows that the base is actually connected.
BRANCH=none
BUG=b:74403503
TEST=Plug/unplug wand several times with charger attached,
PPVAR_VAR_BASE is always 0 whenever the base is disconnected.
Change-Id: I96da9ed39ddbbbe7aea54ad96c62fde6115538c0
Signed-off-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/956204
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
At present issuing several 'waitms 1000' commands immediately after each
other trips the watchdog. Add a watchdog reload to avoid this.
Also document the behaviour in the command help.
BUG=b:72542719
BRANCH=none
TEST=manually on grunt, pasting these three lines in:
waitms 1000
waitms 1000
waitms 1000
and see that it does not reset now.
Change-Id: I453708299e4e26c1bbdb5fc406f26e916e7389af
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/955927
Reviewed-by: Edward Hill <ecgh@chromium.org>
Reviewed-by: Martin Roth <martinroth@chromium.org>
The port_address field is used in the driver. Also making array
declaration consistent with other parts of the file.
BRANCH=none
BUG=none
TEST=none
Change-Id: I43c72182c6afefbdbb7286918326b7ea6f92c7d7
Signed-off-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/955940
Reviewed-by: Edward Hill <ecgh@chromium.org>
list/add_activities should be include even when FIFO support is not
compiled it, when the host is not asking for them, as it is needed for
double tap support.
BUG=b:73546254
BRANCH=master
TEST=Compile when just CONFIG_GESTURE_DETECTION is defined.
Change-Id: Icec7ccec7fd8463ea40afbe05ce1e177ae7d609d
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/924404
Commit-Ready: Gwendal Grignou <gwendal@google.com>
Tested-by: Gwendal Grignou <gwendal@google.com>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Gwendal Grignou <gwendal@google.com>
Add support for generating the authcode from cr50's challenge.
BUG=b:74019846
BRANCH=none
TEST=create a cr50 image with test keys. Verify that the output from
rma_reset -c opens cr50.
Change-Id: I85a209e55dc23daa118e0071e868878b6fbfcb69
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/945419
Reviewed-by: Randall Spangler <rspangler@chromium.org>
To enable USB charging on boards where fusb302 takes care of VBUS detection
BUG=b:65446459
BRANCH=none
TEST=on Scarlet rev3, verify VBUS supplier is updated based on
whether VBUS is present - plug/unplug USB2 charger, boot with USB2
charger plugged.
Change-Id: I50177d40b0eb0490634ad2f103306e0079633fbe
Signed-off-by: Philip Chen <philipchen@google.com>
Reviewed-on: https://chromium-review.googlesource.com/905401
Commit-Ready: Philip Chen <philipchen@chromium.org>
Tested-by: Philip Chen <philipchen@chromium.org>
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
Add support for setting the battery to discharge even if AC is
present. Used for factory testing.
BRANCH=none
BUG=b:74096137
TEST=ectool chargecontrol discharge, ectool battery
Change-Id: I79e6bfabcfc0327e5c12c789decc27591911a6ee
Signed-off-by: Edward Hill <ecgh@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/954283
Reviewed-by: Cheng-Han Yang <chenghan@chromium.org>
Reviewed-by: Jett Rink <jettrink@chromium.org>
Ensure that the short parameter '-p' works as well as the long one
'--progressbar'.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=none
BUG=none
TEST=run 'stm32mon -p' and 'stm32mon --progress' none of them are
displaying the command usage.
Change-Id: If24accf0991dc9705a1fb3e29acf12581d7ab8dc
Reviewed-on: https://chromium-review.googlesource.com/952966
Commit-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Nicolas Norvez <norvez@chromium.org>
Some boards have forgotten to undef CONFIG_PECI but it is benign. This
should be an opt-in feature instead of an opt-out feature. No one is
using it, so no one will opt-in.
BRANCH=none
BUG=none
TEST=Verified that grunt, kahlee, meowth, and zoombini are not using the
PECI bus for Soc temperature via schematics (GPIO81). Other boards are a
no-op. See cl:951407 for steps taken to ensure all npcx boards were
accounted for.
Change-Id: I6ca4b9d22b7cb23c9842729658810ebe165ff6cc
Signed-off-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/951408
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Currently cbi-util accepts only fixed length values. This patch makes
it automatically calculate the required field size to accomodate the
given integer value.
The stored values are expanded to uint32_t when they're read.
BUG=b:74174598,b:70702820
BRANCH=none
TEST=Run cbi-util with --sku_id set to the followings:
0x10 -> field size = 1,
0x1000 -> field size = 2,
0x10000 -> field size = 4,
0x100000000 -> Error
Change-Id: I2221ebfa18260bae2c574d9ebb794dbe645579e5
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/951711
Reviewed-by: Randall Spangler <rspangler@chromium.org>
When the EC sends back an error code inside the 'result' field of the v3
protocol, the transport is supposed to return -EECRESULT-error_code.
Fix the the servo spi transport to do so.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=none
BUG=b:72360575
TEST=with ZerbleBarn connected to a Servo v2, run 'ectool_servo fpinfo'
and 'ectool_servo fptemplate badfile.bin'
Change-Id: I54eec9194cfefd422078344500685736aadaffcf
Reviewed-on: https://chromium-review.googlesource.com/951682
Commit-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
This patch splits struct fan_t into two parts: base configuration
and RPM configuration. RPMs are expected to be different from
model to model while a base configuration is most likely shared.
BUG=b:73720175
BRANCH=none
TEST=make buildall
Change-Id: Iff17573f110e07e88d097dd848cf91ee98b83176
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/949382
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
The CONFIG_UART_HOST is supposed to be defined to the index of the UART we
want to use. It is not supposed to be defined as a boolean. Updated npcx
and all incorrect uses.
BRANCH=none
BUG=none
TEST=Added the following diff to ensure that everything still built:
diff --git a/chip/npcx/lpc.c b/chip/npcx/lpc.c
index 446baa842..826233744 100644
--- a/chip/npcx/lpc.c
+++ b/chip/npcx/lpc.c
@@ -897,6 +897,9 @@ static void lpc_init(void)
/* Initialize Hardware for UART Host */
#ifdef CONFIG_UART_HOST
+#if !CONFIG_UART_HOST
+#error "Fix me"
+#endif
/* Init COMx LPC UART */
/* FMCLK have to using 50MHz */
NPCX_DEVALT(0xB) = 0xFF;
Change-Id: Ia46c7cb86c6040a5c75dddf23d5ccd8e33210581
Signed-off-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/949308
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Remove the former special case for USB RAM
Add additional RAM regions for STM32H7.
For USB RAM, add an explicit alignment directive to ensure we always meet
the 8-byte boundary hardware constraint for the BTABLE.
This was already true because we put the .usb_ram.btable section first.
I keep this property by alpha-sorting the sections but makes it more
explicit by adding a 2-digit numeric prefix: e.g. 00_firstsection,
99_lastsection.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=none
BUG=b:67081508
TEST=on ZerbleBarn, along with the following CLs, run the firmware with
large arrays in special AHB memory regions.
TEST=build all targets with and without the patch and verify that all
smap files are identical.
Change-Id: I9ee7f519a13cb14ba9997220f22180028f9c0175
Reviewed-on: https://chromium-review.googlesource.com/946369
Commit-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
When a chip has special/non-contiguous SRAM physical memory region,
rather than extending the generic linker file ad nauseam, define a
mechanism to declare a chip specific list of those regions.
To do so, a chip must declare the CONFIG_CHIP_MEMORY_REGIONS
configuration and have a memory_regions.inc with the list of regions.
The special-purpose preprocessed chip/<chip_name>/memory_regions.inc
file has one region declaration per line using the following macro:
REGION(name, attributes, start_address, size)
Each region will get a proper MEMORY entry and a section in the linker
file.
the __SECTION(region_name) helper is provided as a convenience to
declare variable in a specific region.
Note: those 'special' regions are NOT cleared at startup contrary to
.bss.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=none
BUG=b:67081508
TEST=on ZerbleBarn, along with the following CLs, run the firmware with
large arrays in special AHB memory regions.
Change-Id: I3f156ef6e5feb4a6a0b2ae2468bae8a20483f17c
Reviewed-on: https://chromium-review.googlesource.com/946368
Commit-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Make it clearer what the new key is about.
CONFIG_KEYBOARD_NEW_KEY to CONFIG_KEYBOARD_ASSISTANT_KEY.
BRANCH=none
BUG=none
TEST=make buildall -j
Change-Id: Ic2db425b40ff8bc612626b6f644463b1f8ec630e
Signed-off-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/950263
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Cr50 lacks native instructions for 64-bit integers and an ABI
function can be used by the compiler to take the place of the
needed instructions. This CL adds support for a right bitwise
shift of 64-bit integers.
BRANCH=none
BUG=chromium:794010
TEST=Set CONFIG_LLSR_TEST, build, update cr50, and run llsrtest
on the console.
Change-Id: Iae66c86720c531454ba29f15b3cc6a07959f5ef2
Signed-off-by: Allen Webb <allenwebb@google.com>
Reviewed-on: https://chromium-review.googlesource.com/931932
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
There's a new pin being added for board versions. Additionally, the
endianness is different than what was implemented.
BUG=b:73260349
BRANCH=stabilize-meowth-10444.B
TEST=Flash meowth; verify board version is as expected.
Change-Id: I97fb66f6c6aaf20d0ea4ed5994301490234ab812
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/949054
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
BRANCH=none
BUG=b:73528930
BUG=b:73660652
TEST=Flash lux, check that lux adc VBUS voltage when only no
charger is connected is around 12V.
Change-Id: Iccc245c96ca3c83674446f96f78f1ce15ffa7de2
Signed-off-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/948322
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Add a new module ID 'MODULE_FAST_CPU'.
When it is enabled with clock_enable_module(MODULE_FAST_CPU, 1), switch
the system clocking to the fast 400-Mhz PLL.
For now, I consider that a single task/user is calling
clock_enable_module(MODULE_FAST_CPU, x), so we don't need to count users
(in a complicated atomic fashion). It's good enough for the current
use-case and we can add the complexity later if we have a real need.
BRANCH=none
BUG=b:67081508
TEST=on ZerbleBarn, with follow-up CL setting
clock_enable_module(MODULE_FAST_CPU,x) around the computation block,
see that computations are fast and the clock goes back to HSI after.
Change-Id: I2aef3ad673ddbffd6fc64c591c54297e94896fa6
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/945688
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
Set the PLL frequency to 400 Mhz (max value) and the AHB frequency to
200 Mhz.
Fix the PLL clocking code for STM32H7 :
- fix the frequency computation.
- adjust the timer divider depending on the system clock.
- the 64Mhz HSI is already setup properly at startup, takes it into
account.
- set the SPI ports on the fixed 64-Mhz HSI, so clocking changes don't
mess up their frequencies or stability.
Note: this is just modifying the CPU frequency when the system is
clocked by the PLL, by default the system is still clocked by the 64-Mhz
HSI. Currently, one have to use the 'clock pll' console command to test
this PLL mode, some code will be added soon to switch on-demand for
heavy computations.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=none
BUG=b:67081508, b:72879097
TEST=On ZerbleBarn, do 'clock pll', check 'gettime' against wall clock,
run image capture and enrollment.
TEST=on ZerbleBarn, verify on the scope that the SPI master frequency is
4 Mhz in both configuration.
Change-Id: I92a2216999337cf9831fb5dfc2797ab1cce71a8f
Reviewed-on: https://chromium-review.googlesource.com/941226
Commit-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
1. Enable fan feature and update fan setting.
2. Enable SW and chipset throttle feature.
3. Fix the issue that cannot set fan duty by "fanduty" in EC console.
BUG=b:72974136
BRANCH=none
TEST=Check fan command(fanduty/fanset/fanauto) in EC console can work and
check below condition.
1.AP throttling soft
--> Increased temperature to over trigger point, then to check
EC notify event in EC console.
2.AP throttling hard
--> Increased temperature to over trigger point, then to check
EC notify event and CPU_PROCHOT pin status in EC console.
3.Fan controlled in s3/s5 as expected (by EC)
--> Check Fan turn off in s3/s5.
4.Fan controlled in S0 as expected (by DPTF)
--> Check Fan keep 100% duty and no see DPTF to set fan duty.
But fan duty can be control by "fanduty" in EC console.
Change-Id: If9fd7f64c123ff54742052b6310023f0d4b0113a
Signed-off-by: raymondchou <raymond_chou@compal.corp-partner.google.com>
Reviewed-on: https://chromium-review.googlesource.com/906086
Commit-Ready: Raymond Chou <raymond_chou@compal.corp-partner.google.com>
Tested-by: Raymond Chou <raymond_chou@compal.corp-partner.google.com>
Reviewed-by: Raymond Chou <raymond_chou@compal.corp-partner.google.com>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
NPCX7 requires that the HW_WIRE bits 2-0 of VWEVSM2 register are set
so that the hardwire signals for SCI, SMI and RCIN are connected to VW
input of eSPI_SIF module. NPCX5 did this by default, however NPCX7 has
made it configurable.
NPCX7 however sets the HW_WIRE bits 2-0 to 1 at reset. So, this change
ensures that they are preserved while initializing VWEVSM2 registers
BUG=b:74111394
BRANCH=None
TEST=Verified that SCI works on glkrvp and meowth with NPCX7.
Change-Id: I9da6f45b4aa0b72b68db6192cb7567f09b072f0c
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://chromium-review.googlesource.com/943801
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Divya S Sasidharan <divya.s.sasidharan@intel.com>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: ML Chao <mlchao@nuvoton.corp-partner.google.com>
Reviewed-by: Jett Rink <jettrink@chromium.org>
