This allows us to use the two SPI ports as SPI master. Also, to save CPU
time on reading large amount of data, let's add an async interface for
SPI transaction.
BUG=chrome-os-partner:29805
TEST=Read manufacturer ID from SPI flash with sync/async interface
BRANCH=None
Change-Id: I427f4215602cccc55c4151f4116226b1e0ccc15e
Signed-off-by: Vic Yang <victoryang@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/204719
Previously each board.h and board.c contained an enum and an array
for gpio definitons that had to be manually kept in sync, with no
compiler assistance other than that their lengths matched.
This change adds a single gpio.inc file that declares all gpio's
that a board uses and is used as an X-macro include file to
generate both the gpio_signal enum and the gpio_list array.
Signed-off-by: Anton Staaf <robotboy@chromium.org>
BRANCH=none
TEST=make buildall -j
Change-Id: If9c9feca968619a59ff9f20701359bcb9374e4da
Reviewed-on: https://chromium-review.googlesource.com/205354
Tested-by: Anton Staaf <robotboy@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Commit-Queue: Anton Staaf <robotboy@chromium.org>
ectool must support all prior versions of commands that shipped
EC binaries use.
BUG=chrome-os-partner:29830
BRANCH=None
TEST=Manual
With an EC that only supports version 0:
- Run 'ectool batterycutoff' -> success
- Run 'ectool batterycutoff at-shutdown' -> error with explicit
message about at-shutdown not being supported
- Run 'ectool batterycutoff foo' -> error, bad parameter
With an EC that support version 0 or 1:
- Run 'ectool batterycutoff' -> success
- Run 'ectool batterycutoff at-shutdown' -> success
- Run 'ectool batterycutoff foo' -> error, bad parameter
Change-Id: Ia88cfc5fa7c5125828ec0595f0b6a505916c97ea
Signed-off-by: Dave Parker <dparker@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/205155
Reviewed-by: Vic Yang <victoryang@chromium.org>
As per the new spec, use the fast OCP to protect against the
short-circuits by putting the threshold at 4.5A.
Set the slow OCP (a few dozen milliseconds latency) at 3.6A to limit the
accepted current range.
Also sample the current/voltage over a larger period (5us) to limit
noise issues.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=none
BUG=chrome-os-partner:28331
TEST=plug Zinger on an electronic load and trigger the OCP with various
pulses.
Change-Id: Ia66cd186716aebf88646cbf5fd340388f8cdd48d
Reviewed-on: https://chromium-review.googlesource.com/204590
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Todd Broch <tbroch@chromium.org>
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
This implements the DMA driver using the same DMA interface we are using
now.
BUG=chrome-os-partner:29805
TEST=Along with the following SPI driver, read manufacturer ID from SPI
flash.
BRANCH=None
Change-Id: Ife3c0c8b414568ff1cab7d072901ba2d11142a17
Signed-off-by: Vic Yang <victoryang@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/205067
Reviewed-by: Randall Spangler <rspangler@chromium.org>
This is a temporary hack to allow PD MCU to negotiate for 20V before
EC tells it that the battery is present. This is currently necessary
because at 5V, we don't have enough power to boot the AP, and we can't
wait to boot the AP until we negotiate because the zinger tends to
get stuck in an infinite reboot loop when the AP is off.
Note that this will need to be removed when we implement PD software
sync because the whole point of that is to not talk to outside world
until we verify our code.
BUG=chrome-os-partner:29840
BRANCH=none
TEST=Tested on samus 2A and 2B boards, made sure system could boot
with and without battery.
Change-Id: I03f319bf81b4e90758132e774848dff5542f4ce5
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/205144
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
This changes the input current limit to 2048mA with no ramp up.
Problem is that the bq24773 is doing a really poor job of measuring
input current, so even though the zinger side can support 3A, the
samus side can cause over currents down to 2300mA. This is set
consertavily to avoid over current errors and will need to be
updated when the hardware allows.
BUG=chrome-os-partner:24461
BRANCH=none
TEST=Used bench top power supply to power multiple samus 2A proto
boards and gathered data on max current samus was drawing based on
input current setting. Samus was often underestimating current by
300-700mA.
Change-Id: Iabeb0d026f2b72a9ee539d92579ee6d11aeaa56b
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/205143
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Increase the stack size for the charger task to work around I2C
battery communication issues.
BUG=chrome-os-partner:29839
BRANCH=None
TEST=watch for I2C0 transation failures and ensure that the charger
task does not stack overflow and reset the EC+system.
Change-Id: Iabae3e2c302b68eb9e25a604dd72ef48128866df
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/205142
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
It would be really nice to be guaranteed to see watchdog warnings
before we actually hit a watchdog reset even if something strange is
going on with the CPU. Let's increase the margin between the timer
and the independent so that the hardware watchdog is really hit as a
last resort.
It seems like a 1.6 second hardware watchdog wouldn't be the end of
the world so let's bump that way rather than increasing the number of
warnings.
BRANCH=ToT
BUG=chrome-os-partner:29162
TEST="waitms 1000" on EC console no longer ever reboots and "waitms
2000" usually does.
Change-Id: Ic5e5ddec22fb8484cc7c552b19d3f2043c105d0c
Signed-off-by: Doug Anderson <dianders@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/204895
Reviewed-by: Randall Spangler <rspangler@chromium.org>
The PP1800_PGOOD pullup resistor was no-stuff on P2B boards so
the input value is floating and cannot be relied on for proper
sequencing.
Before P2B it was always pulled up so it was not a useful signal
to wait on anyways.
BUG=chrome-os-partner:29502
BRANCH=None
TEST=buid and boot on samus proto2b
Change-Id: I29167d55bb0ef36683282946b912dd8cf5b405cf
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/205140
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Use the board version to implement both power sequence behaviors
in order to support both boards with one EC image.
The order of bits used to calculate board version was swapped so
update the GPIO table to reflect that.
BUG=chrome-os-partner:29502
BRANCH=None
TEST=build and boot on samus proto2a
Change-Id: Ib0f6010163af4b3bf9b39f64c26220aee43618ef
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/204869
Reviewed-by: Alec Berg <alecaberg@chromium.org>
On stm32 we were programming the WATCHDOG_HELP timer with the same
value as the independent watchdog (which automatically resets the
CPU). That means we weren't guaranteed to see the WATCHDOG_HELP. It
happened to work most of the time due to the the LSI oscillator fudge
(we assumed the watchdog was on a 56 kHz oscillator when it was
probably on a 38 kHz one), but let's give ourselves a guaranteed gap.
It's unlikely that this extra gap will actually help on most machines
(if we're running at 53 kHz or lower we already had this much margin),
but it's nice to be safe.
BRANCH=ToT
BUG=chrome-os-partner:29162
TEST=Increase margin to 400 (instead of 50) and type "waitms 300".
Sometimes hit watchdog warning.
Change-Id: I7f876757c15d7775116720c408a4127b4b94adfa
Signed-off-by: Doug Anderson <dianders@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/204894
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Fix bug and actually increase watchdog timeout to 1.8s.
BUG=none
BRANCH=none
TEST=put a 3 second blocking delay in pd_task and make
sure watchdog reboots. set blocking delay to 1.5seconds
and make sure no reboot.
Change-Id: Ie66621a3bd98354f9fd22b9b10a866d004277340
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/204471
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
On the P2 boards, the operational amplifier gain for current sensing is
exactly x100 rather than x101.
(non-inverter configuration with R1=1.8kOhm R2=178kOhm)
The voltage gain constant had a typo introducing a 10% error.
the voltage divider is 10k/100k,so it's x11 gain.
ie it should be written (10+100)/10 rather than (10+110).
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=none
BUG=chrome-os-partner:28331
TEST=make BOARD=zinger
checked manually with a voltmeter and traces.
Change-Id: I8097ab50149fee319efc11ebae75802e8a49a7f8
Reviewed-on: https://chromium-review.googlesource.com/204540
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Twinkie only has test points for uart connection so nominally it will
need to be programmed via DFU mode over USB micro-B connection.
This CL changes from programming via flash_stm32 function and instead
adds dfu support.
BUG=chrome-os-partner:28337
TEST=util/flash_ec --board=twinkie successfully programs twinkie f/w
Change-Id: Ia5433b569579bb879bd405e98921450764510a73
Reviewed-on: https://chromium-review.googlesource.com/204749
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Commit-Queue: Todd Broch <tbroch@chromium.org>
Tested-by: Todd Broch <tbroch@chromium.org>
In order to wake the chips from STOP/SLEEP mode with a touch, we need to
put the two chips in correct state before going into STOP/SLEEP mode.
Also, when one of the chips wakes up, it needs to wake the other chip
with GPIO interrupt.
This CL implements the necessary methods and also adds a sample routine
that put the chips in STOP mode and wait for a touch using the
implemented methods.
BUG=None
TEST=Build and boot. Touch the panel and see the response in console.
BRANCH=None
Change-Id: Ia5f7df8b550ee2459bcae1840f8a2717c8d947ce
Signed-off-by: Vic Yang <victoryang@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/204482
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
This adds back DECLARE_IRQ() support when building without common
runtime. With this, we can enable only a subset of IRQs and avoid
linking in other unused IRQ handlers.
Note that after this change, all boards without common runtime need to
have a ec.irqlist file.
BUG=None
TEST=Build Keyborg and check it still works.
TEST=make buildall
BRANCH=None
Change-Id: If68062a803b9a78f383027a1625cf99eb3370d3f
Signed-off-by: Vic Yang <victoryang@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/203264
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Enough USB support to be able to enumerate the device and use bulk or
interrupt endpoints.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=none
BUG=chrome-os-partner:28295
TEST=with the following USB console CL, connect a Fruitpie through USB
and use its console over USB.
Change-Id: I37b7f3b6a754cb82ab5f940ea20122d2e16b3b5b
Reviewed-on: https://chromium-review.googlesource.com/193983
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Todd Broch <tbroch@chromium.org>
Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
Increase watchdog timeout to 1.8 second. The pd_task can delay up
to 1.5 seconds, so the watchdog must be at least that value.
On Zinger, the new timeout period will be 2 seconds with LSI clock at 50kHz
and 3.36 seconds with LSI clock at 30kHz.
Note: the LSI frequency range is tighter on STM32F0 and cannot go up to
56kHz.
BUG=none
BRANCH=none
TEST=add 1.5 second blocking delay to pd_task and make sure
watchdog is normally not firing.
Change-Id: I444639ccacd3452181a5fb6caab8e5df7ef3c847
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/204333
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
We never implemented this. We have no devices which support it. And
we used bit #17 in a 16-bit field to flag it, so it wouldn't have
worked even if we did. So, remove this (dead) code.
BUG=chromium:382944
BRANCH=none
TEST=make -j buildall
Change-Id: Id3a4a93612d1078a3239d85921a05cfd7362b84c
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/204162
Reviewed-by: Doug Anderson <dianders@chromium.org>
Currently the master and the slave must synchronize before starting
slave response. This is to make sure the previous slave response is done
and the slave is ready for the next response. By enabling interrupt on
the master side to capture slave ready event, we can get rid of the
extra sync's. This saves about 1300 us per frame.
BUG=None
TEST=Build and boot. Measure time. Examine heat map.
BRANCH=None
Change-Id: I3c319d8a3636f1f6ae905d7021433c3ba220c9b0
Signed-off-by: Vic Yang <victoryang@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/203789
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
If at-shutdown is specified, the battery is cut off
1 seconds after the host has shutdown.
BUG=chrome-os-partner:29292,chrome-os-partner:28887
BRANCH=tot,nyan
TEST=Run batterycutoff ectool command and cutoff console
command with and without 'at-shutdown' option. Verify
the battery is cut off immediately without the option
specified and 1 seconds after shutdown with. View the
console log to see the deferred cutoff occur.
The following tests are verified on big.
console:
cutoff, AC on: system is off after removing AC.
cutoff, AC off: system is off immediately.
at-shutdown, AC on: system is off after "power off" and removing AC.
at-shutdown, AC off: system is off after "power off".
ectool:
batterycutoff, AC on: system is off after removing AC.
batterycutoff, AC off: system is off immediately.
at-shutdown, AC on: battery is cut off after 1s of shutdown.
system is off right after removing AC power.
at-shutdown, AC off: system is off after 1s of shutdown.
[84.058416 power state 3 = S0, in 0x0000]
[84.058803 power lost input; wanted 0x0001, got 0x0000]
[84.059120 power off 3]
[84.072148 Cutting off battery in 1 second(s)]
[84.123896 power shutdown complete]
[84.128790 power state 7 = S0->S3, in 0x0002]
[84.139694 power state 2 = S3, in 0x0002]
[84.150857 power state 8 = S3->S5, in 0x0002]
[84.166975 power state 1 = S5, in 0x0002]
[84.177972 power state 1 = S5, in 0x0002]
[85.080012 Battery cut off succeeded.]
Change-Id: Id4bacf79ad3add885260655f80cb8127bafe1ad6
Signed-off-by: Dave Parker <dparker@google.com>
Signed-off-by: Louis Yung-Chieh Lo <yjlou@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/203694
Reviewed-by: Vic Yang <victoryang@chromium.org>
- Wait for SLP_SUS to deassert before bringing up PP1050 to avoid
leakage when PP1050 is enabled before the PCH is ready.
- CPU PGOOD is now connected to RSMRST_L on PCH. Configure this
GPIO as an output and hook it into the power sequencing.
- Add a "chipset_force_g3()" function to use for aborting G3->S5
transitions when there is an issue with a rail not coming up.
BUG=chrome-os-partner:29502
BRANCH=samus
TEST=build for samus, tested on reworked p1.9 board
Change-Id: Ib0251943864594ee89a4a9f2c71c45da2c01f44e
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/203081
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Detect when VBUS is disconnected when acting as a sink and go to
the disconnected state.
BUG=none
BRANCH=none
TEST=Connect a zinger to fruitpie, run pd state from console to
verify it is in SNK_READY, then remove zinger and verify the state
changes to SNK_DISCONNECTED.
Change-Id: I0b46cfe3ac129f1ec9c11327c9e0d45c0c6761e8
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/203564
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
The timer on Keyborg is only of 32-bit width, so we should always use
get_time().le.lo instead of get_time().val to avoid unneeded 64-bit
integer operations. This saves about 0.66 us per call to
master_slave_sync(), which is called about 500 times per frame.
BUG=None
TEST=Measure the time used on master_slave_sync().
TEST=Boot and check touch scanning still works.
BRANCH=None
Change-Id: I6668cda3c6c00d1af971fc55fcc8d643b83a4578
Signed-off-by: Vic Yang <victoryang@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/203670
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
In order to make SPI CRC work, we had to ensure the master and the slave
agree on the size of slave response. This required us to first send the
response size and then send the full response. The downside of this is
that we cannot take full advantage of DMA.
Given the SPI bus is fast enough, let's add an option to always transfer
max size packet on slave response. This incurs some overhead as unused
bytes are also sent, but the overhead doesn't affect us when the slave
is busy with touch scanning. (The scanning time is longer than
transferring 64 bytes over SPI.) This situation may change in the
future, so make it a compile time option for now.
Also removed the use of RX channel on the slave side when the slave is
sending response. The RX channel is useless in this case.
BUG=None
TEST=Build and measure scan rate w/ and w/o
CONFIG_KEYBORG_SPI_FULL_PACKET flag.
BRANCH=None
Change-Id: I4b23b1d89903dd022b445eb81667679276858008
Signed-off-by: Vic Yang <victoryang@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/203660
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Added extra arg to typec console command to give the port number (0 or 1)
in order to set the muxes appropriately for both ports.
BUG=none
BRANCH=none
TEST=make -j buildall
Change-Id: I7abddb9f27c22082aed0fbf09a301ca2d5e7c5fc
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/203653
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Samus PD MCU board file changes for version 2 and 2B of the
samus board.
Adds more I/O for case closed debugging, adds sensing of
VBUS voltage (boostin), and moves USB C0 BC12 interrupt pin.
BUG=none
BRANCH=none
TEST=none
Change-Id: I545ff518add19919d1747de91318c33363d99403
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/203314
This slightly reduces binary size and increases scan rate when running
without fast scan.
BUG=None
TEST=Build and boot w/ and w/o fast scan.
BRANCH=None
Change-Id: I66683dce9c8f5e74f86764d8a4f33f4e1a161e08
Signed-off-by: Vic Yang <victoryang@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/203633
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
In case the slave got into a bad state, we may need a way to reboot the
slave from the master. The protocol must not involve SPI communication;
otherwise this will fail if the slave SPI module is in a bad state.
This CL implements this using SPI_NSS. In normal SPI communication, the
master pulls SPI_NSS low and immediately sync with the slave. To reboot
the slave, the master pulls SPI_NSS low without the following sync.
BUG=None
TEST=Reboots the slave from the master.
BRANCH=None
Change-Id: I947523e1d86fb2332b87fbfa3dab73cba958fb72
Signed-off-by: Vic Yang <victoryang@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/203485
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
It's often hard to find out which sync call failed when one happens.
Let's add debug info.
BUG=None
TEST=Add a sync call on master side only, and see the file name and line
number.
BRANCH=None
Change-Id: I68d0fa12d5d84293870e845fbb5f83aa3a8125fa
Signed-off-by: Vic Yang <victoryang@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/203339
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Previously an error in master-slave communication often leaves the chips
in bad states and thus prevents further operation. Improve this by:
- Making master_slave_sync() state-less.
- Restoring SPI_NSS and disabling DMA on error.
BUG=None
TEST=Inject errors on master side and slave side. Check the subsequent
operations succeed.
BRANCH=None
Change-Id: Ief8b5b0df3d4be6319957bb1f9daf93e0e9b5d92
Signed-off-by: Vic Yang <victoryang@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/203337
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Update according to the current PD standard, a monotonic transition
seems mandatory in all cases, so keep the voltage output enabled
when increasing the output voltage.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=none
BUG=chrome-os-partner:28331
TEST=connect Zinger to Fruitpie and probe the VBUS voltage during a
transition.
Change-Id: I3c728cc0049ca41536efd4f075139626b7d371da
Reviewed-on: https://chromium-review.googlesource.com/202657
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
If board.h or config_chip.h is included before config.h, CONFIG_* flags
may be incorrect. For example, if config.h says:
...
#define CONFIG_DEFINED_FLAG
...
#include "board.h"
...
And board.h says:
#ifndef __BOARD_H
#define __BOARD_H
...
#undef CONFIG_DEFINED_FLAG
...
#endif
Then this code:
#include "board.h"
#include "config.h"
would results in CONFIG_DEFINED_FLAG being defined, instead of undefined
as stated in board.h.
Avoid this by emitting error when board.h or config_chip.h is included
before config.h.
BUG=None
TEST=make buildall
BRANCH=None
Change-Id: Ic4a8b68e8ab1ef2a4cf9e926ab9008d2b106b943
Signed-off-by: Vic Yang <victoryang@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/203265
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Created a new smaller task size, 384, for tasks that don't need much
stack space including PDCMD and ALS tasks.
BUG=none
BRANCH=none
TEST=loaded on samus, ran taskinfo, made sure we were comfortbaly
under the smaller task size for those tasks that changed.
Change-Id: Icfa26eeaeed26171ec8b2d888e1190be32f688d1
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/202719
Reviewed-by: Randall Spangler <rspangler@chromium.org>
The fast scan buffer is of type 32-bit integer, so the byte size is 4
times of its size.
BUG=None
TEST=Check buffer is fully cleared after each frame
BRANCH=None
Change-Id: I0980e418a4b323195fec56f4970aca3918a6ee11
Signed-off-by: Vic Yang <victoryang@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/203205
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Increase the delay after receiving a good CRC in send_validate_message()
to avoid catching the last edge as the start of a new packet.
BUG=none
BRANCH=none
TEST=Tested with zinger and samus using the python script to flash
zinger RW, and simply negotiating power and receiving pings.
Change-Id: Iffdd73e02e5d292396d46a611d728f66402f2da4
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/203206
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Fix check for whether or not we are running in RO. The previous
code read the contents of the RW reset vector, but RW code
may be corrupted causing us to think we are in RW when we are not.
BUG=none
BRANCH=none
TEST=mostly just code inspection. verified this code running
in RW correctly identifies we are in RW.
Change-Id: I2c27af45a59b29f55fd24295f91d5c5f0e491dd4
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/203192
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Without common runtime, we need to use IRQ_HANDLER to define IRQ
handlers. Previously IRQ_HANDLER is only implemented in irq_handler.h
which is not included by task.h when building without common runtime.
This causes problem when we want to use code that includes task.h and
uses IRQ. By adding IRQ_HANDLER to task.h, we don't need to include
irq_handler.h in any case, and thus avoid that problem.
BUG=None
TEST=make buildall
TEST=include task.h instead of irq_handler.h. Check Keyborg still
builds.
BRANCH=None
Change-Id: I1213506132025fc656630565f58686b9e7de940c
Signed-off-by: Vic Yang <victoryang@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/203084
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Use a EC to PD host command to notify the PD MCU when a battery
is present and charged enough that it is ok to negotiate for a
higher power. The PD MCU will not negotiate until the host command
is received, which allows the system to be powered without a
battery or with a dead battery with 5V.
BUG=chrome-os-partner:28611
BRANCH=none
TEST=Tested on a samus:
1) Tested the normal case of battery charged and plugged in. When
charger is plugged in, the device immediately starts negotiating
for 20V and starts charging.
2) Tested with no battery. Plug in a charger, samus boots and stays
alive. VBUS measured at 5V. When a battery is plugged in, device
negotiates for 20V and starts charging.
3) Tested dead battery by taking a battery with no charge, and
plugging in zinger. Everything boots, but PD does not negotiate
for power. Then when battery reaches 1%, PD negotiates and zinger
switches to 20V without causing a reboot.
Change-Id: Iaa451403674e86cddbd3fe80e9503584910be576
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/201958
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
