The device-specific subclass used for Non-HC firmware updates is
in the spreadsheet now, so we can rename the macros to be
"official".
BUG=chrome-os-partner:49962
BRANCH=none
TEST=make buildall; test on cr50
make BOARD=cr50 (plus whatever signing magic works for you)
make -C extra/usb_updater
./extra/usb_updater/usb_updater build/cr50/ec.bin (sudo if needed)
Note that you may need to rebuild ec.bin in order to see any
difference after the update. If the A & B images are identical,
the RO bootloader always picks A.
Change-Id: I385ce89a9abe2059d52da2d82a0b92b9b3e3c93f
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/339220
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
On !LPC EC, we can read memory via CROS_EC_DEV_IOCXCMD ioctl,
using command EC_CMD_READ_MEMMAP.
On platform that supports direct memory access (lpc), we access
the memory directly, bypassing the ioctl.
BUG=chromium:602832
TEST=On gnawty and veyron, check 'ectool battery' works.
Verify that gnawty use io mapped registers.
BRANCH=none
Change-Id: I9bfcddcf450bf8df63ead78e1df97dd7392289e6
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/338853
Reviewed-by: Randall Spangler <rspangler@chromium.org>
PMIC already has a built-in 100ms delay for V1P05S when ALL_SYS_PWRGD
asserts, hence EC can assert SOC_PWROK immediately. On shutdown RSMRST_N
should assert and SOC_PWR_OK should de-assert immediately when PMIC asserts
PMIC_RSMRST_N and de-assert All_SYS_PWRGD respectively. Hence removed
the unnecessary timing delay for SOC_PWROK and RSMRST_N.
BUG=none
BRANCH=none
TEST=Issued a shutdown command and manually tested on amenia.
RSMRST_N asserts immediately when PMIC asserts PMIC_RSMRST_N
SOC_PWR_OK de-asserts immediately when PMIC de-asserts All_SYS_PWRGD.
Change-Id: I8bb79277a3dcf8545764ba58736f422ac377776e
Signed-off-by: Kevin K Wong <kevin.k.wong@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/339001
Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
Change the AP UART TX and RX gpios to match the schematic.
BUG=chrome-os-partner:50702
BRANCH=none
TEST=verify AP console output can be seen by cr50
Change-Id: I572bf2f664c276f094116e8a72400c9332bc10a7
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/338895
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
The TPM library serializes RSA keys in big-endian format, while
CR50 requires little-endian.
Handle endianness by converting from big to little and back
to big within the _cpri__* layer.
Also modify test code to make copies of static const RSA keys, as
these get placed on read-only memory.
BRANCH=none
BUG=chrome-os-partner:43025,chrome-os-partner:47524,chrome-os-partner:52337
TEST=tests in test/tpm/tpmtest.py pass
Change-Id: Id9cfbe8c99ecaeb02744fbc7554cd48a08bab819
Signed-off-by: nagendra modadugu <ngm@google.com>
Reviewed-on: https://chromium-review.googlesource.com/331740
Commit-Ready: Nagendra Modadugu <ngm@google.com>
Tested-by: Nagendra Modadugu <ngm@google.com>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
It is quite annoying to see an error reported by buildall, but not
knowing what board(s) actually failed to build.
Create file for each board being built, put build progress information
in it, and remove it if the board build succeeded. Then, once the
build is completed see the failed boards in .failedboards/, if any,
and the states they failed at.
BRANCH=none
BUG=none
TEST=verified that the directory is empty after a successful buildall
run, and has files named after failed boards in case of build
failures.
Change-Id: I67eb1671cadf58d9f8feccebfcc860524f33c2a0
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/338883
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
Implement warm reset and force shutdown routines, which are called from
other modules.
BUG=chrome-os-partner:51926, chrome-os-partner:51923
BRANCH=None
TEST=Verify 'apshutdown' on EC console goes to G3. Verify 'apreset'
causes AP reset while staying in S0.
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: Ifb479287f87f31ac49e007c337cc0c24a79898e6
Reviewed-on: https://chromium-review.googlesource.com/338923
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
Add support for SHA256 based HKDF key
derivation as specified in RFC 5869. This
change includes test vectors from the RFC.
BRANCH=none
BUG=chrome-os-partner:43025,chrome-os-partner:47524
TEST=tests under test/tpm2 pass
Change-Id: I7d0e4e92775b74c41643f45587fc08f56d8916aa
Signed-off-by: nagendra modadugu <ngm@google.com>
Reviewed-on: https://chromium-review.googlesource.com/336091
Commit-Ready: Nagendra Modadugu <ngm@google.com>
Tested-by: Nagendra Modadugu <ngm@google.com>
Reviewed-by: Marius Schilder <mschilder@chromium.org>
The TPM library serializes ECC parameters in big-endian format,
while CR50 requires little-endian.
Handle endianness by converting from big to little and back
to big within the _cpri__* layer.
Also modify test code to make copies of static const ECC keys, as
these get placed on read-only memory.
Rename a couple of instances of ec_ with ecc_ to avoid confusion.
BRANCH=none
BUG=chrome-os-partner:43025,chrome-os-partner:47524,chrome-os-partner:52337
TEST=tests in test/tpm/tpmtest.py pass
Change-Id: I607984f004820d5caa85ce13575b8ab501336479
Signed-off-by: nagendra modadugu <ngm@google.com>
Reviewed-on: https://chromium-review.googlesource.com/331673
Commit-Ready: Nagendra Modadugu <ngm@google.com>
Tested-by: Nagendra Modadugu <ngm@google.com>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Elm is an oak variant that uses ANX7688 PD port controller. This CL sets
PD port count to 1 and modifies TCPC I2C address to 0x50.
Other elm changes are included in this change:
- add 2 KX022 motion sensors, remove BMI160
- remove ALS
- LED configuration changed to 2 bi-color LEDs
- remove pi3usb30532
- add ANX7688 mux driver
- change PD interrupt polarity
BRANCH=none
BUG=none
TEST=manual
make BOARD=elm -j
load and test on elm proto
Signed-off-by: Rong Chang <rongchang@chromium.org>
Change-Id: I8ad02da9acade985bc0e7e2f85d9e58db7e6b38d
Reviewed-on: https://chromium-review.googlesource.com/331453
Reviewed-by: Shawn N <shawnn@chromium.org>
The new debug board presents itself as a yet another USB device, it
uses interface 1 for SPI.
Add it to the table of devices we try to use.
BRANCH=none
BUG=none
TEST=./test/tpm_test/tpm_test.py now succeeds again.
Change-Id: Id14f17de6eff081bebed49d22ddc4b19cd39c2b0
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/338862
Reviewed-by: Marius Schilder <mschilder@chromium.org>
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
This adds support for RD Detection on cr50. It can be used to detect a
debug device and signal the controller to switch from the AP PHY to the
to CCD PHY. When RDCC1 and 2 no longer detect the debug device, then
the controller switches back to using the USB to AP PHY.
BUG=chrome-os-partner:50700
BRANCH=none
TEST=change the value on RDCC1 and RDCC1 and check that the usb
controller connects to the right PHY.
Change-Id: Ice01a45a31fe1932945f89df2e3b851f4d287a17
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/338454
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
This change is required for support 'CONFIG_LOW_POWER_S0'.
Signed-off-by: Dino Li <dino.li@ite.com.tw>
BRANCH=none
BUG=none
TEST=1. fanset 5555, EC enter doze mode only and fan control is functional.
2. fanset 0, EC will enter deep doze mode properly.
Change-Id: I3780b12ef54713258769616bfed0155c865c0725
Reviewed-on: https://chromium-review.googlesource.com/338750
Commit-Ready: Dino Li <dino.li@ite.com.tw>
Tested-by: Dino Li <dino.li@ite.com.tw>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
In case of boot after battery is cut-off without this
change the battery is assumed to be present even though it
is not initialized and ready to provide power in try source
enable function. With this assumption charger is disconnected
momentarily which causes reboot.
Also make sure that try source enable is updated after battery
is ready by notifying hook call HOOK_BATTERY_SOC_CHANGE.
BUG=chrome-os-partner:51753
BRANCH=firmware-glados-7820.B
TEST=Enter battery cutoff command from EC console to enter into ship
mode and plug-in AC, verified no reboots happen.
Change-Id: I6f7656125717f85851f5ad4e37dfd953a52799c6
Signed-off-by: Divya Sasidharan <divya.s.sasidharan@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/335913
Reviewed-by: Shawn N <shawnn@chromium.org>
(cherry picked from commit 10040ac6284efe88b74193bdbb0c05ec92b563b4)
Reviewed-on: https://chromium-review.googlesource.com/336697
Commit-Ready: Divya S Sasidharan <divya.s.sasidharan@intel.com>
Tested-by: Divya Jyothi <divya.jyothi@intel.com>
In Pseudo G3 if both VBUS_EN & VCC_EN are disabled, on plugging the AC
on either of the ports, ACOK pin is not asserted because the charger
cannot detect the voltage on either of the ports. Hence the device cannot
boot until the power button is pressed.
Enable both the VBUS_EN & VCC_EN before entering pseudo G3 at the board
level functions so that the board can boot to S0 on plugging the AC on
either of the ports.
BUG=none
BRANCH=none
TEST=Manually tested on Amenia. Enter PG3, plug in the AC, charger ACOK
is asserted and the device boots to S0.
Change-Id: Idbae2306948a470592219edfe475dc9b45c1df58
Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/338825
Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
Ensure we're not charging from the port we're sourcing, but don't touch
the other port.
BUG=chrome-os-partner:52315
BRANCH=None
TEST=Attach unpowered peripheral + zinger to kevin and go to S0. Verify
that we continue pulling current from zinger at 3A.
Change-Id: Ic22b10e9ae08459cf062d7a51c9d627832d9ed63
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/338833
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
BUG=none
BRANCH=none
TEST=on system which has different static battery info based on
battery present, when the present status has changed, verify the
battery info is also changed.
Change-Id: Id58c545e3315dc63c6dd6b59141b6302d767bfb7
Signed-off-by: Kevin K Wong <kevin.k.wong@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/331655
Reviewed-by: Li1 Feng <li1.feng@intel.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
While kevin is still in development default to connecting to the CCD PHY
instead of the AP PHY. This will automatically enable CCD instead of
having to rely on things working to detect the debug accessory and
switch to the proper PHY.
We also disable the TX lines to the AP and EC, in case servo is
connected. To turn them on manually, use these console commands:
rw 0x40060040 74
rw 0x400600c8 78
pinmux
gpiocfg
BUG=chrome-os-partner:50700,chrome-os-partner:52281,http://crosbug.com/p/52322
BRANCH=none
TEST=hook up suzy q to kevin. Run 'lsusb -vd 18d1:5014' and check that a
device appears.
Change-Id: Ic2802430680adc6186982022c995ee6f452b45fd
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/338680
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
Trybot-Ready: Bill Richardson <wfrichar@chromium.org>
Tested-by: Bill Richardson <wfrichar@chromium.org>
Support both old and new ioctl formats at the same time.
Auto-detect the ioctl format used by the kernel.
BUG=chromium:481710
BRANCH=None
TEST=Work on Samus with kernel 4.4 and 3.8/3.14/3.18
Change-Id: I31d7ce5b517b4b5af8e2b617e386c3cfd3276f20
Signed-off-by: Guenter Roeck <groeck@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/331830
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Gwendal Grignou <gwendal@chromium.org>
This enables the Cr50 to accept RW firmware updates over USB.
BUG=chrome-os-partner:50707, chrome-os-partner:50712
BRANCH=none
TEST=make buildall; test on Cr50
Build and run the extra/usb_updater utility. Watch the console,
and observe that the Cr50 updates and reboots into the new image
correctly.
Note that you'll have to rebuild the ec.bin image in order for
the update to take effect. Just reflashing the same image doesn't
cause the bootloader to change its selection.
All the previously existing endpoints continue to function normally.
Change-Id: I7bd22eae803c2ceeb14a767c06d3d5c9f1ac7c7a
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/338089
Commit-Ready: Vadim Bendebury <vbendeb@chromium.org>
This adds a standalone linux utility to deliver RW firmware
updates to the Cr50 over USB.
It prepares update blocks required by the firmware upgrader, and then
fragments and transfers the blocks though the USB channel. The blocks
are reassembled on the target and passed to the upgrade module for
integrity verification and programming.
BUG=chrome-os-partner:50712
BRANCH=none
TEST=make buildall; test on Cr50 as follows:
sudo extra/usb_updater/usb_updater build/cr50/ec.bin
The Cr50 doesn't yet accept firmware updates that way,
so there's no functionality to test just yet.
Change-Id: I1c698fd0c553c936d58ff16a2acaa05ae05bc857
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/338088
This re-factors the existing firmware upgrade facility, which worked as
a TPM command extension.
The same code processing upgrade blocks prepended by the truncated
SHA1 and the load address is now used by both extended TPM command and
the USB upgrader.
To accommodate USB communications using a smaller message payloads a
reassembly layer is introduced which accumulates short USB payloads
into a single block which can be passed to the firmware upgrade
routine. USB encapsulation adds one 4 byte header at the beginning of
the block to hold the total block size. The reassembly layer keeps
receiving USB messages, concatenating their payloads until the full
block is received.
A config option is added to make sure the module is not compiled when
not needed.
BUG=chrome-os-partner:50707
BRANCH=none
TEST=make buildall; test on Cr50 - with the rest of the patches
applied it is possible to upgrade firmware using the USB utility
on the host..
Change-Id: Ib30b381c4ab196ea9d352f3c6b8f46dc23ddd599
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/338087
Various voltage rails will be enabled / disabled by the PMIC when
GPIO_PMIC_SLP_SUS_L changes. We need to delay the disable of V0.85A
by approximately 25ms in order to allow V1.00A to sufficiently discharge
first.
BUG=chrome-os-partner:52047
TEST=Probe V1.00A and V0.85A during power-down, verify V1.00A discharges
faster than V0.85A.
BRANCH=glados
Change-Id: Ibbf4f989e1814e131dc373d2b5da9b6fa1ac9cce
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/337325
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
It's handy to use the usb-stream interfaces to avoid a lot of
typing. But not all the endpoints are traditional serial ports.
This just adds a new macro that lets us specify additional
parameters.
BUG=chrome-os-partner:50707
BRANCH=none
TEST=make buildall; test on Cr50
Verified that all the previous endpoints still work as before.
There are no endpoints that use the new macro yet.
Change-Id: Ia37901cbe3adc4a4650ab91db3596efa15a110de
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/338086
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
The scheme to disable PD communication in locked RO needs to be
implemented on other platforms, so move it to common code, behind
CONFIG_USB_PD_COMM_LOCKED.
BUG=chrome-os-partner:52157
BRANCH=glados
TEST=Manual on chell. Lock system and boot to recovery, then verify PD
communication is functional. Enable CONFIG_USB_PD_COMM_LOCKED and verify
PD communication isn't functional under the same test conditions.
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: I8d1f24c0b60cf1c54e329af003b7083ee55ffc40
Reviewed-on: https://chromium-review.googlesource.com/338064
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Use LARGER_TASK_STACK_SIZE to increase stack size to 640 bytes.
Check HOSTCMD stack usage with "taskinfo" command while running
the suspend/resume stress test.
8 R HOSTCMD 00000001 21.133553 496/640
It exceeds 488 bytes of TASK_STACK_SIZE.
BUG=chrome-os-partner:51773
BRANCH=none
TEST=enter "suspend_stress_test -i spi32766.0" in AP to do
suspend test. System won't do cold reboot which is cause by
"Stack overflow in HOSTCMD task!".
Change-Id: Ic5edebc6b77637ca2c648798398e3f24bc87ca27
Signed-off-by: YH Huang <yh.huang@mediatek.com>
Reviewed-on: https://chromium-review.googlesource.com/336593
Reviewed-by: Rong Chang <rongchang@chromium.org>
If we #define CONFIG_RW_B, the firmware image can have two RW
components. This CL expands the "sysinfo" command so that we can
see which image we're running from when RW_B is also a
possibility.
BUG=chrome-os-partner:50701
BRANCH=none
TEST=make buildall; test RW update on Cr50
Using test/tpm_test/tpmtest.py, update the RW firmware and reboot
several times to switch between RW_A and RW_B. Note that the
"sysjump" command reports the correct image each time.
Change-Id: Iba3778579587f6df198728d3783cb848b4fd199d
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/337664
Reviewed-by: Randall Spangler <rspangler@chromium.org>
This adds a command to connect or disconnect, and to switch the
PHY between A or B.
BUG=chrome-os-partner:52055
BRANCH=none
TEST=make buildall; test on Cr50
Using a test board with both PHYs plugged in, try the various
commands:
usb off
usb on
usb a
usb b
The on/off option connects and disconnects, the a/b option
switches between PHYs. You can see the state change on the
console, or by running dmesg on the host.
Change-Id: I4c77e9c586ce197dc99b0b50af7396c253a1a377
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/337706
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
This change adds support for forwarding the EC console through USB.
BUG=chrome-os-partner:49960
BRANCH=none
TEST=load the google-serial udev rules in extra/usb_serial/, build the
raiden.ko module, and then check that the console can be accessed from
/dev/google/Cr50/serial/Shell
Change-Id: I35e0bb39fdc8f9485a14c03eb3a4d2f024884e17
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/334132
Tested-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
Cr50 will be used to debug the EC and AP through USB. This change
enables exporting the EC and AP UART through USB by adding the endpoints
and enabling the UART and USB streams.
BUG=chrome-os-partner:50702
BRANCH=none
TEST=Load the serial driver in ec/extras and verify that the EC and AP
UARTs can be accessed through /dev/google/Cr50*/serial/AP and EC.
Change-Id: I3249b250d0ecc41a206c45c5ca66b5a6a5622e62
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/337294
Tested-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
CR50 will need three serial endpoints for the streaming AP and EC UART
and exporting its own console through USB. This change adds a macro to
create endpoints that can be recognized by the usb_serial driver.
BUG=chrome-os-partner:50702
BRANCH=none
TEST=Verify "/dev/google/Cr50*/serial/Blob" prints capital letters when
lower case letters are input.
Change-Id: Iddf2c957a00dc3cd5448a6a00de2cf61ef5dd84c
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/336441
Tested-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
If the charge current or charge voltage registers are set to zero then the
charger cuts the power to board. BD99955 does not support 0mA charge current
& 0mV charge voltage values hence set the charge current & charge voltage
to charger's minimum values.
BUG=chrome-os-partner:52050
BRANCH=none
TEST=Manually tested on Amenia. Board can boot without the battery.
Battery does not discharge when the charger current or charger
voltage is sent to 0 from the charger manager.
Change-Id: I8049525594d107d7ad1ff2f17e8df757ee86458c
Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/337404
Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
If the Cr50 is in deep sleep, it does a full warm boot when it
sees the SPS_CS_L assert. The master doesn't wait for it to
boot (because it doesn't know it has to) and starts clocking in
data bits right away. The Cr50 can't set up the SPS controller
quickly enough to capture those bits, so the first N bits/bytes
are lost and the master keeps clocking, waiting for the SPI
response which it will never get.
To be certain that the Cr50 is awake, this CL causes the
test (master) to assert SPS_CS_L briefly, then wait a little bit
for the Cr50 to wake up from deep sleep (50ms should be plenty),
and THEN it can send the rest of the SPI traffic.
The Cr50 won't enter deep sleep until it's been at least a second
since the last SPI activity, so we don't have to worry about it
going to sleep between SPI commands as long as they're not
terribly far apart.
The kernel driver will have to implement this same hack too,
since the SPI bus doesn't have a suspend/resume protocol like the
USB does. We've known this for some time. It would be nice if
this weren't needed, but it's a hardware constraint.
BUG=chrome-os-partner:49955, chrome-os-partner:52019, b:28018682
BRANCH=none
TEST=make buildall; test on Cr50
Ensure that the Cr50 invokes sleep or deep sleep when idle (refer
to previous commit messages for the setup required), then
cd test/tpm_test
make
./tpmtest.py
Before this CL, the test hung or failed because it couldn't get a
quick response from the Cr50. With this CL, the Cr50 wakes up and
the test passes.
Change-Id: I581475726313981a780beaaa37638e9c3b9ebec5
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/336837
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
When compiling the EC firmware outside of the chroot, some
optional packages may not be installed. Let's be sure the tools
exist before we try to use them.
BUG=none
BRANCH=none
TEST=make buildall, both inside and outside of the chroot
Note that to build outside the chroot, we need to
1. Use GNU make verion 4.1 or later
2. Install the gcc-arm-none-eabi package
Change-Id: I78c75cb4ad658c003ded71b244b0458ae5532e0b
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/337341
Reviewed-by: Shawn N <shawnn@chromium.org>
bd99955 enables BC1.2 detection by default and auto-sets current limit
based upon the detection results. This is undesirable because it races
against our external current limit settings (eg. USB-C / PD detection).
BUG=chrome-os-partner:51766
BRANCH=None
TEST=Manual on kevin. Plug zinger 10 times, verify that battery charges
at ~1500mA on each plug, except for cases where Zinger falls into reset
/ OC loop (a separate issue).
Change-Id: I787b2434c30b89fe78bbe50666075c694bf64503
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/336970
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
This adds (and uses) some additional flags for gpio.inc's
PINMUX() macro, to configure specific pads as wake sources when
the SoC is sleeping.
BUG=chrome-os-partner:49955
BRANCH=none
TEST=make buildall; test on Cr50
The sleep/deep sleep behavior is unchanged. This just replaces
hard-coded wake sources with pads configured in gpio.inc and the
chip/g/sps.c module. Tests from previous CLs still pass.
Change-Id: I6608dc959524f42fd589feb804fa06f29cfd9b9c
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/336838
Reviewed-by: Dominic Rizzo <domrizzo@google.com>
This adds support for the "sleep" low-power mode. It consumes
less power than simply waiting, but doesn't require a full warm
boot to resume.
BUG=chrome-os-partner:49955
BRANCH=none
TEST=make buildall; test on Cr50
Configure the Cr50 to sleep when idle (refer to previous commit
messages for the setup required).
On the console, use the "idle" command to test the three
different modes:
idle w - wfi, wakes instantly
idle s - sleep, wakes slowly but without rebooting
idle d - deep sleep, wakes via warm boot
You can tell the difference between wfi and sleep by observing
that the first character is lost when typing on the serial
console while in sleep (remember that it will wait at least 10
seconds after the last console input before sleeping).
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Change-Id: Ib2584aa44ab885f0c8369ec938ee17b935aa0898
Reviewed-on: https://chromium-review.googlesource.com/336836
Reviewed-by: Dominic Rizzo <domrizzo@google.com>
Wait at least 10 seconds after the last console input before
invoking sleep or deep sleep.
BUG=chrome-os-partner:49955, chrome-os-partner:50721
BRANCH=none
TEST=make buildall; test on Cr50
Use the "idle d" console command to put the Cr50 into deep sleep
when idle (refer to previous commit messages for the setup
required).
Wake it up, then let it sleep again. It should go back to sleep
quickly when woken via USB, but should take much longer when
awakened by typing on the serial console.
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Change-Id: I7a2b840565f5d82e0dbdf8a3e75061a69cb9e405
Reviewed-on: https://chromium-review.googlesource.com/336835
Reviewed-by: Dominic Rizzo <domrizzo@google.com>
This preserves the selected idle action (wfi, sleep, deep sleep)
across soft reboots, which includes deep sleep. Hard reboots will
restore the default which is to not sleep at all.
BUG=chrome-os-partner:49955, chrome-os-partner:50721
BRANCH=none
TEST=make buildall; test on Cr50
Use the "idle d" console command to put the Cr50 into deep sleep
when idle (refer to previous commit messages for the setup
required).
Wake it up, then let it sleep again. It should go back to the
deep sleep state.
Change-Id: Iaad82b725d2b32a19205fa403dbaab9a31c35630
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/336834
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
