Prior to going to S0, GPIO_SHI_CS_L may be low, which can cause glitches
in the SHI HW unit. Enable the GPIO interrupt in S0, and disable it when
leaving S0.
BUG=chrome-os-partner:52222,chrome-os-partner:52217
BRANCH=None
TEST=Manual on kevin. Verify 'ectool version' succeeds with subsequent
kernel / ectool patches.
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: Ie3494122c2486429d3f648ab9220daf5dd34f812
Reviewed-on: https://chromium-review.googlesource.com/338857
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
Previously the maximum number of deferred routines was specified by the
the default maximum number of deferred routines you had to override
this, and if you wanted fewer, you still payed the price of having the
defer_until array statically allocated to be the maximum size.
This change removes that define and instead creates the RAM state of
the deferred routine (the time to wait until to call the deferred) when
the deferred is declared.
Signed-off-by: Anton Staaf <robotboy@chromium.org>
BRANCH=None
BUG=None
TEST=make buildall -j
manually test on discovery-stm32f072
Change-Id: Id3db84ee1795226b7818c57f68c1f637567831dc
Reviewed-on: https://chromium-review.googlesource.com/335597
Commit-Ready: Anton Staaf <robotboy@chromium.org>
Tested-by: Anton Staaf <robotboy@chromium.org>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Previously calls to hook_call_deferred were passed the function to call,
which was then looked up in the .rodata.deferred section with a linear
search. This linear search can be replaced with a subtract by passing
the pointer to the deferred_data object created when DECLARE_DEFERRED
was invoked.
Signed-off-by: Anton Staaf <robotboy@chromium.org>
BRANCH=None
BUG=None
CQ-DEPEND=CL:*255812
TEST=make buildall -j
Change-Id: I951dd1541302875b102dd086154cf05591694440
Reviewed-on: https://chromium-review.googlesource.com/334315
Commit-Ready: Bill Richardson <wfrichar@chromium.org>
Tested-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
It was observed that when connecting to the CR50 console over USB,
there the line feed (LF) characters are not supplemented by carriage
return (CR), which causes weird console output.
Detailed examination has shown that uart_putc() does not do the right
thing itself and also bypasses __tx_char() used by uart_puts(), which
does the right thing.
The simplest solution is to have uart_putc() re-use all the smarts of
uart_puts().
BRANCH=none
BUG=none
TEST=verified that usb console output does not suffer from the "lost
CR" syndrome any more.
Change-Id: I2a1f84b2524c41eb6e84186141b0b9ac55e87ee0
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/339217
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
This signal should be active low, not active high. In addition,
not only can we pull it low but so can other components. If
something else asserts it, we need to react.
This changes the polarity and sets up the interrupt handler. A
future CL will be needed to make the handler do something useful.
BUG=chrome-os-partner:52366
BRANCH=none
TEST=make buildall; test on Cr50
On the test board, short M0 to ground to trigger the interrupt.
Watch the input value with
gpioget
You can drive the output (and trigger the interrupt) with
gpioset SYS_RST_L_OUT 0
gpioset SYS_RST_L_OUT 1
Change-Id: I3556963859601f43f990fc83f26d2cea919383c6
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/339214
Reviewed-by: Shawn N <shawnn@chromium.org>
In board/*/gpio.inc, we can specify pullups and pulldowns on pads
connected to GPIOs, like so:
GPIO(SOME_BUTTON, PIN(0,0), GPIO_INPUT | GPIO_PULL_UP)
This adds flags to do the same thing for pads that connect to
internal periperals:
PINMUX(FUNC(UART0_RX), A1, DIO_PULL_UP)
BUG=chrome-os-partner:51410
BRANCH=none
TEST=make buildall; manual test on Cr50
I added these flags to the gpio.inc file and tested the result:
PINMUX(FUNC(I2C0_SCL), B0, DIO_INPUT | DIO_PULL_UP)
PINMUX(FUNC(I2C0_SDA), B1, DIO_INPUT | DIO_PULL_DOWN)
The "pinmux" console command showed that the new flags took effect:
Before:
400600a0: DIOB0 0 IN
400600a8: DIOB1 0 IN
After:
400600a0: DIOB0 0 IN PU
400600a8: DIOB1 0 IN PD
Change-Id: I1d212331431ef67b2f1bcece8729d092b9ad5ba8
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/339254
Reviewed-by: Dominic Rizzo <domrizzo@google.com>
When a debug accessory is detected by cr50, the USB controller switches
to using the CCD PHY and switches back to the AP PHY when the cable is
disconnected. This change also enables controlling the UART TX output
for the AP and EC console.
BUG=chrome-os-partner:50700
BRANCH=none
TEST=Attach suzy Q and verify the PHY is set to B. Detach Suzy Q and
check the phy has switched to A.
Change-Id: I07f4c4fb7f765788a0914dfc2451a11af8bf0ab2
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/339211
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
When the debug cable is plugged in enable the EC and AP UART output.
Disable the output when the cable is disconnected so servo can use the
UARTs.
BUG=chrome-os-partner:52322
BRANCH=none
TEST=Verify commands can be sent to the EC UART through usb when suzy q
is connected. Verify servo can interact with the EC UART when suzy q is
not connected.
Change-Id: I2ce0e9da464b24e295e732aa638bfc32323cc72d
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/338858
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
The device-specific subclass used for Non-HC firmware updates is
in the spreadsheet now, so we can rename the macros to be
"official".
BUG=chrome-os-partner:49962
BRANCH=none
TEST=make buildall; test on cr50
make BOARD=cr50 (plus whatever signing magic works for you)
make -C extra/usb_updater
./extra/usb_updater/usb_updater build/cr50/ec.bin (sudo if needed)
Note that you may need to rebuild ec.bin in order to see any
difference after the update. If the A & B images are identical,
the RO bootloader always picks A.
Change-Id: I385ce89a9abe2059d52da2d82a0b92b9b3e3c93f
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/339220
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
On !LPC EC, we can read memory via CROS_EC_DEV_IOCXCMD ioctl,
using command EC_CMD_READ_MEMMAP.
On platform that supports direct memory access (lpc), we access
the memory directly, bypassing the ioctl.
BUG=chromium:602832
TEST=On gnawty and veyron, check 'ectool battery' works.
Verify that gnawty use io mapped registers.
BRANCH=none
Change-Id: I9bfcddcf450bf8df63ead78e1df97dd7392289e6
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/338853
Reviewed-by: Randall Spangler <rspangler@chromium.org>
PMIC already has a built-in 100ms delay for V1P05S when ALL_SYS_PWRGD
asserts, hence EC can assert SOC_PWROK immediately. On shutdown RSMRST_N
should assert and SOC_PWR_OK should de-assert immediately when PMIC asserts
PMIC_RSMRST_N and de-assert All_SYS_PWRGD respectively. Hence removed
the unnecessary timing delay for SOC_PWROK and RSMRST_N.
BUG=none
BRANCH=none
TEST=Issued a shutdown command and manually tested on amenia.
RSMRST_N asserts immediately when PMIC asserts PMIC_RSMRST_N
SOC_PWR_OK de-asserts immediately when PMIC de-asserts All_SYS_PWRGD.
Change-Id: I8bb79277a3dcf8545764ba58736f422ac377776e
Signed-off-by: Kevin K Wong <kevin.k.wong@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/339001
Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
Change the AP UART TX and RX gpios to match the schematic.
BUG=chrome-os-partner:50702
BRANCH=none
TEST=verify AP console output can be seen by cr50
Change-Id: I572bf2f664c276f094116e8a72400c9332bc10a7
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/338895
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
The TPM library serializes RSA keys in big-endian format, while
CR50 requires little-endian.
Handle endianness by converting from big to little and back
to big within the _cpri__* layer.
Also modify test code to make copies of static const RSA keys, as
these get placed on read-only memory.
BRANCH=none
BUG=chrome-os-partner:43025,chrome-os-partner:47524,chrome-os-partner:52337
TEST=tests in test/tpm/tpmtest.py pass
Change-Id: Id9cfbe8c99ecaeb02744fbc7554cd48a08bab819
Signed-off-by: nagendra modadugu <ngm@google.com>
Reviewed-on: https://chromium-review.googlesource.com/331740
Commit-Ready: Nagendra Modadugu <ngm@google.com>
Tested-by: Nagendra Modadugu <ngm@google.com>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
It is quite annoying to see an error reported by buildall, but not
knowing what board(s) actually failed to build.
Create file for each board being built, put build progress information
in it, and remove it if the board build succeeded. Then, once the
build is completed see the failed boards in .failedboards/, if any,
and the states they failed at.
BRANCH=none
BUG=none
TEST=verified that the directory is empty after a successful buildall
run, and has files named after failed boards in case of build
failures.
Change-Id: I67eb1671cadf58d9f8feccebfcc860524f33c2a0
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/338883
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
Implement warm reset and force shutdown routines, which are called from
other modules.
BUG=chrome-os-partner:51926, chrome-os-partner:51923
BRANCH=None
TEST=Verify 'apshutdown' on EC console goes to G3. Verify 'apreset'
causes AP reset while staying in S0.
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: Ifb479287f87f31ac49e007c337cc0c24a79898e6
Reviewed-on: https://chromium-review.googlesource.com/338923
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
Add support for SHA256 based HKDF key
derivation as specified in RFC 5869. This
change includes test vectors from the RFC.
BRANCH=none
BUG=chrome-os-partner:43025,chrome-os-partner:47524
TEST=tests under test/tpm2 pass
Change-Id: I7d0e4e92775b74c41643f45587fc08f56d8916aa
Signed-off-by: nagendra modadugu <ngm@google.com>
Reviewed-on: https://chromium-review.googlesource.com/336091
Commit-Ready: Nagendra Modadugu <ngm@google.com>
Tested-by: Nagendra Modadugu <ngm@google.com>
Reviewed-by: Marius Schilder <mschilder@chromium.org>
The TPM library serializes ECC parameters in big-endian format,
while CR50 requires little-endian.
Handle endianness by converting from big to little and back
to big within the _cpri__* layer.
Also modify test code to make copies of static const ECC keys, as
these get placed on read-only memory.
Rename a couple of instances of ec_ with ecc_ to avoid confusion.
BRANCH=none
BUG=chrome-os-partner:43025,chrome-os-partner:47524,chrome-os-partner:52337
TEST=tests in test/tpm/tpmtest.py pass
Change-Id: I607984f004820d5caa85ce13575b8ab501336479
Signed-off-by: nagendra modadugu <ngm@google.com>
Reviewed-on: https://chromium-review.googlesource.com/331673
Commit-Ready: Nagendra Modadugu <ngm@google.com>
Tested-by: Nagendra Modadugu <ngm@google.com>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Elm is an oak variant that uses ANX7688 PD port controller. This CL sets
PD port count to 1 and modifies TCPC I2C address to 0x50.
Other elm changes are included in this change:
- add 2 KX022 motion sensors, remove BMI160
- remove ALS
- LED configuration changed to 2 bi-color LEDs
- remove pi3usb30532
- add ANX7688 mux driver
- change PD interrupt polarity
BRANCH=none
BUG=none
TEST=manual
make BOARD=elm -j
load and test on elm proto
Signed-off-by: Rong Chang <rongchang@chromium.org>
Change-Id: I8ad02da9acade985bc0e7e2f85d9e58db7e6b38d
Reviewed-on: https://chromium-review.googlesource.com/331453
Reviewed-by: Shawn N <shawnn@chromium.org>
The new debug board presents itself as a yet another USB device, it
uses interface 1 for SPI.
Add it to the table of devices we try to use.
BRANCH=none
BUG=none
TEST=./test/tpm_test/tpm_test.py now succeeds again.
Change-Id: Id14f17de6eff081bebed49d22ddc4b19cd39c2b0
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/338862
Reviewed-by: Marius Schilder <mschilder@chromium.org>
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
This adds support for RD Detection on cr50. It can be used to detect a
debug device and signal the controller to switch from the AP PHY to the
to CCD PHY. When RDCC1 and 2 no longer detect the debug device, then
the controller switches back to using the USB to AP PHY.
BUG=chrome-os-partner:50700
BRANCH=none
TEST=change the value on RDCC1 and RDCC1 and check that the usb
controller connects to the right PHY.
Change-Id: Ice01a45a31fe1932945f89df2e3b851f4d287a17
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/338454
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
This change is required for support 'CONFIG_LOW_POWER_S0'.
Signed-off-by: Dino Li <dino.li@ite.com.tw>
BRANCH=none
BUG=none
TEST=1. fanset 5555, EC enter doze mode only and fan control is functional.
2. fanset 0, EC will enter deep doze mode properly.
Change-Id: I3780b12ef54713258769616bfed0155c865c0725
Reviewed-on: https://chromium-review.googlesource.com/338750
Commit-Ready: Dino Li <dino.li@ite.com.tw>
Tested-by: Dino Li <dino.li@ite.com.tw>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
In case of boot after battery is cut-off without this
change the battery is assumed to be present even though it
is not initialized and ready to provide power in try source
enable function. With this assumption charger is disconnected
momentarily which causes reboot.
Also make sure that try source enable is updated after battery
is ready by notifying hook call HOOK_BATTERY_SOC_CHANGE.
BUG=chrome-os-partner:51753
BRANCH=firmware-glados-7820.B
TEST=Enter battery cutoff command from EC console to enter into ship
mode and plug-in AC, verified no reboots happen.
Change-Id: I6f7656125717f85851f5ad4e37dfd953a52799c6
Signed-off-by: Divya Sasidharan <divya.s.sasidharan@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/335913
Reviewed-by: Shawn N <shawnn@chromium.org>
(cherry picked from commit 10040ac6284efe88b74193bdbb0c05ec92b563b4)
Reviewed-on: https://chromium-review.googlesource.com/336697
Commit-Ready: Divya S Sasidharan <divya.s.sasidharan@intel.com>
Tested-by: Divya Jyothi <divya.jyothi@intel.com>
In Pseudo G3 if both VBUS_EN & VCC_EN are disabled, on plugging the AC
on either of the ports, ACOK pin is not asserted because the charger
cannot detect the voltage on either of the ports. Hence the device cannot
boot until the power button is pressed.
Enable both the VBUS_EN & VCC_EN before entering pseudo G3 at the board
level functions so that the board can boot to S0 on plugging the AC on
either of the ports.
BUG=none
BRANCH=none
TEST=Manually tested on Amenia. Enter PG3, plug in the AC, charger ACOK
is asserted and the device boots to S0.
Change-Id: Idbae2306948a470592219edfe475dc9b45c1df58
Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/338825
Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
Ensure we're not charging from the port we're sourcing, but don't touch
the other port.
BUG=chrome-os-partner:52315
BRANCH=None
TEST=Attach unpowered peripheral + zinger to kevin and go to S0. Verify
that we continue pulling current from zinger at 3A.
Change-Id: Ic22b10e9ae08459cf062d7a51c9d627832d9ed63
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/338833
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
BUG=none
BRANCH=none
TEST=on system which has different static battery info based on
battery present, when the present status has changed, verify the
battery info is also changed.
Change-Id: Id58c545e3315dc63c6dd6b59141b6302d767bfb7
Signed-off-by: Kevin K Wong <kevin.k.wong@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/331655
Reviewed-by: Li1 Feng <li1.feng@intel.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
While kevin is still in development default to connecting to the CCD PHY
instead of the AP PHY. This will automatically enable CCD instead of
having to rely on things working to detect the debug accessory and
switch to the proper PHY.
We also disable the TX lines to the AP and EC, in case servo is
connected. To turn them on manually, use these console commands:
rw 0x40060040 74
rw 0x400600c8 78
pinmux
gpiocfg
BUG=chrome-os-partner:50700,chrome-os-partner:52281,http://crosbug.com/p/52322
BRANCH=none
TEST=hook up suzy q to kevin. Run 'lsusb -vd 18d1:5014' and check that a
device appears.
Change-Id: Ic2802430680adc6186982022c995ee6f452b45fd
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/338680
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
Trybot-Ready: Bill Richardson <wfrichar@chromium.org>
Tested-by: Bill Richardson <wfrichar@chromium.org>
Support both old and new ioctl formats at the same time.
Auto-detect the ioctl format used by the kernel.
BUG=chromium:481710
BRANCH=None
TEST=Work on Samus with kernel 4.4 and 3.8/3.14/3.18
Change-Id: I31d7ce5b517b4b5af8e2b617e386c3cfd3276f20
Signed-off-by: Guenter Roeck <groeck@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/331830
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Gwendal Grignou <gwendal@chromium.org>
This enables the Cr50 to accept RW firmware updates over USB.
BUG=chrome-os-partner:50707, chrome-os-partner:50712
BRANCH=none
TEST=make buildall; test on Cr50
Build and run the extra/usb_updater utility. Watch the console,
and observe that the Cr50 updates and reboots into the new image
correctly.
Note that you'll have to rebuild the ec.bin image in order for
the update to take effect. Just reflashing the same image doesn't
cause the bootloader to change its selection.
All the previously existing endpoints continue to function normally.
Change-Id: I7bd22eae803c2ceeb14a767c06d3d5c9f1ac7c7a
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/338089
Commit-Ready: Vadim Bendebury <vbendeb@chromium.org>
This adds a standalone linux utility to deliver RW firmware
updates to the Cr50 over USB.
It prepares update blocks required by the firmware upgrader, and then
fragments and transfers the blocks though the USB channel. The blocks
are reassembled on the target and passed to the upgrade module for
integrity verification and programming.
BUG=chrome-os-partner:50712
BRANCH=none
TEST=make buildall; test on Cr50 as follows:
sudo extra/usb_updater/usb_updater build/cr50/ec.bin
The Cr50 doesn't yet accept firmware updates that way,
so there's no functionality to test just yet.
Change-Id: I1c698fd0c553c936d58ff16a2acaa05ae05bc857
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/338088
This re-factors the existing firmware upgrade facility, which worked as
a TPM command extension.
The same code processing upgrade blocks prepended by the truncated
SHA1 and the load address is now used by both extended TPM command and
the USB upgrader.
To accommodate USB communications using a smaller message payloads a
reassembly layer is introduced which accumulates short USB payloads
into a single block which can be passed to the firmware upgrade
routine. USB encapsulation adds one 4 byte header at the beginning of
the block to hold the total block size. The reassembly layer keeps
receiving USB messages, concatenating their payloads until the full
block is received.
A config option is added to make sure the module is not compiled when
not needed.
BUG=chrome-os-partner:50707
BRANCH=none
TEST=make buildall; test on Cr50 - with the rest of the patches
applied it is possible to upgrade firmware using the USB utility
on the host..
Change-Id: Ib30b381c4ab196ea9d352f3c6b8f46dc23ddd599
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/338087
Various voltage rails will be enabled / disabled by the PMIC when
GPIO_PMIC_SLP_SUS_L changes. We need to delay the disable of V0.85A
by approximately 25ms in order to allow V1.00A to sufficiently discharge
first.
BUG=chrome-os-partner:52047
TEST=Probe V1.00A and V0.85A during power-down, verify V1.00A discharges
faster than V0.85A.
BRANCH=glados
Change-Id: Ibbf4f989e1814e131dc373d2b5da9b6fa1ac9cce
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/337325
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
It's handy to use the usb-stream interfaces to avoid a lot of
typing. But not all the endpoints are traditional serial ports.
This just adds a new macro that lets us specify additional
parameters.
BUG=chrome-os-partner:50707
BRANCH=none
TEST=make buildall; test on Cr50
Verified that all the previous endpoints still work as before.
There are no endpoints that use the new macro yet.
Change-Id: Ia37901cbe3adc4a4650ab91db3596efa15a110de
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/338086
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
The scheme to disable PD communication in locked RO needs to be
implemented on other platforms, so move it to common code, behind
CONFIG_USB_PD_COMM_LOCKED.
BUG=chrome-os-partner:52157
BRANCH=glados
TEST=Manual on chell. Lock system and boot to recovery, then verify PD
communication is functional. Enable CONFIG_USB_PD_COMM_LOCKED and verify
PD communication isn't functional under the same test conditions.
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: I8d1f24c0b60cf1c54e329af003b7083ee55ffc40
Reviewed-on: https://chromium-review.googlesource.com/338064
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
