The code clearly indends to sleep on the second time the loop
is taken, but the variable first_exchange is reset to 1 inside
the loop. If, for whatever reason, PD alert status cannot be
cleared, the code will then loop forever, and lead to a watchdog
reset.
BRANCH=none
BUG=chrome-os-partner:58750
TEST=Flash EC RO using ec_util
Run fwupdatetest with charger unplugged for 10 iterations.
Change-Id: I9e13f2523111853fdc5c45e75886c11f1c8006eb
Reviewed-on: https://chromium-review.googlesource.com/401238
Commit-Ready: Nicolas Boichat <drinkcat@chromium.org>
Tested-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
The lengths were previously specified as end offsets and were
thus off by 1.
Fortunately it seems these chips were never used with an EC where we
actually utilize this table. Still, it would be nice if we actually
tested this on real hardware to check that there aren't any other
silly errors.
BUG=none
BRANCH=none
TEST=needs testing
Signed off-by: David Hendricks <dhendrix@chromium.org>
Change-Id: I0a5315808c756797940436a10cd4f6df7313ab8c
Reviewed-on: https://chromium-review.googlesource.com/400642
Commit-Ready: Dan Shi <dshi@google.com>
Tested-by: David Hendricks <dhendrix@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
The host command parameter and response buffers should be explicitly
aligned by the LPC/SPI/I2C drivers. But the host command handlers don't
know that, and the structs are all __packed, so the compiler generates
horribly inefficient ARM Cortex-M code to cope with unaligned accesses.
Add __ec_align{1,2,4} to force the param / response structs to be
aligned. Use it in a few structs now which were straightforward to
test. It should be added to more structs as space is needed, but that
would make this change unwieldy to review and test.
Add CONFIG_HOSTCMD_ALIGNED to enable the additional alignment.
Currently, this is enabled only for LM4 and samus_pd, so that EC code
can be tested without affecting other non-samus ToT development (none of
which uses LM4).
Fix the two handlers that weren't actually aligned (despite one of
them having comments to the contrary).
Also, add a CHROMIUM_EC define that can be used to determine if a file
is being compiled for an EC target. We need that so that we only force
structure alignment for EC binaries. On the AP side, buffers may not be
aligned, so we should not force alignment.
BUG=chromium:647727
BRANCH=none
TEST=Flash samus and samus_pd. Boot samus and run a bunch of ectool
commands (with and without --dev=1, so it tests both EC and PD).
System boots and all commands return expected results.
Change-Id: I4537d61a75cf087647e24281288392eb85f22eba
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/387126
Shifted pd_task debug level by 1 so that debug level 1 will
enable printing the pd state name.
Added a CONFIG flag to remove ability to change debug_level
during runtime and debug print level will be fixed.
BUG=none
BRANCH=none
TEST=make buildall
Change-Id: I545813bafa8084355cedc2d8334c3aec5a2b6739
Signed-off-by: Kevin K Wong <kevin.k.wong@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/339935
Tested-by: Divya S Sasidharan <divya.s.sasidharan@intel.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
The two types added, bool and uint_least8_t, are needed by the nanopb
common header file "pb.h".
The file added and the file modified are EC versions of files that are
normally provided by the compiler. This change follows the approach
already take to provide our own, mimimalist versions of these files.
BUG=none
BRANCH=none
TEST=make buildall -j
Change-Id: I892e25b14f7cbe3ecca6f60d6a2955d4d628e3a9
Reviewed-on: https://chromium-review.googlesource.com/398921
Commit-Ready: Carl Hamilton <carlh@chromium.org>
Tested-by: Carl Hamilton <carlh@chromium.org>
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
Don't call into tcpm_*() functions from HOOKs since these functions may
manipulate common sets of TCPC registers.
BUG=chrome-os-partner:57691
BRANCH=gru
TEST=On kevin, boot to S0, verify 5V is sourced to legacy peripheral.
Drop to G3, verify role is back to sink and charging is functional. Back
to S0, verify 5V is sourced.
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: I9ade9de068589dce6995cda6b106217aa85aa793
Reviewed-on: https://chromium-review.googlesource.com/394809
(cherry picked from commit 18e9e3870722d57efd232bd7f0a0300003b46ad6)
Reviewed-on: https://chromium-review.googlesource.com/396137
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
This allows a servo_v4 to export case closed debugging
automatically, if it detects that it's been plugged into
a ccd device.
BUG=chromium:571476
TEST=Connect to reef in both orientations.
BRANCH=None
Change-Id: I8e2781056b22e834132bc4bb839ef2763fa0b4b8
Signed-off-by: Nick Sanders <nsanders@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/375359
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Currently eCTS suites share the same directory (e.g. build/stm32l476g
-eval) to put build artifacts even though some files (e.g. board.c)
compile differently suite to suite. So, if cts-i2c-stm32l476g-eval is
built, followed by cts-gpio-stm32l476g-eval, build fails or produces
incorrect binary.
This patch makes eCTS create different directories for each suite.
As a bonus, we can now builds eCTS suites in parallel.
BUG=chromium:654549
BRANCH=none
TEST=make buildall -j (with uncommitted change)
Change-Id: I4abedc917787be5f79b97e0e50d0d08e01bd5f9d
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/398281
make build=lucid fails if there is an uncommitted change in the tree
because '-dirty' is appended to version strings, which causes the image
to exceed the flash size limit.
BUG=chromium:654549
BRANCH=none
TEST=make buildall -j
Change-Id: Ie4a7b4c7dc70846108aed953215f79dc30a10fca
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/396617
Reviewed-by: Randall Spangler <rspangler@chromium.org>
This is based off of the protocol in the stm32 directory. We should
unify these implementations and the other ccd endpoints at some point.
Right now I though that I should keep the implementation the same as the
other g chips ccd drivers.
BUG=chrome-os-partner:57059
BRANCH=none
CQ-DEPEND=CL:390015
TEST=manual
download the servo patch and run 'sudo servod -c ccd_cr50.xml -c
reef_r1_inas.xml'
Test the usb i2c bridge by running 'dut-control | grep pp'
Attach servo and verify cr50 will not enable i2c
Change-Id: I0f72671505f5451a960d3baea4b2c34b6910d892
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/388896
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-by: Nick Sanders <nsanders@chromium.org>
In dead battery mode, we can find ANX7688 will pull the CC to Rp in the beginning;
some of the adapters will drop the VBUS since this should be treated as a
disconnection, hence the whole system lost the only power source and cannot boot up.
According to chrome-os-partner:58283, there's a chance for ANX7688 to be in an
abnormal state if the system provides it with 3.3V first but RESET_N and PWR_EN
are still in an unstable level. To prevent this situation, we try to enable the
3.3V only after RESET_N and PWR_EN are in their initial state.
BRANCH=none
BUG=chrome-os-partner:58283
TEST=plug in the adapter, check ANX7688 does not pull CC to Rp in the beginning,
and boot up system in dead battery mode
Change-Id: Ibb81a33a7dd957d3bdc6c54bb7723cc9ffdcfd26
Signed-off-by: Milton Chiang <milton.chiang@mediatek.com>
Reviewed-on: https://chromium-review.googlesource.com/394408
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
The USB stream should check that there are bytes in the rx fifo to read
before trying to read them. This should have been in here already.
Checking if rx is valid in usb-stream makes the rx_valid call in usb_spi
unnecessary so that is removed.
BUG=none
BRANCH=none
TEST=manual
Test CCD functionality still works on gru and reef
AP/EC consoles
sudo flashrom -p raiden_debug_spi:[AP|EC] -r img.bin
usb updater
Change-Id: Ieb77e35cc471b1f97d540ea4560591f0f40dd600
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/397858
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
Existing get_cc function depends on set_cc function which marks a
"pull" variable to indicate if anx74xx is setting Rp or Rd. However,
if DRP auto toggle is used, this "pull" variable is unknown, but
CC_STATUS register can differentiate between SRC and SNK, so this
"pull" variable is actually not needed.
BUG=none
BRANCH=none
TEST=verify Type-C functionality did not change on Reef.
Change-Id: I6cab8d7fcee20ec6e8414b6b2591c5d975d85293
Signed-off-by: Kevin K Wong <kevin.k.wong@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/396428
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
In current FW implement, there are two ways to generate SMI/SCI:
(1) Controlled by GPIO module register.(#define CONFIG_SCI_GPIO)
(2) Controlled by PM module register.(#undef CONFIG_SCI_GPIO)
This CL fix for case(2):
In this case, these two dedicated pins(GPIOC6/GPIO76) are used
as SMI/SCI and must be enabled by pinmux. Set the related pinmux
at initial.
By default, the SMI/SCI polarity is negative. This means SMI/SCI
is inverted when writing to SMI/SCIB but not inverted when reading
from them(see Section 5.2.2, figure 61 in datasheet). It will cause
the code more complicated to implement. Disable negative polarity
at init.
Modified drivers:
1. lpc.c: set pinmux for dedicated SMI/SCI pins and disable the
negative polarity.
BUG=chrome-os-partner:34346
BRANCH=none
TEST=make buildall; try hostevent(lid switch) on Wheatley with
CONFIG_SCL_GPIO undefined.
Change-Id: Ia317e54deb6861d7189b3594bd7414b53408b933
Signed-off-by: CHLin <CHLIN56@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/396718
Commit-Ready: CH Lin <chlin56@nuvoton.com>
Tested-by: CH Lin <chlin56@nuvoton.com>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Duncan Laurie <dlaurie@google.com>
Reviewed-by: Mulin Chao <mlchao@nuvoton.com>
Doing a hard reboot after a usb spi transaction is overkill. This
changes the hard reboot to a EC reset so the AP, EC, and TPM will reset
without affecting ccd.
BUG=none
BRANCH=none
TEST=running 'sudo flashrom -p raiden_debug_spi:target=EC' doesn't
interfere with the cr50 console but resets the AP, EC, and TPM.
Change-Id: I15579c75deb837842585d1473de2182bede4ad96
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/396919
Reviewed-by: Scott Collyer <scollyer@chromium.org>
Cr50 no longer reboots when sys_rst_l is asserted so it is now safe for
cr50 to react to sys_rst when we assert it. This change removes the
is_sys_rst_asserted check before TPM reset.
BUG=none
BRANCH=none
TEST='sysrst pulse' causes the tpm to reset.
Change-Id: I8dd5ae85fc3ca839af20b7e67ef081cbb118b068
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/396616
Reviewed-by: Scott Collyer <scollyer@chromium.org>
To be able to identify different cr50 devices connected to the same
machine we need a serial number. This change uses dev id 0 and 1 to come
up with one.
BUG=chrome-os-partner:56641
BUG=chrome-os-partner:58342
BRANCH=none
TEST=lsusb -vd 18d1:5014 | grep iSerial shows different numbers for
different devices. Verify when ccd is disabled the serial number is 0.
Change-Id: I85c54af4a21bdfd0542019c02aa8420d9a879fae
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/395633
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
Add the production endorsement CA public key to
the endorsement certificate validation flow.
This change retains recognition of the test
endorsement CA public key as well, and either
issuer is accepted as valid.
BRANCH=none
BUG=none
TEST=build succeeds
Change-Id: I2666fdfb19ce8c950ef1a9190bc7b994a105132c
Signed-off-by: nagendra modadugu <ngm@google.com>
Reviewed-on: https://chromium-review.googlesource.com/396554
Commit-Ready: Nagendra Modadugu <ngm@google.com>
Tested-by: Nagendra Modadugu <ngm@google.com>
Reviewed-by: Marius Schilder <mschilder@chromium.org>
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
Enable valid bits of SCI#/SMI# of eSPI's VW if there's no CONFIG_SCI_GPIO
definition in board-level driver. This CL also fixed the order of VW
event bits in comments.
Modified sources:
1. espi.c: Enable valid bits of SCI#/SMI#.
BRANCH=none
BUG=chrome-os-partner:34346
TEST=make all; test nuvoton IC specific drivers
Change-Id: I8d094513284b4ed42c5c26fe1975d71bbf050aa4
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/396618
Reviewed-by: Duncan Laurie <dlaurie@google.com>
CONFIG_TABLET_MODE_SWITCH was incorrectly defined by default.
BUG=none
TEST=Kevin still have TABLET_MODE_SWITCH included.
BRANCH=none
Change-Id: I0748151e61eab5370be50be4512d2a851f705011
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/396384
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Endorsement registration is done with 0 for FWR keyladder branch.
The certificate packet has hmac with key derived from keyladder.
Thus RW can check that the certificate packet it is about to load does
indeed match its current keyladder status. If not, reject.
BUG=none
BRANCH=none
TEST=launch RW that has 1 for FWR and observe fail; 0 for FWR RW succeeds.
Change-Id: I820892a54fbf9aa52a6f778595b5b7ef4389cff3
Reviewed-on: https://chromium-review.googlesource.com/393233
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-by: Marius Schilder <mschilder@chromium.org>
Tested-by: Vadim Bendebury <vbendeb@chromium.org>
Tested-by: Marius Schilder <mschilder@chromium.org>
Commit-Queue: Marius Schilder <mschilder@chromium.org>
This change adds options to the powerbtn console command to press and
release the power button.
BUG=chrome-os-partner:58123
BRANCH=none
TEST=manual
'powerbtn press' force a power button press
'powerbtn release' release the power button. This will not
override the signal if the button is physically pressed.
Change-Id: I52631d30dbae874ba6637f728cb6e435cb626e12
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/396207
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
On both Reef and Gru there are INA (shunt bus voltage monitor) ICs
connected to the Cr50 I2C master bus. The use case for these chips is
in a lab setting using case closed debugging. Power to the INA chips
is controlled by a separate Cr50 gpio signal.
By default, the INAs are powered off and the I2C master bus is not
connected. A function ina_connect() is provided which needs to be
called prior to attempting to access the INAs via I2C.
BRANCH=none
BUG=chrome-os-partner:57059
TEST=manual
Tested both Reef and Gru. Verified that console command 'ccd ina
on|off' works as expected and that can repeatedly read registers on
the INA using the following command "i2cxfer r16 0 0x40 0".
Read 0x2771 [10097] which is the default value. In addition
wrote register 14 (bits 15:1 are writeable) and verified the value was
able to read the value back which was written.
Change-Id: I670f7897555dae29642264531599dc4471c52bbd
Signed-off-by: Scott <scollyer@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/394168
Commit-Ready: Scott Collyer <scollyer@chromium.org>
Tested-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
Added i2cm driver to support chip_i2c-xfer function. The initial use
case is for INA chips on the Reef/Gru platforms. Note that this CL
does not include any board specific changes and therefore does not
include an I2C port definition or required pinmux settings.
BRANCH=none
BUG=chrome-os-partner:57059,chrome-os-partner:58355
TEST=manual
Used console command "i2cxfer r16 0 0x40 0" to read the config
register. Read 0x2771 [10097] which is the default value. In addition
wrote register 14 and read back the value.
Change-Id: If9e377da4c8f4835d4676281872a0f079fe56aa6
Signed-off-by: Scott <scollyer@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/388794
Commit-Ready: Scott Collyer <scollyer@chromium.org>
Tested-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
This command will be used to perform power validation.
BUG=none
BRANCH=none
TEST=ectool backlight command can be used to enable/disable Display
Backlight while system is in S0 state.
Change-Id: Ic61aa4cf5beadc83ea9dd38bb11cf10c53d4c20e
Signed-off-by: Shamile Khan <shamile.khan@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/393007
Reviewed-by: Shawn N <shawnn@chromium.org>
For some boards, the HCDEBUG setting is defaulting to off due to "too
spammy" console output. An unfortunate side effect of this is that when
a host command results in an error, it's impossible to know what was the
command that failed.
This commit adds the host command code to the error print so that it's
clear what command failed.
BUG=None
BRANCH=gru,glados,oak
TEST=Build and flash kevin, verify that any host commands that resulted
in an error have the command code printed alongside them.
Change-Id: I6a5f251e7941a47a3cf102a1fb6c5e96ffc8fa5d
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/395490
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Match ec_commands.h, adding new type and sensors.
BUG=none
BRANCH=reef
TEST=Check on Reef that barometer sensor info is displayed properly.
Change-Id: I257f5161e5f57be562a2b3a29442b49f47f3fc89
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/394749
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
When the kernel reads sensor data via LPC, it expects the order to be:
- ACCEL
- ACCEL
- GYRO
(other sensors data are read through EC commands)
BMI160 expects ACCEL, GYRO and MAG to be next to each other.
Reorganize motion_sensor array to fit these 2 requirements:
If BMI160 in the lid:
- BASE_ACCEL
- LID_ACCEL
- LID_GYRO
...
If BMI160 in the base:
- LID_ACCEL
- BASE_ACCEL
- BASE_GRYO
...
BUG=none
BRANCH=amenia,reef,wheatley
TEST=On reef, check the sensor data pull directly by the AP (for chrome
for lid angle) is correct. Check ARC++ works are expected.
Change-Id: If9477be0de44472e38a057c0b8533cb54acee220
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/394751
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
From the specs, "KX022-1020 Specifications Rev4.0", the power up time
can be as long as 10ms.
Add a loop to be sure the device is responsive before initalizing it.
BRANCH=reef,glados,oak,veyron,cyan
BUG=none
TEST=After putting a KX022 accel as first in the list, it would not
initialize properly. After adding the loop, it initializes properly.
Change-Id: I3194a5d1deb0c2eb2a04a459aab3b4269e479af3
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/394750
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
The new extension command is used to request device reset after a
successful update when communicating over SPI.
tpm_send_pkt() is being refactored to allow passing of different
extension commands.
BRANCH=none
BUG=chrome-os-partner:58226
TEST=verified that the system gets reset and the new image version
kicks in on both gru (over SPI) and reef (over USB).
Change-Id: I02f3ef76fc4b4ee1e52dedb9cb538e072638257a
Signed-off-by: Vadim Bendebury <vbendeb@google.com>
Reviewed-on: https://chromium-review.googlesource.com/395629
Commit-Ready: Vadim Bendebury <vbendeb@chromium.org>
Tested-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
While USB updates have a mechanism to trigger the target reset, SPI
updates do not have it.
This patch adds an extension command to cause the device reset.
BRANCH=none
BUG=chrome-os-partner:58226
TEST=with the rest of the patches applied verified that the system
gets reset and the new image version kicks in on both gru (over
SPI) and reef (over USB).
Change-Id: I498538670e2c43d17b13510288eb9ae75eb7b761
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/395628
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
Usually CR50 TPM reset happens when the AP reboots, the CR50 RO does
not get a chance to run in this case, so the running RW does not
change either,
Once the idle RW section was updated, the only way to start it is to
reboot the CR50 completely, Rebooting CR50 causes the whole system
reset, so it should not be happening at random moments in time.
This patch introduces a mechanism to delay reboot to the moment when
the TPM is reset. The reboot request would be posted in the end of the
update, and then the AP would reboot, triggering a TPM reboot, which
in turn would trigger the CR50 reset.
The USB update handler now posts the reboot request instead of
triggering the reboot immediately.
BRANCH=none
BUG=chrome-os-partner:58226
TEST=with the rest of the patches applied verified that the system
gets reset and the new image version kicks in on both gru (over
SPI) and reef (over USB).
Change-Id: Iff859f2e7a48c5035a27fffd17aefe7e318af569
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/395627
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
When we are using MKBP in LPC mode, user event are not sent over MKBP.
Therefore, we can remove host_get_next_event, it will never been called.
BUG=none
BRANCH=none
TEST=compile
Change-Id: Ia6de611291648bd3f394a20b02072b1787cca7ac
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/394069
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Interrupt test checks whether DUT can be interrupted by an interrupt
and an interrupt handler can be invoked as expected.
Note the previous interrupt test ported from test/interrupt.c runs in
an emulated environment on the host, thus does not test the real
interrupt capability of the chip.
BUG=chromium:653195
BRANCH=none
TEST=Run cts.py -m interrupt
Change-Id: I21cecff07594f048633d1c1b699fb3a1876379e0
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/363943
Reviewed-by: Randall Spangler <rspangler@chromium.org>
The current implementation of the ecrst and sysrst commands don't
have a way to show the state of the EC_RST_L and SYS_RST_L.
This tweaks the commands to accept an optional "pulse" argument
in addition to the boolean arg, which will assert, pause, then
deassert the relevant signal. With no args at all, the current
signal state is shown.
BUG=chrome-os-partner:58123
BUG=chrome-os-partner:56835
BRANCH=none
TEST=manual
sysrst pulse resets the AP
sysrst on/off asserts/deasserts SYS_RST_L
sysrst displays the current SYS_RST_L state
ecrst pulse resets the EC (and AP)
ecrst on/off asserts/deasserts EC_RST_L
ecrst displays the current EC_RST_L state
Change-Id: I8e1c9a577afd9ed9e770f1b3f5c0a69e4607de66
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/395587
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
