Add code for set/getting calibration data on bmi160
Add code to perform FOC (Fast Online Calibration) on bmi160.
Add delay after getting out of suspend to be sure sensor is
available.
BRANCH=smaug
TEST=Check sensors are properly calibrated on Smaug:
Perform calibration:
echo 1 > /sys/bus/iio/devices/iio:device1/calibrate
Read calibration values:
cat /sys/bus/iio/devices/iio:device1/*_calibbias
Check the values are translated properly.
Write calibration values and check it affects the
sensor output.
BUG=chromium:506101,chrome-os-partner:39900
Change-Id: Ib9aad9bbd90b4249625641d68febf94b69aa4987
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/283165
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Store at which frequency each sensor should be sampled.
This frequency is different from the sensor frequency:
- sensor frequency: frequency at which the sensor produce information.
- sensor sampling frequency: frequency at the which the EC gater
information.
If 2 sensors must be sampled at very different frequency,
we don't want to oversample the slow one, and filling the
software FIFO unnecessarily.
BRANCH=smaug
TEST=Unit test. Check that frequency is correct when sensor
frequencies change from IIO driver.
BUG=chrome-os-partner:39900
Change-Id: I4272963413f53d4ca004e26639dc7a2affd317eb
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/284616
Reviewed-by: Alec Berg <alecaberg@chromium.org>
port80 task polling prevents the EC from entering low power states and
isn't useful when the AP isn't running. Therefore, when
CONFIG_PORT80_TASK_EN is enabled, only enable the port80 task when
entering S0, and disable it when leaving S0.
BUG=chrome-os-partner:42104
TEST=Manual on Glados. Boot AP, verify that 'port80' log starts with "10
20...". Shutdown AP, verify with 'taskinfo' that PORT80 task stops
consuming cycles. Boot AP again, verify that 'port80' log starts with
new "10 20...".
BRANCH=None
Change-Id: Id41dbdaa4597456d042b7a3921c1ec439af759f4
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/285550
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Alec Berg <alecaberg@chromium.org>
When FIFO overfills, keep track of the number of lost vectors per
vector types. This way, when we calculate timestamps in user space,
we can evaluate the number of empty slots to skip per vector type.
This is important when different types are samples at very different
frequencies.
BRANCH=smaug
TEST=Check that when we drop events, the timestamp are better than
without.
BUG=chrome-os-partner:39900
Change-Id: Ib9cb994ada38373e5a49dd4ba2123ca7534a169e
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/284615
Reviewed-by: Alec Berg <alecaberg@chromium.org>
To meet Android HiFi requirement, set accelerometer range to +/-8g.
BRANCH=smaug
TEST=Check range is correct from user space.
BUG=chrome-os-partner:39900
Change-Id: I4e08c8dddf6d345185c961e7db8ab47f3b1aa5c0
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/284614
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
- Disable USB, wireless and audio power rail when powering down from S3
- Disable sensor power rail and display backlight when powering down
from S0
BUG=chrome-os-partner:42104
TEST=Manual on Glados. Boot AP, verify that display backlight and USB
are functional.
BRANCH=None
Change-Id: I2879f57db555753b280e785df3d2cc967c152f21
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/285545
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Remove duplicate board_discharge_on_ac() functions and create
CONFIG_CHARGER_DISCHARGE_ON_AC_CUSTOM for boards that have a
unique implementation of board_discharge_on_ac().
BUG=chrome-os-partner:42294
BRANCH=none
TEST=make -j buildall.
load on samus and test 'ectool chargecontrol discharge' forces
discharging on AC, and 'ectool chargecontrol normal' resumes normal
charging.
Change-Id: I2b7c04b9278d07748d6d41798ceab1a7e90684e4
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/284911
Reviewed-by: Randall Spangler <rspangler@chromium.org>
To avoid FIFO errors - the fifo becomes full will we wait for the AP
to read the vectors, increase the i2c speed between EC and AP.
Target 1Mhz, 400KHz observed due to a limitation of the Tegra I2C
controller.
BRANCH=smaug
TEST=Verify with analyzer that speed is now 400KHz.
The duty cycle is still not right.
Check that FIFO underrun do not happen during tests.
BUG=chrome-os-partner:40280,chrome-os-partner:39233,chrome-os-partner:39900
Change-Id: Id6c2dfb10c34a919ec99a58bc0082207f7748b7e
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/284613
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Removed USB enable/disable as it will be handled by
HOOK task as CONFIG_USB_PORT_POWER_SMART is enabled.
BUG=none
TEST=Verified on Acer EVT GPIO USB1_ENABLE and USB2_ENABLE value
changed when state switch between S3 and S5.
BRANCH=none
Change-Id: I85f2047c1a40aebf36743a17d353ff3bc481d867
Signed-off-by: li feng <li1.feng@intel.com>
Signed-off-by: Divya Jyothi <divya.jyothi@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/283593
Reviewed-by: Shawn N <shawnn@chromium.org>
I accidentally removed this when poking around with the SPS
driver. This adds it back as a separate file. Enabling
CONFIG_SPS_TEST will restore the "spstest" console command to use
for low-level driver tests.
Note that invoking it will replace any other registered SPS
handler.
BUG=chrome-os-partner:40969
BRANCH=none
TEST=manual
Connect the EC to the build host with an FTDI USB-to-SPI adapter.
On the EC console, invoke
spstest
Build and run the external ftdi_dongle test:
git clone sso://user/vbendeb/ftdi_dongle
cd ftdi_dongle/src
make
./examples/spiraw.py -l 10 -f 2000000
Change-Id: Ia6165e3be06d976c59c3e849349da0f7f5006f56
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/284943
Reviewed-by: Vadim Bendebury <vbendeb@google.com>
GPIO_INT_DSLEEP is useful on LM4 to save power when in deep sleep
by allowing us to disable clock to gpio blocks unless it's needed
as a wake source. The MEC and ST chips don't have this option, so
all gpio's can be used as wake source from deep sleep. Therefore
remove this flag from all boards where this flag doesn't do
anything to remove confusion.
BUG=none
BRANCH=none
TEST=make -j buildall
Change-Id: I4cb175431a22f100035a81b32e9367b510f4836e
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/284742
Reviewed-by: Shawn N <shawnn@chromium.org>
Mec1322 cannot distinguish between Power-on and reset condition.
MEC1322_EC_WDT_CNT was used to determine the power-on condition.
VBAT_POR cannot not be used to distinguish no battery condition.
All of the feautures that need support need to determine VCC1_REST
which is used for reset considion. lfw and main code use the same
condition.
When VCC1_RESET is asserted we need to set the image type to
RO image for sysjump to work correctly. This in turn will affect
Recovery mode,software sync and Flashrom. All of these conditions
were tested with this patch.
BUG=chrome-os-partner:40526
TEST=Recovery mode,Software Sync,Flashrom
BRANCH=None
Change-Id: I65f2aa9f56863597116b875ea436d4413887b92b
Signed-off-by: Divya Jyothi <divya.jyothi@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/283605
Reviewed-by: Shawn N <shawnn@chromium.org>
This commit changes the way in which tasks are started. Instead of
having all tasks marked as ready to run upon initialization, only the
hooks task is marked as ready to run. HOOK_INITs are now run at the
beginning of the hooks task. After the HOOK_INITs, the hooks task calls
back to enable the rest of the tasks, reschedules, and proceeds as
usual. This also allows the removal of checks for task_start_called().
BUG=chrome-os-partner:27226
BRANCH=None
TEST=Built and flash EC image for samus and verified that EC boot was
successful as well as AP boot. Additionally, verified that charging,
keyboard, tap-for-battery were all still functional.
TEST=make -j buildall tests
Change-Id: Iea53670222c803c2985e9c86c96974386888a4fe
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/283657
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Commit-Queue: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
This lets the RX interrupt handler configure the wire protocol
(clock polarity and phase) and SPS communication mode that it
would prefer.
BUG=chrome-os-partner:40969
BRANCH=none
TEST=make buildall
This is just a refactoring, since the sps_hc.c module is the only
thing that uses this (in one mode only). I tested it using
extra/ftdi_hostcmd and it still works.
Change-Id: I9ed26e9fa66de65e72f188184f4f3f41a5b5562a
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/284922
Reviewed-by: Randall Spangler <rspangler@chromium.org>
The "sps" console command declared in sps_hc.c is misleading. It
shouldn't be "sps", when it's actually part of the host command
protocol stuff.
This CL changes the command name to "spshc" instead. The command
just enables or disables SPS host commands. Note that because
there's no notification if something else calls
sps_unregister_rx_handler(), there's no way for the sps_hc.c
module to know whether it's still registered.
BUG=none
BRANCH=none
TEST=make buildall
Using a test program, such as extra/ftdi_hostcmd/, I can send
host commands to an EC attached via an FTDI USB-to-SPI adapter.
On the EC console, this:
spshc off
causes the test program to fail, and this:
spshc
causes it to work again.
Change-Id: Ie0edbde179b570f170ff9464313e5e33ab985f21
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/284942
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Remove board function callback on charge override timeout, since
the implementation should be common to all boards: send host event.
This function is called when a power swap fails during an issued
charge override and notifies the host so that it is aware that the
power swap did not succeed.
BUG=none
BRANCH=smaug
TEST=make -j buildall
Change-Id: Ia2a078a17aef6b302fd2b9fd21a5a92c628fd7db
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/284923
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Remove duplicate definitions of USB charger min current across
boards and make one set of defines for standard USB charger voltage
and minimum USB charger current.
BUG=none
BRANCH=smaug
TEST=make -j buildall
Change-Id: Ib842fafb317417c8de9a67d314fdde4c1e47ad9d
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/284956
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
When the SPI slave chip select is deasserted, it means that the
SPI master doesn't want to hear any more from the EC. We need to
clear any bytes left in the TX FIFO, so that the next SPI
transaction doesn't send those leftover bytes out.
Since the EC's SPI protocol for host commands uses software flow
control, those leftover bytes could screw up the messages. I
expanded a comment explaining how that works.
BUG=chrome-os-partner:40969
BRANCH=none
TEST=make buildall
And, with the EC connected to the build host via an FTDI USB-to-SPI
adapater, I used the extra/sps_errs/ test program to see the
original problem and that this CL fixed it:
cd extra/sps_errs
make
./prog -v
./prog -v -c 22
./prog -v
This sends a complete EC_CMD_HELLO message, then a truncated
message, then sends the whole message. Before this change to
sps.c, the third message response begins with the leftover bytes
from the aborted second message.
Bad third message:
Transfer(12) =>
03 64 01 00 00 00 04 00 a5 a5 a5 a5
Transfer(12) <=
a9 a8 a7 a6 f8 f8 f8 f8 f8 f8 f9 f9
^^ ^^ ^^ ^^
Good third message:
Transfer(12) =>
03 64 01 00 00 00 04 00 a5 a5 a5 a5
Transfer(12) <=
f8 f8 f8 f8 f8 f8 f8 f8 f8 f8 f9 f9
^^ ^^ ^^ ^^
Change-Id: Id6e431f91be0204921edee2f774b6c487966ddff
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/284746
Reviewed-by: Vadim Bendebury <vbendeb@google.com>
This adds another test program to use with the EC connected to
the build host via an FTDI USB-to-SPI adapater, This program
sends an EC_CMD_HELLO host command to the EC. Options exist to
display the bytes transferred over the SPI interface, and to
truncate the message before its complete, to see how the EC reacts.
BUG=chrome-os-partner:40969
BRANCH=none
TEST=make buildall
To try out the new test program:
cd extra/sps_errs
make
./prog
./prog -v
./prog -v -c 22
Change-Id: I1d370ecdbae047d9504bc6e5f73949d4e3aed9d9
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/284865
Reviewed-by: Vadim Bendebury <vbendeb@google.com>
A new private repo has been added, so prevent git from
complaining about it.
BUG=chromium:507445
BRANCH=none
TEST=make build all; git status
Nothing breaks, "git status" stops pointing out the new
subdirectory.
Change-Id: Ibf1fbc7504fb6bbb9df7d6ddf0efda9a632e39b6
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/284874
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Was comparting a int16_t with 0x8000 leading to:
error: comparison of constant 32768 with expression of
ec-utils-0.0.1-r2377: type 'int16_t' (aka 'short') is always false
(Builder: Chromium OS (x86) Asan (stats) 7005)
BRANCH=smaug
TEST=On Smaug check that ectool does report invalid temperature
when EC returns 0x8000.
Check the temperature is correct when the EC returns a valid
temperature.
BUG=chromium:508674
Change-Id: I2a1414cf7bf018ecaa7ff8dd37c76804de4bce52
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/284673
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Reviewed-by: Achuith Bhandarkar <achuith@chromium.org>
Enable code to use BMI150 FIFO and interrupt support on Smaug
BUG=chrome-os-partner:39900
BRANCH=smaug
TEST=Check fifo is working, interrupts are enabled.
Change-Id: Ifc07da793d3ece4806895db4aff5d880c0f3d9b0
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/274228
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Add FIFO support, where bmi160 hardware FIFO is copied in local fifo.
Add rudimentary support for single/double tap and lift detection.
BUG=chrome-os-partner:39900
BRANCH=smaug
TEST=Check on F411 that FIFO data is retrieved and correct.
Check on Smaug as well, with proper kernel the collect the FIFO:
- check that increasing sampling_frequency we are collecting
the FIFO less often
- check no frames are lost.
- check tap/lift interrupts are working
- if latency is less than 100ms, check we are collecting much faster.
Change-Id: Ic2317c27fad0ef31dacd6e18cd5f71ccd2cec807
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/274227
This adds a range of (proto v3) host commands to use for
experimental/one-off feature development without constantly
updating include/ec_commands.h
BUG=none
BRANCH=none
TEST=make buildall
This doesn't implement any new commands. It just adds some new constants.
Change-Id: I1d7b829dec9fa847e16f92d35c78446cc5f34cc5
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/284408
Reviewed-by: Randall Spangler <rspangler@chromium.org>
This enables the feature that lets the Cr50 receive host commands
via the SPI (slave) interface.
BUG=chrome-os-partner:40969
BRANCH=none
TEST=make buildall
CQ-DEPEND=CL:283998
This CL also adds a test example in the extra/ftdi_hostcmd/
directory. To use it, you need the Cr50 attached to the build
host via an FTDI USB-to-SPI adapter.
cd extra/ftdi_hostcmd
make
./test_cmds
Change-Id: Ia719b1c898afc45b3105a9cd573a8492178d9be2
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/284001
BRANCH=smaug
BUG=chromium:506101
TEST=On samus, check we can set the offset and are taken into account.
Check the bias added is correct in the measurements.
Change-Id: I6cf06271ac080a47a008a342d9d108fd302241cc
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/283164
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Add code to store bias from AP at boot and correct
raw data from accelerometer on the fly.
Also return the raw data on 16 bits, as recommned by sysfs.
BRANCH=smaug
BUG=chromium:506101
TEST=check set and get offset works fine.
Check value from accelerometer are sane (on Samus).
Change-Id: Ia62f02aadb9e11988edf0049a0cfee817641db88
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/283163
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Add code to store bias from AP at boot and correct
raw data from accelerometer on the fly.
Also return the raw data on 16 bits, as recommned by sysfs.
BRANCH=smaug
BUG=chromium:506101
TEST=check set and get offset works fine.
Check value from accelerometer are sane (on Samus).
Change-Id: I2ad4ce601665b497527dc8c6acb6e7d398366afe
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/283162
Move calibration in the EC to returns raw value with offset already
applied, as recommended by iio interface.
BRANCH=smaug
TEST=On Samus, with kernel change CL:283103
Check raw value are returned properly.
BUG=chromium:506101
Change-Id: I3dcb4f2fcfff35639e3bfdcc6c1468bdb5e53c45
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/283161
Reviewed-by: Alec Berg <alecaberg@chromium.org>
All boards in ToT have the same RO configuration.
Boards which define CONFIG_FLASH_PSTATE_BANK have pstate following RO.
BRANCH=none
BUG=chrome-os-partner:22990
TEST="git grep" to see that none of the affected functions are called.
Change-Id: Ie1eb9a726e1fa157852b0c55d474c9b4587c41f0
Signed-off-by: Myles Watson <mylesgw@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/273908
Reviewed-by: Randall Spangler <rspangler@chromium.org>
rename setup_openocd -> flash_openocd
refactor so that flash_npcx and flash_lm4 set OCD_CMDS and call flash_openocd
BRANCH=none
BUG=chrome-os-partner:22990
TEST=run flash_ec before and after and compare the sequence of calls to
dut-control and the command-line args to openocd
tested with ryu (non-lm4), samus, link, npcx_evb, and peppy
Change-Id: I7a05e3219d4b324bcf19a20f86b149f8e3377465
Signed-off-by: Myles Watson <mylesgw@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/273907
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Avoid duplicating servo configurations for every chip.
BRANCH=none
BUG=chrome-os-partner:22990
TEST=None. This is an intermediate step to make it clear what's happening.
CQ-DEPEND=CL:273950
Change-Id: I448543b6ab9d39423955e8d2589b6035c59e838a
Signed-off-by: Myles Watson <mylesgw@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/273906
Reviewed-by: Randall Spangler <rspangler@chromium.org>
This adds a module that attaches to the SPS driver to process
host commands delivered over the SPI slave interface.
BUG=chrome-os-partner:40969
BRANCH=none
TEST=make buildall
This feature is not yet enabled, so there's nothing new to test.
That will come next.
Change-Id: If57a6fce698a7eb050e2a68b7f4d18d8b0e2956f
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/284010
Reviewed-by: Randall Spangler <rspangler@chromium.org>
1. Added new config option CONFIG_USB_PD_TRY_SRC
2. Added pd_try_source_enable global flag with console command
3. Added bit to pd.flags to indicate Try.SRC states are active
BUG=chrome-os-partner:39724
TEST=Manual samus to samus with the Try.SRC enabled on both and just
one samus. Tested Samus to Honeybuns and Samus to Zinger connections.
BRANCH=TOT
Change-Id: Ifa5d5d82e443f376e546aaf852ff24d92ef04d72
Signed-off-by: Scott Collyer <scollyer@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/282052
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Tested-by: Alec Berg <alecaberg@chromium.org>
1. Add flash control module for emulation board.
2. Fix system jump for Andes core.
3. Change the physical size of the flash on the chip to 256KB.
note:
1. Only IT839x series supports flash write protect by registers.
2. Static DMA method of flash code only for IT839x series and IT838x Dx.
Signed-off-by: Dino Li <dino.li@ite.com.tw>
BRANCH=none
BUG=none
TEST=1. console command flashwp and flashinfo
1-a. flashwp enable
1-b. WP asserted and reboot
1-c. flashinfo RO protected now
1-d. WP deasserted and reboot
1-e. No protected
1-f. flashwp disable
1-g. WP asserted and reboot
1-h. No protected
2. console sysjump and sysinfo
2-a. sysjump rw
2-b. jumping to image RW
2-c. sysinfo, Copy : RW, Jumped : yes
2-d. sysjump ro
2-e. jumping to image RO
2-f. sysinfo, Copy : RO, Jumped : yes
3. RO/RW firmware image test
3-a. sysjump rw
3-b. use console command "eflash" to erase RO region,
erase OK and system still work.
3-c. reflash firmware
3-d. sysjump rw, sysjump ro
3-e. use console command "eflash" to erase RW region,
erase OK and system still work.
Change-Id: I7666a095e73026a02fb812e5143bc5172ab713e8
Reviewed-on: https://chromium-review.googlesource.com/271390
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Commit-Queue: Dino Li <dino.li@ite.com.tw>
Tested-by: Dino Li <dino.li@ite.com.tw>
Board jerry was removed from the list in CL 276524. The board share the same
overlay as pinky. So ideally user can call flash_ec with board set to pinky.
This applies to other veyron boards in BUG 505003 as well.
However, servo in the lab runs on ToT, and it only updates firmware of the dut
by calling flash_ec with board name retrieved from the overlay file. Also, lab
has a tool to check the servod's board and the dut's board. That is, if we
change servod to return board name pinky for servo connected to a jerry dut,
the lab script will raise a warning that the servod is running with a wrong
board.
Before we have a good design to really address the issue, I'd like to add jerry
back to flash_ec so the board can run FAFT in the lab.
BUG=chromium:505003
BRANCH=None
TEST=None
Change-Id: I155e79710f2731701af0acdfeab6089701cf52a8
Reviewed-on: https://chromium-review.googlesource.com/283494
Tested-by: Dan Shi <dshi@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Commit-Queue: Dan Shi <dshi@chromium.org>
The SPS (SPI Slave) driver handles incoming traffic from the SPI
master. This abstracts the basic hardware functions into a clean
API so that the response to the SPI bytes can be put into
separate files.
BUG=chrome-os-partner:40969
BRANCH=none
TEST=make buildall
If CONFIG_SPI is not defined, incoming SPI traffic is completely ignored.
Even when it's enabled, nothing is reacting to the traffic so
incoming SPI bytes return 0xFF bytes to the master (SPI traffic
is always bidirectional).
Change-Id: I9bbcebc9c5223b942362200fe43a11ac57dfff40
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/283581
Reviewed-by: Sheng-liang Song <ssl@chromium.org>
This provides a way to experiment with or support random
functionality not specifically related to the normal EC
operation. With this, we can use a standard host command to pass
opaque data blobs between the AP and EC without specifying a
particular meaning to them.
BUG=chrome-os-partner:40969
BRANCH=none
TEST=make buildall
Nothing in the normal EC usage sends these messages. I have a
test/example program coming soon.
Change-Id: I77fe434cbd9151e4c2c22bc36d1ed6063d3bf940
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/283070
Reviewed-by: Randall Spangler <rspangler@chromium.org>
