This change implements logic for installing
endorsement certificates in the RW section.
The endorsement certificates are initially
provisioned in a fixed RO flash region and
are copied in the RW TPM data region (once
this region has been initialized).
Also add code for reading from the info bank,
which is where the endorsement seed is
initially stored.
BRANCH=none
BUG=chrome-os-partner:43025,chrome-os-partner:47524
BUG=chrome-os-partner:50115
TEST=TCG tests running
Change-Id: Id8c16d399202eee4ac0c4e397bdd29641ff9d2f3
Signed-off-by: nagendra modadugu <ngm@google.com>
Reviewed-on: https://chromium-review.googlesource.com/362402
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Commit-Queue: Vadim Bendebury <vbendeb@chromium.org>
Tested-by: Vadim Bendebury <vbendeb@chromium.org>
There are three timers, each with four capture/compare (CC)
registers. The timer code uses 3 CC registers from one timer.
Use macros for the defines, so that it is more obvious which
timer and which register are being used.
TEST=make BOARD=hadoken
BRANCH=NONE
BUG=None
Change-Id: Icb058d9717800a87b394270eef38a3a744a13b7d
Signed-off-by: Myles Watson <mylesgw@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/361793
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Levi Oliver <levio@google.com>
Flush our UART buffer to ensure that we don't miss prints when we reboot
the EC.
BUG=chrome-os-partner:55539
BRANCH=None
TEST=Manual on kevin, issue cold reboot host command, verify that
"Executing host reboot command" is seen on console.
Change-Id: I96d5687b413ba4f603e3e7845b5cbba1c2d65efa
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/362681
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Old kevin / gru boards are no longer supported by our current GPIO
configuration and must revert a CL to boot properly. Detect if old
boards are used with an incompatible config and warn users of this fact
by spamming the EC console and blinking the LED red.
BUG=chrome-os-partner:55561
BRANCH=None
TEST=Boot new kevin, verify no console spam or LED blinkage is seen. Verify
old kevin + old gru spam the console and blink LED.
Change-Id: I6d49720f760a6bef2bb3db6872857a5f61259e06
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/362653
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
The tpm firmware version register should report the current RW image's
version, not the RW_A.
BRANCH=none
BUG=chrome-os-partner:55145
TEST=verified that tpm firmware version reported by coreboot on the AP
console matches the version running on the device, for both RW_A
and RW_B.
From coreboot console log on two different runs:
Firmware version: RO: 84e2dde7 RW: cr50_v1.1.4943-f81a901
Firmware version: RO: 84e2dde7 RW_B: cr50_v1.1.4943-f81a901
Change-Id: I43f5432e44e38dbf9b42750dd2042a0f005bcbfb
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/362612
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
We had been putting the NVMEM flash where the boot rom would
expect to find RO_B, preventing us from ever being able to update
the bootloader.
With this CL, we're rearranging the flash to support both RO_A
and RO_B. The current flash layout now looks like this:
0x40000 RO_A
0x44000 RW_A
0x7c000 TOP_A
0x80000 RO_B
0x84000 RW_B
0xbc000 NVMEM
0xbffff <end of flash>
BUG=chrome-os-partner:44803
BRANCH=none
TEST=make buildall, also manual tests on Cr50 boards
First, check that our current process still works:
make BOARD=cr50 CR50_RO_KEY=cr50_rom0-dev-blsign.pem.pub
spiflash -i -v build/cr50/ec.hex
Yep, it does, but that only produces RO_A, not RO_B.
To test the dual RO behavior, I used prebuilt RO_A and RO_B blobs
for the bootloaders, signed using Marius' new scheme.
Build the unsigned image, then sign it using Vadim's scripts:
make BOARD=cr50 -j30
~/bin/bs hex
We'll garble various bits of the full image to invalidate each of
the four RO/RW/A/B parts.
Find lines common to both ROs and common to both RWs:
sort B1*.hex | uniq -c | grep ' 2 ' | \
awk '{print $2}' | sort > tmp.ro2
sort build/cr50/RW/ec.RW*.signed.hex | uniq -c | grep ' 2 ' | \
awk '{print $2}' | sort > tmp.rw2
ro=$(diff tmp.ro2 tmp.rw2 | grep '<' | head -1 | awk '{print $2}')
rw=$(diff tmp.ro2 tmp.rw2 | grep '>' | head -1 | awk '{print $2}')
Double-check to be sure we don't have any false matches:
grep -l $ro build/cr50/RW/ec.RW*.signed.hex B1_*.hex
grep -l $rw build/cr50/RW/ec.RW*.signed.hex B1_*.hex
The pre-signed RO_A image is older than RO_B, but both have the
same epoch/major/minor, which is all that the bootrom checks for.
It doesn't look at the timestamp.
The RW_A is older than RW_B because of the sequential signing
process. The RO bootloaders will check their timestamp, so RW_B
should be preferred.
RO_A RO_B RW_A RW_B
good good good good
cat build/cr50/RW/ec.RW*.signed.hex B1_*.hex > foo.hex
spiflash -v -i foo.hex
jump @00040400
jump @00084000
=> boots RO_A -> RW_B
RO_A RO_B RW_A RW_B
good good good bad
cat build/cr50/RW/ec.RW*.signed.hex B1_*.hex > foo.hex
ln=$(grep -n $rw foo.hex | awk -F: 'NR==2 {print $1}')
sed -i "${ln}d" foo.hex
spiflash -v -i foo.hex
jump @00040400
jump @00044000
=> boots RO_A -> RW_A
RO_A RO_B RW_A RW_B
bad good good good
cat build/cr50/RW/ec.RW*.signed.hex B1_*.hex > foo.hex
ln=$(grep -n $ro foo.hex | awk -F: 'NR==1 {print $1}')
sed -i "${ln}d" foo.hex
spiflash -v -i foo.hex
jump @00080400
jump @00084000
=> boots RO_B -> RW_B
RO_A RO_B RW_A RW_B
bad good good bad
cat build/cr50/RW/ec.RW*.signed.hex B1_*.hex > foo.hex
ln=$(grep -n $ro foo.hex | awk -F: 'NR==1 {print $1}')
sed -i "${ln}d" foo.hex
ln=$(grep -n $rw foo.hex | awk -F: 'NR==2 {print $1}')
sed -i "${ln}d" foo.hex
spiflash -v -i foo.hex
jump @00080400
jump @00044000
=> boots RO_B -> RW_A
Yay.
Now make sure RW_A and RW_B can be updated using usb_updater.
\rm -rf build
make BOARD=cr50 -j30
~/bin/bs
./extra/usb_updater/usb_updater build/cr50/ec.bin
I'm running RW_A, it updates and reboots into RW_B. Good.
reboot 5 times, and it reverts to RW_A.
Power cycle and it goes to RW_B again.
Update to RW_A.
\rm -rf build
make BOARD=cr50 -j30
~/bin/bs
./extra/usb_updater/usb_updater build/cr50/ec.bin
I'm running RW_B, it updates and reboots into RW_A. Good.
reboot 5 times, and it reverts to RW_B.
Power cycle and it goes to RW_A again.
Cool.
Change-Id: I6c1689920de06c72c69f58ad2ef1059d9ee0d75f
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/362521
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
When a kevin, gru, or reef are attached to the host machine using a
suzyQ, they can use CCD to update the AP or EC using flashrom. To use
suzyQ you have to specify raiden_debug_spi as the flashrom programmer.
This change adds support to flash_ec for using the right programmer to
update with CCD over suzyQ instead of servo.
BUG=chrome-os-partner:50701, chrome-os-partner:50712
BRANCH=none
TEST=make sure "util/flash_ec --BOARD=kevin --raiden" updates the EC
when CCD is enabled
Change-Id: Ie63337b9689c68aa60163d7e54c5ebefa97b4e21
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/344427
Reviewed-by: Randall Spangler <rspangler@chromium.org>
This will be used to hack around code that only works on proto.
The earlier method of attempting to use board ID to determine
codepath worked to a limited extent, but fell short due to pin
swappings. So the dream of having a single binary that would work
on multiple board revisions died, and now if someone wants to build
for an old proto board they need to set this #define to 1.
BUG=chrome-os-partner:54947
BRANCH=none
TEST=tested with upcoming patches in this series
Change-Id: I5468c252e5401d69b108c75fa00b3dfbbcf77c22
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/360949
Reviewed-by: Shawn N <shawnn@chromium.org>
During initialization the NvMem module looks for either a valid
partition or that the NvMem area is fully erased. If neither of
these two conditions were found, then it was only returning an
error code and logging a message to the console.
This CL modifies nvmem_init() so that if the error case as described
above is detected, then it will call nvmem_setup() which will
create two valid partitions. In addition, the setup function
erases all of the existing data in the NvMem space.
Enhanced the unit test that deals with both partitions being
corrupted so that it verifies the version numbers are correct
and that all user buffer data is set to 0xff.
BUG=chrome-os-partner:55536
BRANCH=None
TEST=Manual
Executed make runtests TEST_LIST_HOST=nvmem and verifed that all
tests passed.
Change-Id: Ib932e02f15bd1aad7811032a12d826c76476e53f
Signed-off-by: Scott <scollyer@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/362448
Commit-Ready: Vadim Bendebury <vbendeb@chromium.org>
Tested-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
The USB controller should disable the PHY itself when usb is released,
but from the power tests I ran it does not. This change adds a call in
usb_release to deactivate the PHY.
It looks like having the AP on vs off also makes a difference in power
consumption. I am looking into that now, but until that is resolved turn
of the AP off while testing this USB change to see the effects on power.
BUG=chrome-os-partner:54331
BRANCH=none
TEST=manual
Without deactivating the PHY put cr50 into deep sleep on gru.
run 'reboot ap-off'
measure pp3300_haven_mw and it is around 4.5mW
Add deactivating the PHY during usb_release.
Put cr50 into deep sleep
run 'reboot ap-off'
measure the power and the average should be around 2mW
Change-Id: I16e6885a4e40c78e81d9bbc42c9af79e5f55047e
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/362159
Commit-Ready: Dan Shi <dshi@google.com>
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
This script is more flexible for updating multiple targets,
including servo_v4, servo_micro, and sweetberry.
The command takes a json config file that specifies
flash layout, USB ID, and size.
BUG=chromium:571476
TEST=./fw_update.py -b servo_v4.json -f ec.bin; both RW, RO
BRANCH=none
Change-Id: Ic9dcee2c23484bb28c8bfaf1882c578314534116
Signed-off-by: Nick Sanders <nsanders@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/361835
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
The clock() function was introduced to provide free running clock for
the TPM2 library, which expects this clock to run with a millisecond
resolution.
This patch fixes the bug where the function in fact was returning the
clock running at a microsecond resolution.
BRANCH=none
BUG=chrome-os-partner:43025,chrome-os-partner:47524
BUG=chrome-os-partner:50115
TEST=with the appropriate modification of the user of this function
all lockout related TCG tests pass.
Signed-off-by: nagendra modadugu <ngm@google.com>
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/361180
(cherry picked from commit b4e78b309900402499b8742199fb4536570d3000)
(cherry picked from commit fefaa02a4f2c807a3ad50137bd7dba7f5f081c31)
Change-Id: Ic02fffca610426d22e58609eb8c3693aec96ad5c
Reviewed-on: https://chromium-review.googlesource.com/362118
TCG test CPCTPM_TC2_2_22_02_08 installs an RSA key
for which p does not divide the modulus, and subsequently
the test is expected to fail accordingly.
This change adds the check necessary to pass this test --
a check that p divides N.
Also removed dangling function declaration for bn_mul().
BRANCH=none
BUG=chrome-os-partner:43025,chrome-os-partner:47524
BUG=chrome-os-partner:50115
TEST=TCG test CPCTPM_TC2_2_22_02_08 passes consistently
Signed-off-by: nagendra modadugu <ngm@google.com>
Reviewed-on: https://chromium-review.googlesource.com/360968
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Commit-Queue: Vadim Bendebury <vbendeb@chromium.org>
(cherry picked from commit c4430ecac8f77a05ac4071679de1535e0da2779e)
(cherry picked from commit 832d04b5b8cebf702d2ec00051615f827d2d16e1)
Change-Id: If2ffc6260ae848d75e93263a37e84f0ed7d301a0
Reviewed-on: https://chromium-review.googlesource.com/362117
Commit-Ready: Vadim Bendebury <vbendeb@chromium.org>
Tested-by: Vadim Bendebury <vbendeb@chromium.org>
The manufacturing status check verifies if the proper certificates are
found in the device NV RAM. This check can not succeed unless NV RAM
metadata is initialized by calling _TPM_Init().
If the check shows that the device has not been through manufacturing
sequence yet, TPM_Manufacture() needs to be invoked to make sure that
all relevant TPM structures are initialized and properly stored in NV
RAM. _TPM_Init() needs to be invoked again after that.
BRANCH=ToT
BUG=chrome-os-partner:43025
TEST=restarting Kevin device with pre-manufactured CR50 takes it
through factory initialization on every reboot. Restarting Kevin
once TPM is through manufacturing process shows that the
previously saved rollback counters are preserved.
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/361093
Reviewed-by: Nagendra Modadugu <ngm@google.com>
(cherry picked from commit 61a0fe734e808d1dbdf56fb6023e04adf66553b3)
(cherry picked from commit 3207a57fb2f5957b6e833d9ab1f9ea46021c5e1e)
Change-Id: I80b69f2c4b8d0e4cca154db510867df39c707ce2
Reviewed-on: https://chromium-review.googlesource.com/362084
For now the presence of both RSA and EC certificates at fixed NVRAM
indices is considered evidence of TPM being through manufacturing.
BRANCH=none
BUG=chrome-os-partner:50645
TEST=with the rest of the patches applied TPM manufacturing status is
properly detected at startup.
Change-Id: Iff3861603272cdfb58ebc523458c114685b2429f
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/362351
Reviewed-by: Marius Schilder <mschilder@chromium.org>
This change updates the ecc and rsa key generation templates.
Due to crosbug.com/p/55260 in which the TPMT_PUBLIC template is
truncated during personalization, ecc generation requires a
workaround.
For RSA, allow the standard template to be used even on development
builds.
BRANCH=none
BUG=chrome-os-partner:43025,chrome-os-partner:47524
BUG=chrome-os-partner:50115,chrome-os-partner:55260
TEST=test full personalize + cros_ack verify cert flow
Signed-off-by: nagendra modadugu <ngm@google.com>
Reviewed-on: https://chromium-review.googlesource.com/360441
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Commit-Queue: Vadim Bendebury <vbendeb@chromium.org>
Tested-by: Vadim Bendebury <vbendeb@chromium.org>
(cherry picked from commit db5a1ca8a40be9bf7e741637cd8d7f15f520ab11)
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
(cherry picked from commit b6620239bb7c4f5900051677f40f161c0a853a94)
Change-Id: I1af83f1ec86e7ee4d325a4b7aabe03ce08c4108b
Reviewed-on: https://chromium-review.googlesource.com/362142
Reviewed-by: Nagendra Modadugu <ngm@google.com>
The TPM2 wrapper library does not initialize the
size of an output buffer length prior to calling
into cr50/tpm2. This results in arbitrary failures
depending on memory layout.
Force the buffer length unseen, though this should
be fixed in the TPM2 library.
BRANCH=none
BUG=chrome-os-partner:43025,chrome-os-partner:47524
BUG=chrome-os-partner:50115,chrome-os-partner:55260
TEST=test full personalize + cros_ack verify cert flow
TEST=CPCTPM_TC2_2_20_02_03 passes, which was consistently failing
Signed-off-by: nagendra modadugu <ngm@google.com>
Reviewed-on: https://chromium-review.googlesource.com/360908
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
(cherry picked from commit 635cb7ada25e76e504087916364e2db08a2133ab)
Change-Id: I90e9b4d76986ffa27acc944e48afc2efaadad7cd
Reviewed-on: https://chromium-review.googlesource.com/362116
Commit-Ready: Vadim Bendebury <vbendeb@chromium.org>
Tested-by: Vadim Bendebury <vbendeb@chromium.org>
Primes generated for RSA keys need to hold the following
property (public_exponent mod p) > 1 in order for the
private exponent to exist. This change adds this check
for the public exponent RSA_F4 (65537).
BRANCH=none
BUG=chrome-os-partner:43025,chrome-os-partner:47524
BUG=chrome-os-partner:50115,chrome-os-partner:55260
TEST=test full personalize + cros_ack verify cert flow
Signed-off-by: nagendra modadugu <ngm@google.com>
Reviewed-on: https://chromium-review.googlesource.com/360662
Reviewed-by: Marius Schilder <mschilder@chromium.org>
Reviewed-by: Bill Richardson <wfrichar@google.com>
(cherry picked from commit 1c37f84ae7fae9f5841421447c7f235790ab6a93)
(cherry picked from commit b2c1678b27c79a2c93f5519e00161243fa0a5d88)
Change-Id: I87bd898cc3750bf1e492bc263edb6eac1edf2a17
Reviewed-on: https://chromium-review.googlesource.com/362115
Commit-Ready: Vadim Bendebury <vbendeb@chromium.org>
Tested-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
The modinv logic shouldn't reduce modulo MOD
on a carry condition. Instead, just use more
space to hold the carry bit.
Also use full size buffers for all variables.
BRANCH=none
BUG=chrome-os-partner:43025,chrome-os-partner:47524,chrome-os-partner:50115
TEST=unit tested
Signed-off-by: nagendra modadugu <ngm@google.com>
Reviewed-on: https://chromium-review.googlesource.com/360248
Reviewed-by: Marius Schilder <mschilder@chromium.org>
Tested-by: Marius Schilder <mschilder@chromium.org>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
(cherry picked from commit 3f4e131daef04db5c990bb4532bb67ee9e58c02b)
(cherry picked from commit 485b02a17ecdd3c52210fd90ff29b4f1b829a47a)
Change-Id: I8d4f78966bfe15f0739c9de23f5a12685a65aabb
Reviewed-on: https://chromium-review.googlesource.com/362113
Commit-Ready: Vadim Bendebury <vbendeb@chromium.org>
Tested-by: Vadim Bendebury <vbendeb@chromium.org>
The name BIGNUM collides with a namesake struct
in openssl. It would be convenient to write
test code that compares results between openssl
and dcrypto, hence this rename.
Also rename some #defines that conflict with
openssl names.
CQ-DEPEND=CL:*270476
BRANCH=none
BUG=chrome-os-partner:43025,chrome-os-partner:47524,chrome-os-partner:50115
TEST=build succeeds
Signed-off-by: nagendra modadugu <ngm@google.com>
Reviewed-on: https://chromium-review.googlesource.com/360346
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
(cherry picked from commit a15b495497728a6b212bd87e92f6ba5ba463f985)
Change-Id: Ic53ce805cfcc591c68fbc1ef90ff2f92cec973a6
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/362112
Reviewed-by: Nagendra Modadugu <ngm@google.com>
BRANCH=None
BUG=None
TEST=Manual
- Connect handshake and gpio test lines between th
and dut
- Build tests
- run 'cat /dev/ttyACM0' in one terminal
- run 'cat /def/ttyACM1' in another
- Flash boards
- All test results print their test name followed
by a space and and integer error code
Change-Id: If52e9b50705779b3a291e2d0f6b0721a5b6197d8
Reviewed-on: https://chromium-review.googlesource.com/359988
Commit-Ready: Chris Chen <twothreecc@google.com>
Tested-by: Chris Chen <twothreecc@google.com>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
This copies the generic USB update code into common
so it can be used on other platforms. There should be
no functional change. cr50 folks want no change to their
code so vbendeb@chomium.org will refactor this back
together at a later date.
BUG=chromium:571476
TEST=none
BRANCH=none
Change-Id: I710afb22940013e7db5d8694898b90c0ae245777
Signed-off-by: Nick Sanders <nsanders@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/362131
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
In certain test scenarios the tpm task is hogging all resource and
causes watchdog resets. Let's kick the watchdog in every loop, Long
calculations already have watchdog kicking in place.
BRANCH=ToT
BUG=none
TEST=tests executed in rapid succession do not cause watchdog resets
any more.
(cherry picked from commit de8fb11bfd07d3fea2048b6848b8a183c31e2580)
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/360229
Reviewed-by: Marius Schilder <mschilder@chromium.org>
Tested-by: Marius Schilder <mschilder@chromium.org>
Change-Id: Ifaad6f9b4af2218f601412a36a075b4b4275d56f
Reviewed-on: https://chromium-review.googlesource.com/362170
Let's not force the linux kernel description format on cherry picked
patchs, especially since this check sometimes gets false positive, and
since this formwat is not used in the ec codebase.
BRANCH=none
BUG=none
TEST=no more annoying error reports on cherry-picked patches
Change-Id: I903bb87c48998932bc9308245d158f212a57fdd1
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/362074
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
The SHA config register should be cleared, so that
only required bits are set on init().
Doing so ensures that previous settings that used
the engine in a different mode, e.g HMAC, do not
survive.
BRANCH=none
BUG=chrome-os-partner:43025,chrome-os-partner:47524
TEST=build succeeds; tpmtest.py tests pass; manufacture works
(cherry picked from commit 9b3619ddd7304359ee17e243923f1e47c925cb21)
Signed-off-by: nagendra modadugu <ngm@google.com>
Reviewed-on: https://chromium-review.googlesource.com/359418
Reviewed-by: Marius Schilder <mschilder@chromium.org>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Commit-Queue: Vadim Bendebury <vbendeb@chromium.org>
Tested-by: Vadim Bendebury <vbendeb@chromium.org>
Change-Id: If5a79af06ea7512f19775a2f34d741b144f211f7
Reviewed-on: https://chromium-review.googlesource.com/358982
Commit-Ready: Vadim Bendebury <vbendeb@chromium.org>
In order for the vstore to be unlocked one needs to enable
the CHIPSET_RESET_HOOK. Do that for reef.
BUG=chrome-os-partner:55471
BRANCH=None
TEST=Able to boot and reboot without getting vboot hash saving
errors. Also am able to see the assertion/deassertion messages
on the console.
Change-Id: I94a41a08ad8649423988372607835da01ec12b8b
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/362001
Reviewed-by: Shawn N <shawnn@chromium.org>
Different actions need to be taken on PLTRST_L depending on
if it is asserted or deasserted. The vstore module needs to
reset its locks when PLTRST_L is asserted (host is in reset).
The interrupt was previously on occurring on a deassertion of
PLTRST_L (rising edge). That's not conducive for handling
actions which are required for assertion (falling edge).
Lastly, fix the CONFIG_CHIPSET_RESET_HOOK logic to be
called when PLTRST_L is asserted.
BUG=chrome-os-partner:55471
BRANCH=None
TEST=Able to boot and reboot without getting vboot hash saving
errors. Also am able to see the assertion/deassertion messages
on the console.
Change-Id: I70eac3309a5876de775ec5c34dab2e9aa8bbb42c
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/362000
Reviewed-by: Shawn N <shawnn@chromium.org>
usb-stream is used by USB updater as well as uart
forwarding. Add parameter for custom USB class define.
BUG=chromium:571476
TEST=builds
BRANCH=none
Change-Id: Id6294709de0c5408b10ed366b261be1bc7da7767
Signed-off-by: Nick Sanders <nsanders@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/361832
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
This allows us to specify the polarity of the alert signal for
each TCPC chip onboard, even if we have multiple instances of
the same chip.
BUG=none
BRANCH=none
TEST=built and booted on reef
Change-Id: I06a58c4e26892843243e8e98f2c86c6d3a696eb1
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/360948
Reviewed-by: Shawn N <shawnn@chromium.org>
MODULE_SHI is used for the SPI master interface pins, so don't
reconfigure those. Instead manually configure the SHI pins using the
appropriate DEVALT bit.
BUG=chrome-os-partner:54328
BRANCH=None
TEST=Manual on kevin. Verify SHI continues to function on cold boot,
sysjump and resume from S3. Verify SPI sensors now function on resume
from S3 - `accelinit 0` succeeds.
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: I63f028968f3d0dbc9d7ca7dacc70c9c399f7a180
Reviewed-on: https://chromium-review.googlesource.com/362061
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Caesar Wang <wxt@rock-chips.com>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Mulin Chao <mlchao@nuvoton.com>
* Remove GPIO USB endpoint to make room for update endpoint.
* Change GPIO mapping slightly to support servo micro v2.
BUG=chromium:571477
BRANCH=None
TEST=run servod, see new controls.
Change-Id: Id3b85b4c77b8f21afd9636b2ee459ace6f42f68e
Reviewed-on: https://chromium-review.googlesource.com/361383
Commit-Ready: Nick Sanders <nsanders@chromium.org>
Tested-by: Nick Sanders <nsanders@chromium.org>
Reviewed-by: Todd Broch <tbroch@chromium.org>
Having uart0 RX enabled can cause serious issues. This change adds a
config option to disable uart0 rx no matter what.
BUG=none
BRANCH=none
TEST=On B2 check that the ultradebug console is now read only
Change-Id: Icaec6954ffd3cbf0fda3f53581f6e4020d555267
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/361976
Commit-Ready: Vadim Bendebury <vbendeb@chromium.org>
Tested-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Programmable Peripheral Interconnect is a shared resource.
This CL adds code for allocating PPIs to devices.
BUG=None
BRANCH=None
TEST=Modify the I2C code to use this PPI allocation code and test
I2C communication (using experimental MXT touch controller code)
Change-Id: I8ec27867d041982ef18e8515d6434c5de2c189c5
Signed-off-by: Myles Watson <mylesgw@google.com>
Reviewed-on: https://chromium-review.googlesource.com/361405
Commit-Ready: Myles Watson <mylesgw@chromium.org>
Tested-by: Myles Watson <mylesgw@chromium.org>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Levi Oliver <levio@google.com>
The battery on kevin apparently requests 0A / 0V when extremely low, so
ignore this request and apply the pre-charge current.
BUG=chrome-os-partner:55416
BRANCH=None
TEST=Verify Kevin powers on with dead battery and battery charges as
expected.
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: I224f8ccd4f1d70d3a0f6f6e940fa6cbd80997fef
Reviewed-on: https://chromium-review.googlesource.com/361994
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Pre-charge vs fast-charge mode depends on battery voltage relative to
VSYS. Rather than checking battery voltage (which may change), set
pre-charge and fast-charge currents whenever charger_set_current() is
called.
BUG=chrome-os-partner:55416
BRANCH=None
TEST=Manual on kevin. Verify system continues to boot with no battery.
Attach depleted battery, run "battery" and verify charger current is
~200 mA.
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: I68c06108c6d85ceede396294bedd1a017ddddd52
Reviewed-on: https://chromium-review.googlesource.com/361993
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
During pre-charge, batteries may request < 512 mA. Allow battery
charging at this low current, and only apply the 512 mA floor when no
battery is present.
BUG=chrome-os-partner:54821
BRANCH=None
TEST=Manual on kevin. Verify system continues to boot with no battery.
Attach depleted battery, run "battery" and verify charger current is
~200 mA.
Change-Id: Ia10e732a6b21587917ffa5e34035507f5be74dd3
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/361589
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
There was a mistake in the initial driver implementation
regarding the MDAC field in the measure register (address 0x04).
The header file and associated code defined this 6 bit field
to be the upper 6 bits of the 8 bit register. However, the
data sheet for both rev A and B silicon show this field as
being the lower 6 bits of this register.
In addition, when using this threshold to distinguish between
a Rd and Ra attach, the threshold test logic was backwards.
If the threhold bit is set, then it means the voltage is
higher than the 200mV setting and should indicate a Rd attach.
BUG=chrome-os-partner:54790
BRANCH=none
TEST=manual
Tested with Anker TypeC hub using known polarity (CC1). Previously,
would see CC2 be selected as the active polarity. This resulted
in USB PD state machine getting stuck in SRC_DISCOVERY due to
SRC_CAP messages not being received correctly. With the changes,
verified that correct CC polarity is always detected and results
in reaching SRC_READY state.
Change-Id: Ia522abdac31642ff99bbf13ccc73a0a77bbdb32d
Signed-off-by: Scott <scollyer@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/361614
Commit-Ready: Scott Collyer <scollyer@chromium.org>
Tested-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Joe Bauman <joe.bauman@fairchildsemi.com>
Reviewed-by: Guenter Roeck <groeck@google.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
