When cr50 connects to the AP usb it should only initialize the usb when
it knows that the AP is on. If usb is incorrectly initialized it can
prevent cr50 from going to sleep. In this change the AP usb will be
initialized when suzyq is disconnected or on HOOK_CHIPSET_RESUME and it
will be released on HOOK_CHIPSET_SHUTDOWN.
BUG=chrome-os-partner:55747
BRANCH=none
TEST=manual
On reef run apreset and verify the AP can communicate with cr50
over usb after it boots up.
Run poweroff and verify cr50 has released the usb.
power the AP back on and check that it can communicate with cr50
again
Change-Id: Id35010525e2354ee140d3b7220fb5ea434a0993f
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/383979
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
On CHIPSET_SHUTDOWN set the idle_action to deep sleep. If sleep is
enabled it will go into deep sleep. If not it will wait until sleep is
sleep is enabled.
This change also sets the idle_action to IDLE_DEFAULT when resuming from
deep sleep or during init. Before cr50 kept track of the previous idle
state in a PWRDN register and then used that state during the next
resume. If we went into deep sleep, on resume we want the idle action to
be reset to sleep and then only enter deep sleep if we have detected the
AP is off.
BUG=chrome-os-partner:56100
BUG=chrome-os-partner:55747
BRANCH=none
TEST=manual
run 'poweroff' on the AP and see that cr50 enables deep sleep
verify that even if the ap is powered off it doesn't prevent ccd
from working and when suzyq is unplugged cr50 will go into deep
sleep
After running poweroff on the AP wait a while and run powerbtn
on the EC. Verify the system can boot up fully without going
into recovery.
Do this on gru and reef.
Change-Id: I07f5a9d85dd0467cd22e499d4261c75caf653563
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/373139
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
When generating the RSA endorsement primary key, use the
CR50 vendor specific template. Doing so generates the
RSA key corresponding to the certificate issued at manufacture.
Also, always start the RSA key generation counter at 1. Doing
so matches the certificate generation process at manufacture;
and there is no harm in always starting at 1, since the key
generation process remains deterministic.
BUG=none
BRANCH=none
TESTED=generated key matches endorsement cert;
checked via attestation_client
Change-Id: I6a5c329e99292e32f880c0c5ea364d511cb6ea82
Signed-off-by: nagendra modadugu <ngm@google.com>
Reviewed-on: https://chromium-review.googlesource.com/386279
Commit-Ready: Nagendra Modadugu <ngm@google.com>
Tested-by: Nagendra Modadugu <ngm@google.com>
Tested-by: Andrey Pronin <apronin@chromium.org>
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
We found the api utility in ROM doesn't enable burst mode of GDMA. It
influences the performance of FW download a lot. The CL modified GDMA
for moving the code of the other region from flash to ram. And move a
function that kicks off GMDA transactions to suspend ram in case this
utility is erased by itself. This issue will be fixed in our next
generation.
Modified sources:
1. system.c: Implement GDMA bypass.
2. system_chip.h: Import flash addresses for GDMA bypass code.
3. registers.h: Add GDMA register definitions.
4. cortex-m/ec.lds.S: Add lowpower_ram2 section in linker script.
BRANCH=none
BUG=chrome-os-partner:56794
TEST=make BOARD=npcx_evb; test sysjump and measure download time
Change-Id: I8490f8f2e5a8cdcb6fd10511878c4a4af8073bbf
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/381779
Commit-Ready: Shawn N <shawnn@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The argument is mHz not ms.
BUG=chrome-os-partner:57117,b:27849483
BRANCH=reef
TEST=Using frequency sysfs parameter check the returned value is close
to the requested value. It will be greater than the requested frequency.
It maxes out at 76Hz when frequency is greater than 13.5Hz.
Check Androsensor reports pressure.
Change-Id: Ie40ac0f0a83d1578b5b66097d85a9124ec8e4c54
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/385083
Reviewed-by: Divya S Sasidharan <divya.s.sasidharan@intel.com>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
- Enable MKBP events:
Allow EC to send sensor event to the kernel sensor stack.
- Disable APCI message display, to avoid overwhelming the console.
- Set the rotation matrices to match Android requirement.
BUG=b:27849483
CQ-DEPEND=CL:384341
BRANCH=reef
TEST=Check we can receive sensor events for ARC++.
Check the acceleromter axis are correct.
Change-Id: I5fa58e22167f027bd1b84e72f002060d15d882c4
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/385082
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
The g i2c slave controller does not support clock stretching, so it is
necessary to flow control the AP by some other means. Luckily there is
an interrupt line which g can toggle and the AP can watch.
This patch adds generating a pulse on the AP interrupt line once g
finished processing the i2c transaction. In case of the read
transaction the pulse is generated after the data to read is put in
the i2cs transmit buffer.
BRANCH=none
BUG=chrome-os-partner:57338
TEST=with this patch and the AP firmware synchronizing on the
interrupt pulse, the TPM initialization succeeds in coreboot and
depthcharge.
Change-Id: I16c09b59b7d772624baa9d1f5258aaff26f91ff9
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/385256
Reviewed-by: Scott Collyer <scollyer@chromium.org>
When we source VBUS, the BD99955 does not disable its power saving mode
and messes up our USB2.0 data connection (DP/DN).
Let's disable the BD99955 power-save mode whenever a USB data connection
is present on one of the ports.
For configurations without power saving enabled, let's still write the
power-save mode register to ensure it is in the proper (disabled) state
whatever happened before (bad RW ...)
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=gru
BUG=chrome-os-partner:57310
TEST=On Kevin, connect a USB-Ethernet dongle and see it enumerating
properly (while BD99955 power-save mode is enabled).
Change-Id: I379f94ecd294f045f353bd50eafd2035636837b1
Reviewed-on: https://chromium-review.googlesource.com/384851
Commit-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
The bug with USB data connection when the BD9995x power save mode is
enabled has been solved.
We can re-enable the low power mode to save energy.
BRANCH=gru
BUG=chrome-os-partner:57310
TEST=check that usb ethernet works after booting on kevin
Change-Id: I439f97c43e79e50db7af1f63207ad72ce8192a30
Reviewed-on: https://chromium-review.googlesource.com/385696
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
In case the AP is asking for a ODR frequency the sensor can not achieve
(for instance over 76Hz for BMP280), be sure we do not set oversampling
to 0.
Otherwise, no sensor data will be sent to the AP.
BUG=b:27849483
BRANCH=reef
TEST=Check Androsensor reports presure information even when frequency
is set at 100Hz.
Change-Id: Idb849782daa96531cc33d21ea6780fd7f1f299d5
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/385081
Commit-Ready: Gwendal Grignou <gwendal@google.com>
Tested-by: Gwendal Grignou <gwendal@google.com>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
We want the default build to be ready for production use, without
any unlocked security features, development-only tests, etc.
Running "make buildall" or "make BOARD=cr50" builds the
default (production) image.
To build a development image, use
CR50_DEV=1 make BOARD=cr50
This CL adds "-DCR50_DEV=$(CR50_DEV)" to the CFLAGS for use in
compiled code.
BUG=chrome-os-partner:55557
BRANCH=none
TEST=make buildall
Verify that
#ifdef CR50_DEV
[stuff]
#endif
works inside C code.
Change-Id: Id5e16e9ba0135828f4365fc1ac4a23384f30ba01
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/385059
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Noteworthy changes:
- Move Board and its child classes in common/board.py
- Separate flashing and resetting. Flashing used to imply running tests.
- Move up constants up for better visibility
- Change default suite to 'meta'
- Removed redundant code
- Lots of renames (all lower case names, shorter names, etc.)
BUG=none
BRANCH=none
TEST=Ran meta test and verify the results match the expectations
Change-Id: I158d96e2ee104767d25b2e721d5206e528600381
Reviewed-on: https://chromium-review.googlesource.com/383911
Commit-Ready: Daisuke Nojiri <dnojiri@chromium.org>
Tested-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
This moves the various GPIO/PINMUX reconfigurations needed to
occasionally drive a common-pulldown signal into a set of clean
functions. There's no new functionality, it's just abstracting
the control of SYS_RST_L and EC_RST_L into specific functions.
BUG=none
CQ-DEPEND=CL:380484
BRANCH=none
TEST=make buildall; test on relevant hardware
I tested this on Gru, Kevin, and Reef, and it works correctly in
all cases. I used flashrom over CCD to update both AP and EC
firmware on each of those systems.
If you just want a quick check, you can run this instead:
sudo flashrom -p raiden_debug_spi:target=AP --flash-name
sudo flashrom -p raiden_debug_spi:target=EC --flash-name
Change-Id: I15fa3b2089d10649bfd17f442e3b261f3b62b92e
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/382665
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Now that the AP uart is enabled whenever the AP is on, stop using it to
detect the state of servo. Using the EC uart is good enough and it
simplifies the device state stuff.
BUG=none
BRANCH=none
TEST=on reef and gru verify cr50 can detect servo and disable/enable
cr50 uart at whenever it is attached/detached.
Change-Id: I2fe6e796feaae5d90682d5015cdde6b46950dae6
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/383955
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
To improve spec compliance, we reduce input current limit on PD voltage
transition. This may cause us to brownout if the battery cannot provide
sufficient current, so use the max. negotiated current when our battery
is critical.
BUG=chrome-os-partner:56139
BRANCH=None
TEST=Boot with critical battery on kevin, verify system boots to OS
without brownout.
Change-Id: I1bdb2b7168c7b810af789e2206d0420f5d2bdcdd
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/383733
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
charge_manager may request a charge current limit less than the
capability of the supply in certain cases (eg. during PD voltage
transition, to make an effort to comply with reduced load spec).
Depending on the battery / system state, setting a reduced charge
current limit may result in brownout.
Pass the uncapped / max negotiated current to board_set_charge_limit()
so that boards may use it instead of the requested limit in such
circumstances.
BUG=chrome-os-partner:56139
BRANCH=gru
TEST=Manual on kevin with subsequent commit, boot system with zinger +
low-charge battery, verify devices powers up to OS without brownout.
Change-Id: I2b8e0d44edcf57ffe4ee0fdec1a1ed35c6becbbd
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/383732
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
AL3010 is Dyna-Image ambient light sensor.
Here is add basic driver and functions.
BUG=chrome-os-partner:52915
BRANCH=elm
TEST=Flash on base board "glados" with ASUS
al3010_init is return success.
al3010_read_lux is return the lux success.
Change-Id: Ie3b97d0889b150c43d19bc84d84f04c13e415c31
Signed-off-by: Rocky Hsiao <rocky.hsiao@dyna-image.com>
Reviewed-on: https://chromium-review.googlesource.com/356874
Reviewed-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-by: Thomas Lin <thomas.lin@dyna-image.com>
If the host sends a back to back I2CS write followed by a read of the
access register, then the read IRQ can be missed by FW because it was
clearing this bit at the end of the ISR. This would result in a
following write to have the incorrect number of bytes since the
address register byte from the read that wasn't processed gets left in
the HW write fifo.
BRANCH=none
BUG=chrome-os-partner:40397
TEST=manual
The issue was happening at the beginning of depthcharge. Without this
fix, I would see the Cr50 console message:
'data size mismatch for reg 0x0 rx 2, need 1'
After moving the IRQ clear could not reproduce this message. In
addition, the debug I2CS log showed that there was a read transaction
immediately following the write.
Change-Id: I9854dde6880a789e0acb2b1f6a06b43c73a5a2df
Signed-off-by: Scott <scollyer@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/382687
Commit-Ready: Scott Collyer <scollyer@chromium.org>
Tested-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
In the initial design multi-byte registers were being converted to
network byte order and so there was reason to treat 1 byte and 4 byte
register reads differently. However, since the conversion to network
byte order is not being done, there is no reason to treat these cases
differently outside of the number of bytes to read.
BRANCH=none
BUG=chrome-os-partner:40397
TEST=manual
Reboot Reef and verify that TPM is working in coreboot
coreboot-coreboot-unknown.9999.fbbcb2d Thu Sep 8 19:41:15 UTC 2016
LPSS I2C bus 2 at 0xfe022000 (400 KHz)
tpm_vendor_probe: ValidSts bit set(1) in TPM_ACCESS register after 5 ms
I2C TPM 2:50 (chip type cr50 device-id 0x28)
setup_tpm():404: TPM: SetupTPM() succeeded
src/lib/tpm2_tlcl.c:179 index 0x1007 return code 0
Change-Id: If74c432136c02d334e0d58d16dc817d7773b0584
Signed-off-by: Scott <scollyer@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/382688
Commit-Ready: Scott Collyer <scollyer@chromium.org>
Tested-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
By this time hopefully all old hardware has been junked. Take out the
old code to check for old hardware to save a little bit of space, since
space is tight.
BRANCH=gru
BUG=chrome-os-partner:55561
TEST=Build and boot
Change-Id: I9b147a8c1955e1c2c3fee3dd6ab7fc6e520be4bf
Reviewed-on: https://chromium-review.googlesource.com/384452
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Simon Glass <sjg@google.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
This reverts commit 1966433427.
The CL seems to break USB ethernet dongles (and maybe other USB
functionality). Reverting for now so development isn't impacted.
BUG=chrome-os-partner:57310
BRANCH=gru
TEST=check that usb ethernet works after booting on kevin
Change-Id: I91d05da65d56afcd8a21ac2074a31f759c4aaec8
Reviewed-on: https://chromium-review.googlesource.com/383862
Commit-Ready: Douglas Anderson <dianders@chromium.org>
Tested-by: Douglas Anderson <dianders@chromium.org>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
LID_OPEN gpio is interrupt trigger on both the edge. If the system is
hibernated when LID is open and then LID is closed, system wakes from
hibernation. Hence setting the LID_OPEN GPIO as interrupt raising before
hibernation so that system won't wake up upon LID close in hibernation.
BUG=chrome-os-partner:57221
BRANCH=none
TEST=Issued hibernate when LID is open, closed the LID after hibernation
observed system won't boot back till LID is open again.
Change-Id: Idc89c3d85b7d246c3e18d0ced48e7d47bebeafec
Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/383753
Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
There is leakage on SYS_RST_ODL from the internal pullup cr50 has on
DIOM0. This change removes the internal pullup on reef.
On Kevin there is a bug preventing the EC from being able to pull
sys_rst_l up high enoug for cr50 to detect that it is pulled high. This
change adds an internal pullup back when cr50 detects that it is on a
kevin or gru.
BUG=chrome-os-partner:56945
BUG=chrome-os-partner:53544
BRANCH=none
TEST=On gru and kevin remove servo verify when apreset is run on the EC
it resets cr50 and the AP. Run pinmux and check that there is a pullup
on diom0 on kevin but not on gru.
Change-Id: Ica4f557745967b93e0bd9c8462916b1f735756ac
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/381322
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
This changes how tpm_register_put() debug messages are displayed
to show only the bytes that are sent instead of some
uninitialized bytes as well.
BUG=none
BRANCH=none
TEST=make buildall; run on Cr50 hardware
On the console, run
chan -1
to enable displaying the debug output.
Before this CL, you'd see messages like this:
tpm_register_put(0x024, 21 180)
tpm_register_put(0x024, 1 17f)
tpm_register_put(0x018, 1 120)
tpm_register_put(0x018, 1 140)
Afterwards, you'd see accurate messages:
tpm_register_put(0x024, 21, 80 01 00 00 ...)
tpm_register_put(0x024, 1, 01)
tpm_register_put(0x018, 1, 20)
tpm_register_put(0x018, 1, 40)
Change-Id: Iad798804a4b6060e9bfafad50c90138eb1144c8f
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/382664
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
All PIN() assignments in board/$BOARD/gpio.inc must be unique,
since otherwise you're just creating duplicate names and table
entries for the same core interrupt and may not be initializing
things the way you think.
BUG=none
BRANCH=none
TEST=make buildall; test on Cr50 hardware
Also verified that the image size is exactly the same before an
after this CL.
Change-Id: Ifb1805a010905f67fc5c0d246b6252af73715409
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/383773
Reviewed-by: Randall Spangler <rspangler@chromium.org>
On different systems SYS_RST may be edge triggered, so it is not
guaranteed holding it low will hold the AP in reset. With this change,
enable_ap_spi now holds the EC in reset, so it is guaranteed the AP is
in reset.
BUG=chrome-os-partner:54982
BRANCH=none
TEST=run 'sudo flashrom -p raiden_debug_spi:target=[EC|AP] --flash-name'
on gru, kevin and reef
Change-Id: I3176462b932eba5bf8d69dbab70500bca8c7ff46
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/380484
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
For kevin, we are not using the PROCHOT# signal for the charger so we
can enable a power save mode. This commit will leave BGATE on but
without monitoring the PROCHOT# signal. When VBUS or VCC is removed
from the charger, the charger will enter this power save mode. It will
return to normal functionality when VBUS or VCC is applied.
BUG=chrome-os-partner:55631
BRANCH=kevin
TEST=Flash kevin; Verify we can still charge; Verify that power
consumption is less with this patch applied than without.
CQ-DEPEND=CL:382877
Change-Id: I05274a770b35c981e0541d8f79f66b81ffb4d153
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/383391
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
The BD99956 charger has a power save mode that it can enter once VBUS or
VCC is removed. This commit adds an optional config option that can be
used to select the power save mode:
CONFIG_BD99955_POWER_SAVE_MODE
By default, no power save mode will be enabled. However, a board can
device what level of power savings they wish to use.
The levels are the following:
BD99955_PWR_SAVE_LOW /* BGATE ON w/ PROCHOT# monitored only system
* voltage. */
BD99955_PWR_SAVE_MED /* BGATE ON w/ PROCHOT# monitored only system
* voltage every 1ms. */
BD99955_PWR_SAVE_HIGH /* BGATE ON w/o PROCHOT# monitoring. */
BD99955_PWR_SAVE_MAX /* BGATE OFF */
BUG=chrome-os-partner:55631
BRANCH=kevin
TEST=make -j buildall
Change-Id: Ibab7ad30d5f1ae9917b46b40d6f2800ef19e52dd
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/382877
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
Enable interrupt from BMI160 for FIFO control.
It can be use for significant motion detection.
BRANCH=kevin
BUG=b:28552512
TEST=Pass CTS tests SensorBatchingTests, SingleSensorTests
To trigger FIFO interrupt during the batch tests, EC lid angle
calculation is disabled from the EC with "acclerate 0 0"
Change-Id: I3ed4afcdee7075c5e5e20974d70a9e6bd64ecd52
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/382677
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Allow the detection of tablet mode for sensors and powerd.
BUG=chromium:606718,b:28552512
BRANCH=kevin
TEST=Check with evtest that events are send.
Check sensor data is in lid referal in tablet mode.
Change-Id: I0822e7419ccba01d70bf9327593164c15493fb10
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/380377
Reviewed-by: Randall Spangler <rspangler@chromium.org>
When tablet mode is detected, send an event to the AP.
BUG=chromium:606718
BRANCH=none
TEST=Check with evtest that events are sent when the tablet goes in tablet
mode and back to device mode.
Change-Id: I49f2404b5ecf87e71fa5aef4c8ce9c9beda26a15
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/380414
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
User of sensor data can use tablet mode to rotate the sensor datums
along the X axis.
This is useful on Kevin where we gather base data.
When the base is behind the lid, the datums needs to be rotated by 180
to be in the lid referential.
BUG=b:27849483
BRANCH=none
TEST=check the sensors changes when kevin is in tablet mode.
Change-Id: I60147600f534df0770a44b5158ef8afe87d9dd9d
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/380413
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Using the lid angle, detect if we are in tablet mode or not.
We are in tablet mode when the lid angle is large enough:
tablet_mode:
1 | +-----<----+----------
| \/ /\
| | |
0 |------------------------>----+
+------------------+----------+----------+ lid angle
0 240 300 360
BRANCH=kevin
BUG=chrome-os-partner:55702,b:27849483
TEST=Check on Kevin event are sent on tablet mode transition.
Change-Id: Id9935ce4dd717e2c20fa6c9520defb504a1760d9
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/383073
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
