Change prefix from CONFIG_ESPI to CONFIG_HOSTCMD_ESPI for consistency.
BRANCH=none
BUG=chromium:818804
TEST=Full stack builds and works on yorp (espi) and grunt (lpc)
Change-Id: I8b6e7eea515d14a0ba9030647cec738d95aea587
Signed-off-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1067513
Reviewed-by: Randall Spangler <rspangler@chromium.org>
We have converted all LPC-only configs to HOSTCMD_LPC so the remaining
CONFIG_LPC defines represent the common case.
BRANCH=none
BUG=chromium:818804
TEST=Full stack builds and works on yorp (espi) and grunt (lpc)
Change-Id: Iba9a48f2cab12fadd0d9ab8eab0d5d5476eab238
Signed-off-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1067503
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Remove the previous hack of force increasing the adapter current.
The PP5000 rail is now turned on/off during power-on/off AP.
Add a check to ensure it has enough power to enable the 5V rail
and boot AP. If the battery is in low level or unplugged and the
charger adapter doesn't supply enough power, don't boot AP and
transition back to S5. The check may wait a while for PD
negoiation.
BRANCH=none
BUG=b:79353631
TEST=On battery plugged and unplugged cases, checked the device can
source VBUS to USB port-0 and port-1.
TEST=Unplug battery and use a low-power adapter, can't boot up AP.
See the "Not enough power to boot" message and transition to S5.
Change-Id: Ie9b8dff6e10d97dffd554b382595e5e7a70875e6
Signed-off-by: Wai-Hong Tam <waihong@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1050607
Keep the timestamp of the latest power lost. Add a handler to wake
the chipset task to check if power lost stays low for a while (the
time between now and the latest power lost is longer than a period).
BRANCH=none
BUG=b:78455067
TEST=Toggle EC GPIO SYS_RST_L for a low pulse to execute PMIC reset
sequence and verified AP reset but not a transition S0 -> S5.
TEST=Toggle EC GPIO PMIC_KPD_PWR_ODL and SYS_RST_L for a low pulse
(see power_off function) to execute PMIC shutdown sequence and verified
a power-lost transition S0 -> S5.
Change-Id: I8ed789d701e834195865bfdf2d302388d42618d2
Signed-off-by: Tom Wai-Hong Tam <waihong@google.com>
Signed-off-by: Alexandru M Stan <amstan@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1028831
Commit-Ready: Wai-Hong Tam <waihong@google.com>
Tested-by: Wai-Hong Tam <waihong@google.com>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
This makes the EC listen to the AP_RST_REQ GPIO from AP. The rising
edge interrupts to trigger a hook to call chipset_reset().
As the hook task will be preempted by the chipset task, it adds a
flag bypass_power_lost_trigger to avoid triggering to S5 as the
chipset state machines sees power lost during the reset.
So far the chipset_reset() implementation is to do a cold reset;
will be revised to a warm reset after the PMIC registers are
reprogrammed.
BRANCH=none
BUG=b:74395451
TEST=make buildall -j
TEST=Ran 'reboot' on AP console which toggles the GPIO.
Change-Id: I946cb029541ce018a8ed1ce25681d38998a7f4b6
Signed-off-by: Wai-Hong Tam <waihong@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1023986
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Configure switchcap every time we're about to change the signal,
just in case it forgot.
Feel free to revert this after b/77957956 is fixed.
BRANCH=none
BUG=b:77957956
TEST="i2cxfer r 0 0xd0 0x2" never shows 0x70, even after a bad brownout
(like "gpioset EN_PP5000_A 1" on an unreworked board)
Change-Id: I8994cd402ce96d8bf4e436dadfc0e572e7f77a85
Signed-off-by: Alexandru M Stan <amstan@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1024501
Commit-Ready: Wai-Hong Tam <waihong@google.com>
Tested-by: Wai-Hong Tam <waihong@google.com>
Reviewed-by: Wai-Hong Tam <waihong@google.com>
This is the power sequence for rev-0 board. Confirmed the behavior of
reprogramming the PMIC registers to enable the instant reset and
shutdown.
BRANCH=none
BUG=b:74395451
TEST=make buildall -j
TEST=Tried the following cases:
* Cold reset:
$ dut-control cold_reset:on sleep:0.2 cold_reset:off
Result: G3 -> S0
* Long power press to shutdown:
$ dut-control pwr_button:press sleep:8.2 pwr_button:release
Result: S0 -> S5 -> G3
* Long power press to power-on but then shutdown:
$ dut-control pwr_button:press sleep:8.2 pwr_button:release
Result: G3 -> S0 -> S5 -> G3
* Short power press to power-on:
$ dut-control pwr_button:press sleep:0.2 pwr_button:release
Result: G3 -> S0
* Console command: apreset
Result: S0 -> S5 -> S0
* Console command: power off
Result: S0 -> S5 -> G3
* Console command: power on
Result: G3 -> S0
* Console command: apshutdown
Result: S0 -> S5 -> G3
* Lid open to power-on:
$ dut-control lid_open:no sleep:0.2 lid_open:yes
Result: G3 -> S0
Change-Id: Ia9d44b1dccac66b5b580c08c6c1697ef5989b923
Signed-off-by: Wai-Hong Tam <waihong@google.com>
Signed-off-by: Alexandru M Stan <amstan@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/969702
The value of pwr_5v_en_req needs to be preserved when the EC performs a
sysjump, otherwise any task calling power_5v_enable(tid, 0) will drop
the 5v rail for the entire system.
I've scheduled this at HOOK_PRIO_FIRST for restoring the value to ensure
that no other init hooks read a stale value, but I'm not sure if that's
necessary.
BUG=b:78275296
BRANCH=none
TEST=Booted yorp with power only connected to USB-C port 0
Change-Id: I3a9ed24a5fde02b60163ad2c5e3252759f8c1c5b
Signed-off-by: Justin TerAvest <teravest@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1020066
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Jett Rink <jettrink@chromium.org>
In order to ensure that all chipset init/shutdown operations happen
within the context of chipset task for APL/GLK:
1. Update chipset_force_shutdown to only set a flag force_shutdown to
indicate that chipset shutdown is requested and wake the chipset task.
2. Make chipset task (within the power state machine) call
internal_chipset_shutdown.
3. Make internal_chipset_shutdown reset force_shutdown flag and make a
callback to weak function chipset_do_shutdown to trigger chipset
shutdown.
BUG=b:78259506
BRANCH=None
TEST=Verified that "apshutdown" on EC console results in chipset
shutdown action being taken within chipset task.
Change-Id: If13b65ae47e3dce2e466320cc14c68239563f6ed
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1018737
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Jett Rink <jettrink@chromium.org>
Now that all boards are moved to using chipset_pre_init_callback,
get rid of hook notification for CHIPSET_PRE_INIT from x86 power state
machine.
BUG=b:78259506
BRANCH=None
TEST=Verified that yorp still boots.
Change-Id: I244848b3c80e8ccd34b3c99c8aa2dee3030e0e53
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1018736
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Jett Rink <jettrink@chromium.org>
This change adds a callback for chipset_pre_init_callback which is
made by x86 common power state machine when in G3S5 state. Until now,
there was a hook CHIPSET_PRE_INIT_CALLBACK that was notified by
chipset task when in G3S5 state. However, there are at least following
reasons why this should be a callback and not a hook notification:
1. The initialization that is done as part of pre-init could be
essential for the power state machine to make progress. Though the
chipset task goes to sleep waiting for power signals after the hook
notification, pre-initialization can all be done as part of a callback
since it is mostly board-specific code that is doing work to
initialize PMIC.
2. Typically, boards use I2C transactions to setup PMIC on getting
chipset pre-init notification. However, since i2c transfers are not
encouraged in hook task, they have to be deferred anyways.
3. Since the initialization is being done as part of hook task, use of
any constructs e.g. pwr_5v_en_req which allows multiple consumers to
enable/disable power rails will use task id for hook task. Instead it
is better to provide correct information about the task by letting
chipset task perform this request.
Thus, this change adds a callback chipset_pre_init_callback in G3S5
state for x86 power state machine. This callback is guarded by
CONFIG_CHIPSET_HAS_PRE_INIT_CALLBACK.
The hook notification is left as is for now until all x86 boards are
moved over to using the newly added callback.
BUG=b:78259506
BRANCH=None
TEST=None
Change-Id: I2e1d73e5308759fef41680ae715ef71268b61780
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1018733
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Jett Rink <jettrink@chromium.org>
Majority of the chipsets do not have a dedicated GPIO to trigger
AP cold reset. Current code either ignores cold reset or does a warm
reset instead or have a work around to put AP in S5 and then bring
back to S0. In order to avoid the confusion, removed the cold reset
logic and only apreset is used hence forth.
BUG=b:72426192
BRANCH=none
TEST=make buildall -j
Manually tested on GLKRVP, apreset EC command can reset AP.
Change-Id: Ie32d34f2f327ff1b61b32a4d874250dce024cf35
Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/991052
Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Jett Rink <jettrink@chromium.org>
In APL & GLK, cold reset code does a AP force shutdown (with board
specific AP shutdown code) by power sequencing the SOC all the way
to S5 and bring it back to S0. However there is no separate GPIO
in APL & GLK for doing AP cold reset hence removed the AP cold
reset logic.
BUG=b:72426192
BRANCH=none
TEST=make buildall -j
Manually verified on GLKRVP, apreset cold & warm behave same
Change-Id: I6ee5e4c4df94e685acdabe31b8b5554295883792
Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/974107
Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Geminilake uses the same power sequencing code as Apollolake. Instead
of the board specifying the wrong chipset, we will make the correct
chipset reuse the existing power code.
This also gives us flexibility in the future if GLK needs to vary from
ALK in any of shared code.
BRANCH=none
BUG=b:74020444
TEST=build all
Change-Id: Icd00286ac4f0612d1bda56677c4141957480c6bf
Signed-off-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/969613
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
EN_PWR_A GPIO turns on PP1800_A, PP5000_A, PP3300_A, PP950_A.
These should be off in G3 and on in S5 and higher.
VGATE (S0 power) is pulled high in G3 when SPOK (system power,
S5) is low because PP5000_A turns off, so add a check for this
and only pass through high VGATE when SPOK is also high.
Leave kahlee behavior unchanged (power stays on in G3).
BUG=b:72744306
BRANCH=none
TEST=power on and off SOC, see GPIO_EN_PWR_A go low in G3
Change-Id: I68a1ac10263ad84d5ee154613e5e248edb4d287c
Signed-off-by: Edward Hill <ecgh@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/904729
Commit-Ready: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Jett Rink <jettrink@chromium.org>
When AP requests cold reboot, currently EC does not perform PMIC
reset because chipset_handle_reboot is executed only after EC jumps
to RW. This causes EC to miss CHIPSET_STARTUP and CHIPSET_RESUME
events because power rails do not cycle.
This patch will make EC execute PMIC reset to before vboot_main.
BUG=b:73093795
BRANCH=none
TEST=reboot, reboot ap-off, verify USB ports are powered after
transitionining to dev mode.
Change-Id: Ic04395d8a4bff45d9fc60601b07c600dfb75d9c0
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/908094
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
To support CR50 deep sleep mode:
In up-sequence, SYS_RST_L needs to remain asserted on the transition
to S5 and then deasserted on the transition to S0;
In down-sequence, SYS_RST_L needs to be asserted on the transition to S5.
This only affects Scarlet.
BUG=b:35647982
BRANCH=none
TEST=minitor SYS_RST_L pin to confirm it is toggled right
Change-Id: Ic73d39c531f9d28b2087a23d58613e98ec80dbd2
Signed-off-by: Philip Chen <philipchen@google.com>
Reviewed-on: https://chromium-review.googlesource.com/866115
Commit-Ready: Philip Chen <philipchen@chromium.org>
Tested-by: Philip Chen <philipchen@chromium.org>
Reviewed-by: David Schneider <dnschneid@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
We should turn off PP3300_S0 and then PP1800_S0 to meet
KD panel spec. PP3300_S0 has to be on in S3_WoUSB, so PP1800_S0
also has to be on - let's move PP1800_S0_EN to s0s3_usb_wake_power_seq.
BUG=b:71057948
BRANCH=none
TEST='suspend_stress_test' for 10+ cycles without seeing things go wrong
Change-Id: Ic44411062b4c9e857b9f8ca6565550ba8bd2f950
Signed-off-by: Philip Chen <philipchen@google.com>
Reviewed-on: https://chromium-review.googlesource.com/862254
Commit-Ready: Philip Chen <philipchen@chromium.org>
Tested-by: Philip Chen <philipchen@chromium.org>
Reviewed-by: Philip Chen <philipchen@chromium.org>
Add espi_signal_is_vw in new file common/espi.c for
testing if a signal is an eSPI virtual wire. API used
in power common and intel_x86.
Fix CONFIG_BRINGUP support for eSPI (off by default).
Add espi_vw_get_wire_name returning a pointer to
constant string. Chip modules do not need to maintain
names of eSPI signals.
BRANCH=none
BUG=
TEST=Build poppy and other eSPI enabled boards. Test
power state machine.
Change-Id: I13319e79d208c69092a02ec3ac655477d3043d61
Signed-off-by: Scott Worley <scott.worley@microchip.corp-partner.google.com>
Reviewed-on: https://chromium-review.googlesource.com/836818
Commit-Ready: Randall Spangler <rspangler@chromium.org>
Tested-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
When SLP_SUS_L is deasserted, that means the chipset is in S5.
BUG=None
BRANCH=None
TEST=Flash meowth; boot from AC only, verify that when SoC actually
boots the power state is reported as S0 instead of G3.
Change-Id: Ib9cd76aa9efd6f81df432205b8c1e8c342e32af6
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/837485
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The cannonlake power state chipset code would fail to keep an accurate
record of the chipset's power state. For example, the EC could claim
that the AP was in G3, whereas the SLP_SUS_L signal was deasserted.
This commit fixes a few issues with the chipset code.
- First, don't have PP3300_DSW_EN enabled by default coming out of
reset.
The default chipset power state when the EC comes out of reset is G3,
therefore we should not enable the PP33000 DSW rail until we decide to
leave G3. This is usually triggered by a power button press.
- Similarly, when we wish to enter G3, we should turn off the PP3300 DSW
rail instead of the noop that was done before.
- Lastly, turn on the 5V rail when entering S5 instead of S3 and turn it
off when leaving S5 to G3.
BUG=b:70184397,b:70244199
BRANCH=None
TEST=Flash zoombini; Verify that AP boots to S0 and can shutdown to S5
and the EC tracks it. Verify that after the S5 inactivity timer, we
fall to G3. Verify that SLP_SUS_L is asserted and DSWPWROK is low.
Verify that we can still perform BC1.2 detection in G3. `reboot ap-off`
and verify that the AP does indeed remain off and no port 80 codes are
seen.
TEST=Verify that 5V is off in G3, but can be turned on if needed.
TEST=Verify that 5V is on in S5.
TEST=With the exception of BC1.2, repeat the above tests for meowth.
Change-Id: I444a8f29969ef6a68a83d1734912d239bad429a5
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/813501
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
Waiting out HOOK_TICK_INTERVAL for a non-interrupt power signal can
cause boot delays of up to 500ms, which can lead to dropped host
commands and other bad side effects. Poll IN_PGOOD_S0 when sequencing up
to reduce the minimum delay to 5ms.
BUG=b:70390178
BRANCH=None
TEST=Run "reboot" on EC console, check timestamp of S0 transition print:
[0.332974 power state 3 = S0, in 0x000f]
Compare to pre-patch:
[0.692799 power state 3 = S0, in 0x000f]
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: I4b8891f75d896b1ae47d8f12ed07581f20b6ae7c
Reviewed-on: https://chromium-review.googlesource.com/822594
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Philip Chen <philipchen@chromium.org>
Add delay of 1ms with stable power before asserting PWR_GOOD.
CDX03 seems to work ok with and without the delay, but since it
is a requirement in the electrical data sheet, better add it.
Also removed an unnecessary header while I was here.
BUG=b:70350333
BRANCH=none
TEST=power CDX03 on and off
Change-Id: I9f2f94bfb907ac9e88f350e72286061a97ebfe3d
Signed-off-by: Edward Hill <ecgh@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/816063
Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Unified Host Event Programming Interface (UHEPI) enables a unified host
command EC_CMD_PROGRAM_HOST_EVENT to set/get/clear different host events.
Old host event commands (0x87, 0x88, 0x89, 0x8A, 0x8B, 0x8C, 0x8D, 0x8E,
0x8F) is supported for backward compatibility. But newer version of
BIOS/OS is expected to use UHEPI command (EC_CMD_PROGRAM_HOST_EVENT)
The UHEPI also enables the active and lazy wake masks. Active wake mask
is the mask that is programmed in the LPC driver (i.e. the mask that is
actively used by LPC driver for waking the host during suspended state).
It is same as the current wake mask that is set by the smihandler on host
just before entering sleep state S3/S5. On the other hand, lazy wake masks
are per-sleep masks (S0ix, S3, S5) so that they can be used by EC to set
the active wake mask depending upon the type of sleep that the host has
entered. This allows the host BIOS to perform one-time programming of
the wake masks for each supported sleep type and then EC can take care
of appropriately setting the active mask when host enters a particular
sleep state.
BRANCH=none
BUG=b:63969337
TEST=make buildall -j. And verfieid following scenario
1). Verified wake masks with ec hostevent command on S0,S3,S5 and S0ix
2). suspend_stress_test with S3 and S0ix
3). Verified "mosys eventlog list" in S3 and s0ix resume to confirm
wake sources (Lid, power buttton and Mode change)
4). Verified "mosys eventlog list" in S5 resume to confirm wake sources
(Power Button)
5). Verified above scenarios with combination of Old BIOS + New EC and
New BIOS + Old EC(making get_feature_flags1() return 0)
Change-Id: Idb82ee87fffb475cd3fa9771bf7a5efda67af616
Signed-off-by: Jenny TC <jenny.tc@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/576047
Commit-Ready: Jenny Tc <jenny.tc@intel.com>
Commit-Ready: Jenny Tc <jenny.tc@intel.corp-partner.google.com>
Tested-by: Jenny Tc <jenny.tc@intel.com>
Tested-by: Jenny Tc <jenny.tc@intel.corp-partner.google.com>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
If power-up is inhibited by charger because of battery SOC, then check
for the conditions again on BATTERY_SOC_CHANGE. This allows the EC to
boot the AP up on connecting AC power and SOC going above the minimum
required.
BUG=b:65864825
BRANCH=None
TEST=Verified following on coral and soraka:
1. Discharge battery to ~0%
2. Connect AC power ==> Power-up is inhibited
3. When battery SOC reaches 1%. AP is not taken out of reset:
"[12.974428 Battery 1% / 8h:4 to full]
[12.980439 power-up still inhibited]"
4. When battery SOC reaches 2%, AP is taken out of reset:
"[9.230148 Battery 2% / 4h:5 to full]
[9.236122 Battery SOC ok to boot AP!]"
Change-Id: Ifa89f8929987d86c9e02530b663d563dbe25ed85
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/753294
Reviewed-by: Shawn N <shawnn@chromium.org>
Similar to CL:774298, intention of chipset_force_shutdown is to power
off the AP by simulating power button press until it results in power
button override and shuts down AP. However, if AP is already in hard
or soft off conditions (i.e. G3, S5G3, G3S5 or S5) then AP is already
off, and simulating power button press results in
charge_prevent_power_on from incorrectly assuming that the power
button is pressed by user. Thus, check if the system is in soft or
hard off before shutting it down.
BUG=b:65864825
BRANCH=None
TEST=make -j buildall
Change-Id: I4b6d798af4618cbd4179f8700ebb2aa78021207e
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/791933
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Intention of chipset_force_shutdown is to power off the AP by
simulating power button press until it results in power button
override and shuts down AP. However, if AP is already in hard or soft
off conditions (i.e. G3, S5G3, G3S5 or S5) then AP is already off, and
simulating power button press results in charge_prevent_power_on from
incorrectly assuming that the power button is pressed by user. Thus,
check if the system is in soft or hard off before shutting it down.
BUG=b:65864825
BRANCH=None
TEST=Verified that apshutdown still works fine from EC console on
soraka.
Change-Id: Id892e5b2c8c1e4ce0bad95a70ea6a3ed547a7047
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/774298
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
With the upcoming change to add a new command to get/set/clear host
events and masks, it seems to be the right time to bump up the host
events and masks to 64-bit. We are already out of available host
events. This change opens up at least 32 bits for new host events.
Old EC commands to operate on host events/masks will still deal with
lower 32-bits of the events/mask. On the other hand, the new command
being added will take care of the entire 64-bit events/masks. This
ensures that old BIOS and kernel versions can still work with the
newer EC versions.
BUG=b:69329196
BRANCH=None
TEST=make -j buildall. Verified:
1. hostevent set 0x4000 ==> Sets correct bit in host events
2. hostevent clear 0x4000 ==> Clears correct bit in host events
3. Kernel is able to query and read correct host event bits from
EC. Verified using evtest.
4. Coreboot is able to read correct wake reason from EC. Verified
using mosys eventlog list.
Change-Id: Idcb24ea364ac6c491efc2f8dd9e29a9df6149e07
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/770925
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Created Meowth symbolic link to Zoombini.
Modified Zoombini gpio.inc and board, etc. files to
compile a Meowth EC image with the correct gpios.
BUG=b:69133424
BRANCH=none
TEST=make BOARD=meowth and BOARD=zoombini
runs with no errors
Change-Id: Ib34d956efa89ae125de1ce7f8799162c74df0122
Signed-off-by: Rachel Nancollas <rachelsn@google.com>
Reviewed-on: https://chromium-review.googlesource.com/762039
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
This reverts commit 352276235c.
This is required to ensure that PMIC VR decay is enabled before
SLP_S0# is asserted. Else, the setting does not take effect and hence
results in higher power consumption.
BUG=b:69337192
BRANCH=None
TEST=make -j buildall
Change-Id: I6885e7447277d853a2414be299dfea25f5547df4
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/771054
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Change chipset_force_shutdown() to not call power_button_pch_press()
when called from POWER_S5G3 state, so that we don't set pwrbtn=LOW
when entering G3.
BUG=b:68760602
BRANCH=none
TEST=push kahlee power button
Change-Id: I931fc73f2386f8124f1e082cccb095e3863cbb99
Signed-off-by: Edward Hill <ecgh@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/752682
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
power_board_handle_host_sleep_event was added to allow boards like
poppy to enable/disable PMIC VR decay only once during S0ix
entry/exit. Now that the chipset hooks have been fixed, there is no
need of this board specific callback. If in the future, there is a
need to have such a callback, this change can be reverted.
BUG=None
BRANCH=None
TEST=make -j buildall
Change-Id: I1d60e43da6c0d462132593efa26bc52312b81786
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/745982
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Instead of using HOST_SLEEP_EVENT_S0IX_RESUME as a reset state to
reinitialize S0ix flag, add a new default state
HOST_SLEEP_EVENT_DEFAULT_RESET. This also allows different parts of
the code to take correct action depending upon the state that is
currently triggered.
BUG=None
BRANCH=None
TEST=Verified that SLP_S0# interrupt doesn't get asserted during
runtime S0ix.
Change-Id: Id6fc8f3b015561d2899a9d39796b77a11a57e758
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/745901
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Add a new LPC helper routine lpc_resume_clear_masks that can be used
to clear SCI, SMI and wake masks upon resume from S3. This is done to
mask the events until host explicitly unmasks them.
It also ensures that these masks do not get reset on resume from S0ix
where the host does not re-configure these masks.
BUG=b:68669668
BRANCH=None
TEST=Verified following:
1. make -j buildall
2. On resume from S0ix, SCI mask is not reset.
3. On resume from S3, SCI mask is reset and then set again by host request.
Change-Id: I17a86bd60ef066b3716fb79ecce62f311eb45509
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/745533
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The 5V power good signal is being removed from the PMIC power good tree,
however, if the 5V power good is not asserted, we should not try booting
to S0. This is because the 1050_STG rail load switch is powered off of
the 5V rail.
Since wireless power control is being moved to the AP, these pins are now
repurposed to control the PMIC enable and for the 5V power good signal.
This commit adds the 5V power good pin to the EC and makes it a required
power signal for S0.
BUG=b:66000679
BRANCH=None
TEST=make -j buildall
TEST=flash zoombini; Verify EC boots up okay.
Change-Id: I8924320030a00b8808aea27fb668451e6e41d590
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/736312
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
There is a fundamental difference in host behavior w.r.t. S3 and
S0ix. When the host enters S3, it asserts the SLP_S3# signal until it
is woken back up. Thus, EC depends on the SLP_S3# signal state to
decide when to notify listeners about CHIPSET_SUSPEND and
CHIPSET_RESUME state.
With S0ix, SLP_S0# signal is asserted whenever host enters
S0ix. However, periodically (every 8 seconds), the host wakes up for
some bookkeeping activities, but does not come out of the low power
mode completely. This bookkeeping activity takes ~2-5 ms and the host
goes back into S0ix state. Because of this periodic activity, SLP_S0#
signal is de-asserted and asserted back every 8 seconds.
Thus, if the power state machine depends solely on the SLP_S0# signal
to notify CHIPSET_SUSPEND and CHIPSET_RESUME states, then all the
listeners would be performing unnecessary actions every 8
seconds. This leads to a number of side-effects including:
1. Dual-role toggle being enabled and disabled every 8 seconds.
2. Power spikes in EC power consumption during S0ix every 8 seconds.
In order to avoid the side-effects of periodic host activity in S0ix,
this change adds a new flag s0ix_notify, which is set based on the
notifications that are pending based on host sleep event.
On receiving host sleep event for S0ix suspend, s0ix_notify will be
set to S0IX_NOTIFY_SUSPEND. Next, whenever SLP_S0# is asserted,
power_state machine notifies listeners of CHIPSET_SUSPEND
and resets s0ix_notify flag to S0IX_NOTIFY_NONE. Thus, all future
assertions of SLP_S0# do not result in the suspend notification.
Similarly, on resume, power_state machine will not notify
CHIPSET_RESUME on SLP_S0# deassertion. Instead the host sleep event
for S0ix resume will set s0ix_notify flag to S0IX_NOTIFY_RESUME and
wake chipset task. The power state machine in turn will notify
listeners of the resume event and reset s0ix_notify flag.
BUG=b:65356050,b:67750352
BRANCH=None
TEST=Verified that the CHIPSET_SUSPEND/CHIPSET_RESUME notification
happens only once during a system suspend/resume cycle. Periodic host
wakes for book-keeping activities do not result in
CHIPSET_SUSPEND/CHIPSET_RESUME notifications.
Change-Id: Idf253b9393a0c25ff2eac63c60ddbcd3af954818
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/729478
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
