qca-wifi-7: Add Zyxel NWA50BE model

Signed-off-by: YenLin Pan <YenLin.Pan@zyxel.com.tw>

.github/workflows/build-dev.yml

@@ -21,7 +21,7 @@ jobs:
     strategy:
       fail-fast: false
       matrix:
-        target: [ 'cig_wf189h', 'cig_wf189w', 'cig_wf660a', 'cig_wf672', 'cig_wf186h', 'cig_wf186w', 'cig_wf188n', 'cig_wf189', 'cig_wf196', 'cig_wf196', 'cybertan_eww631-a1', 'cybertan_eww631-b1', 'sonicfi_rap630w-312g', 'sonicfi_rap63xc-211g', 'sonicfi_rap630c-311g', 'sonicfi_rap630w-311g', 'sonicfi_rap630w-211g', 'sonicfi_rap650c', 'sonicfi_rap7110c-341x', 'sonicfi_rap750e-h', 'sonicfi_rap750e-s', 'sonicfi_rap750w-311a', 'edgecore_eap101', 'edgecore_eap102', 'edgecore_eap104', 'edgecore_eap105', 'edgecore_eap111', 'edgecore_eap112', 'edgecore_oap101', 'edgecore_oap101-6e', 'edgecore_oap101e', 'edgecore_oap101e-6e', 'edgecore_oap103', 'hfcl_ion4xe', 'hfcl_ion4xi', 'hfcl_ion4x', 'hfcl_ion4x_2', 'hfcl_ion4x_3', 'hfcl_ion4xi_w', 'hfcl_ion4x_w', 'indio_um-305ax', 'senao_iap4300m', 'senao_iap2300m', 'senao_jeap6500', 'udaya_a6-id2', 'udaya_a6-od2', 'yuncore_ax820', 'yuncore_ax840', 'yuncore_fap640', 'yuncore_fap650', 'yuncore_fap655', 'emplus_wap588m', 'zyxel_nwa130be', 'sercomm_ap72tip-v4' ]
+        target: [ 'cig_wf189h', 'cig_wf189w', 'cig_wf660a', 'cig_wf672', 'cig_wf186h', 'cig_wf186w', 'cig_wf188n', 'cig_wf189', 'cig_wf196', 'cig_wf196', 'cybertan_eww631-a1', 'cybertan_eww631-b1', 'sonicfi_rap630w-312g', 'sonicfi_rap63xc-211g', 'sonicfi_rap630c-311g', 'sonicfi_rap630w-311g', 'sonicfi_rap630w-211g', 'sonicfi_rap650c', 'sonicfi_rap7110c-341x', 'sonicfi_rap750e-h', 'sonicfi_rap750e-s', 'sonicfi_rap750w-311a', 'edgecore_eap101', 'edgecore_eap102', 'edgecore_eap104', 'edgecore_eap105', 'edgecore_eap111', 'edgecore_eap112', 'edgecore_oap101', 'edgecore_oap101-6e', 'edgecore_oap101e', 'edgecore_oap101e-6e', 'edgecore_oap103', 'hfcl_ion4xe', 'hfcl_ion4xi', 'hfcl_ion4x', 'hfcl_ion4x_2', 'hfcl_ion4x_3', 'hfcl_ion4xi_w', 'hfcl_ion4x_w', 'indio_um-305ax', 'senao_iap4300m', 'senao_iap2300m', 'senao_jeap6500', 'udaya_a6-id2', 'udaya_a6-od2', 'yuncore_ax820', 'yuncore_ax840', 'yuncore_fap640', 'yuncore_fap650', 'yuncore_fap655', 'emplus_wap588m', 'zyxel_nwa130be', 'zyxel_nwa50be', 'sercomm_ap72tip-v4' ]
     steps:
     - uses: actions/checkout@v3
 

feeds/qca-wifi-7/ath12k-wifi/Makefile

@@ -93,6 +93,11 @@ $(call Package/ath12k-wifi-default)
     TITLE:=board-2.bin for NWA130BE
 endef
 
+define Package/ath12k-wifi-zyxel-nwa50be
+$(call Package/ath12k-wifi-default)
+    TITLE:=board-2.bin for NWA50BE
+endef
+
 define Package/ath12k-wifi-cig-wf672
 $(call Package/ath12k-wifi-default)
     TITLE:=board-2.bin for WF672
@@ -191,6 +196,14 @@ define Package/ath12k-wifi-zyxel-nwa130be/install
 	$(INSTALL_DATA) ./board-2.bin.nwa130be.IPQ5332 $(1)/lib/firmware/ath12k/IPQ5332/hw1.0/board-2.bin
 endef
 
+define Package/ath12k-wifi-zyxel-nwa50be/install
+	$(INSTALL_DIR) $(1)/lib/firmware/ath12k/QCN6432/hw1.0/
+	$(INSTALL_DIR) $(1)/lib/firmware/ath12k/IPQ5332/hw1.0/
+	$(INSTALL_DATA) ./board-2.bin.nwa50be.QCN6432 $(1)/lib/firmware/ath12k/QCN6432/hw1.0/board-2.bin
+	$(INSTALL_DATA) ./board-2.bin.nwa50be.IPQ5332 $(1)/lib/firmware/ath12k/IPQ5332/hw1.0/board-2.bin
+	$(INSTALL_DATA) ./ipq5332_qcn6432.regdb $(1)/lib/firmware/ath12k/QCN6432/hw1.0/regdb.bin
+endef
+
 define Package/ath12k-wifi-cig-wf672/install
 	$(INSTALL_DIR) $(1)/lib/firmware/ath12k/QCN92XX/hw1.0/
 	$(INSTALL_DIR) $(1)/lib/firmware/ath12k/IPQ5332/hw1.0/
@@ -210,4 +223,5 @@ $(eval $(call BuildPackage,ath12k-wifi-cig-wf189h))
 $(eval $(call BuildPackage,ath12k-wifi-sercomm-ap72tip))
 $(eval $(call BuildPackage,ath12k-wifi-sercomm-ap72tip-v4))
 $(eval $(call BuildPackage,ath12k-wifi-zyxel-nwa130be))
+$(eval $(call BuildPackage,ath12k-wifi-zyxel-nwa50be))
 $(eval $(call BuildPackage,ath12k-wifi-cig-wf672))

feeds/qca-wifi-7/ath12k-wifi/board-2-nwa50be-IPQ5332.json

@@ -0,0 +1,20 @@
+[
+    {
+        "board": [
+            {
+                "names": [
+                    "bus=ahb,qmi-chip-id=0,qmi-board-id=18"
+                ],
+                "data": "nwa50be-IPQ5332.bin"
+            }
+        ],
+        "regdb": [
+            {
+                "names": [
+                    "bus=ahb,qmi-chip-id=0,qmi-board-id=18"
+                ],
+                "data": "ipq5332.regdb"
+            }
+        ]
+    }
+]

feeds/qca-wifi-7/ath12k-wifi/board-2-nwa50be-QCN6432.json

@@ -0,0 +1,20 @@
+[
+    {
+        "board": [
+            {
+                "names": [
+                    "bus=ahb,qmi-chip-id=0,qmi-board-id=112"
+                ],
+                "data": "nwa50be-QCN6432.bin"
+            }
+        ],
+        "regdb": [
+            {
+                "names": [
+                    "bus=ahb,qmi-chip-id=0,qmi-board-id=112"
+                ],
+                "data": "ipq5332_qcn6432.regdb"
+            }
+        ]
+    }
+]

feeds/qca-wifi-7/ath12k-wifi/generate.sh

@@ -18,3 +18,6 @@ $encoder -c board-2-ap72tip-v4-QCN92XX.json -o board-2.bin.ap72tip-v4.QCN92XX
 
 $encoder -c board-2-nwa130be-IPQ5332.json -o board-2.bin.nwa130be.IPQ5332
 $encoder -c board-2-nwa130be-QCN92XX.json -o board-2.bin.nwa130be.QCN92XX
+
+$encoder -c board-2-nwa50be-IPQ5332.json -o board-2.bin.nwa50be.IPQ5332
+$encoder -c board-2-nwa50be-QCN6432.json -o board-2.bin.nwa50be.QCN6432

feeds/qca-wifi-7/ipq53xx/base-files/etc/board.d/02_network

@@ -20,7 +20,8 @@ ipq53xx_setup_interfaces()
 		;;
 	sonicfi,rap7110c-341x|\
 	sonicfi,rap750e-h|\
-	sonicfi,rap750e-s)
+	sonicfi,rap750e-s|\
+	zyxel,nwa50be)
 		ucidef_set_interfaces_lan_wan "" "eth0"
 		;;
 	cig,wf189w)
@@ -127,6 +128,16 @@ qcom_setup_macs()
 		ucidef_set_wireless_macaddr_base 5g $(macaddr_add "$wan_mac" 3)
 		ucidef_set_wireless_macaddr_base 6g $(macaddr_add "$wan_mac" 4)
 		;;
+	zyxel,nwa50be)
+		wan_mac=$(cat /proc/cmdline)
+		wan_mac="${wan_mac##*hwaddr=}"
+		wan_mac="${wan_mac%% *}"
+		wan_mac="$(echo ${wan_mac} | sed 's/\(..\)/\1:/g;s/:$//')"
+		ucidef_set_network_device_mac eth0 $wan_mac
+		ucidef_set_label_macaddr $wan_mac
+		ucidef_set_wireless_macaddr_base 2g $(macaddr_add "$wan_mac" 1)
+		ucidef_set_wireless_macaddr_base 5g $(macaddr_add "$wan_mac" 2)
+		;;
         *)
                 wan_mac=$(cat /sys/class/net/eth1/address)
                 lan_mac=$(macaddr_add "$wan_mac" 1)

feeds/qca-wifi-7/ipq53xx/base-files/etc/hotplug.d/firmware/10-ath12k-caldata

@@ -67,8 +67,9 @@ ath12k/IPQ5332/hw1.0/caldata.bin)
 	emplus,wap7635|\
 	sercomm,ap72tip-v4|\
 	sercomm,ap72tip|\
-	zyxel,nwa130be)
-		caldata_extract "0:ART" 0x1000 0x20000 
+	zyxel,nwa130be|\
+	zyxel,nwa50be)
+		caldata_extract "0:ART" 0x1000 0x20000
 		;;
 	cig,wf672)
 		cig_ipq5322_cal
@@ -124,6 +125,9 @@ ath12k/QCN6432/hw1.0/cal-ahb-soc@0:wifi2@c0000000.bin)
 	cig,wf189w)
 		caldata_extract "0:ART" 0x58800 0x20000
 		;;
+	zyxel,nwa50be)
+		caldata_extract "0:ART" 0x58800 0x2d000
+		;;
 	esac
 	;;
 ath12k/IPQ5332/hw1.0/board-2.bin)

feeds/qca-wifi-7/ipq53xx/base-files/lib/upgrade/platform.sh

@@ -174,7 +174,8 @@ platform_do_upgrade() {
 		sonicfi_dualimage_check
 		nand_upgrade_tar "$1"
 		;;
-	zyxel,nwa130be)
+	zyxel,nwa130be|\
+	zyxel,nwa50be)
 		nand_upgrade_tar "$1"
 		;;
 	esac

feeds/qca-wifi-7/ipq53xx/dts/ipq5332-zyxel-nwa50be.dts

@@ -0,0 +1,956 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * IPQ5332 RDP442 board device tree source
+ *
+ * Copyright (c) 2020-2021 The Linux Foundation. All rights reserved.
+ * Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+/dts-v1/;
+
+#include "ipq5332.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
+#include "ipq5332-default-memory.dtsi"
+
+
+/ {
+	model = "Qualcomm Technologies, Inc. IPQ5332/RDP442/AP-MI01.3";
+	compatible = "zyxel,nwa50be", "qcom,ipq5332-ap-mi01.3", "qcom,ipq5332-rdp442", "qcom,ipq5332";
+
+#ifdef __IPQ_MEM_PROFILE_512_MB__
+
+	/*     512M  Layout for IPQ5332 + QCN6432 + QCN6432
+	 * +==========+==============+========================+
+	 * |         |              |                         |
+	 * |  Region | Start Offset |          Size           |
+	 * |         |              |                         |
+	 * +---------+--------------+-------------------------+
+	 * |   Q6    |              |                         |
+	 * |  code/  |  0x4A900000  |          25MB           |
+	 * |  data   |              |                         |
+	 * +---------+--------------+-------------------------+
+	 * | IPQ5332 |              |                         |
+	 * |  data   |  0x4C200000  |          17MB           |
+	 * +---------+--------------+-------------------------+
+	 * | IPQ5332 |              |                         |
+	 * | M3 Dump |  0x4D300000  |           1MB           |
+	 * +---------+--------------+-------------------------+
+	 * | IPQ5332 |              |                         |
+	 * |  QDSS   |  0x4D400000  |           1MB           |
+	 * +---------+--------------+-------------------------+
+	 * | IPQ5332 |              |                         |
+	 * |  CALDB  |  0x4D500000  |           3MB           |
+	 * +---------+--------------+-------------------------+
+	 * |QCN6432_1|              |                         |
+	 * |  data   |  0x4D800000  |          16MB           |
+	 * +---------+--------------+-------------------------+
+	 * |QCN6432_1|              |                         |
+	 * | M3 Dump |  0x4E800000  |           1MB           |
+	 * +---------+--------------+-------------------------+
+	 * |QCN6432_1|              |                         |
+	 * |  QDSS   |  0x4E900000  |           1MB           |
+	 * +---------+--------------+-------------------------+
+	 * |QCN6432_1|              |                         |
+	 * |  CALDB  |  0x4EA00000  |           5MB           |
+	 * +---------+--------------+-------------------------+
+	 * |QCN6432_2|              |                         |
+	 * |  data   |  0x4EF00000  |          16MB           |
+	 * +---------+--------------+-------------------------+
+	 * |QCN6432_2|              |                         |
+	 * | M3 Dump |  0x4FF00000  |           1MB           |
+	 * +---------+--------------+-------------------------+
+	 * |QCN6432_2|              |                         |
+	 * |  QDSS   |  0x50000000  |           1MB           |
+	 * +---------+--------------+-------------------------+
+	 * |QCN6432_2|              |                         |
+	 * |  CALDB  |  0x50100000  |           5MB           |
+	 * +---------+--------------+-------------------------+
+	 * |         |              |                         |
+	 * |   MLO   |  0x50600000  |          12MB           |
+	 * +==================================================+
+	 * |                                                  |
+	 * |                                                  |
+	 * |                                                  |
+	 * |             Rest of memory for Linux             |
+	 * |                                                  |
+	 * |                                                  |
+	 * |                                                  |
+	 * +==================================================+
+	 */
+
+	reserved-memory {
+
+		/delete-node/ m3_dump@4cc00000;
+		/delete-node/ q6_etr_dump@1;
+		/delete-node/ mlo_global_mem_0@0x4db00000;
+		/delete-node/ wcnss@4a900000;
+		/delete-node/ q6_caldb_region@4ce00000;
+
+		q6_mem_regions: q6_mem_regions@4A900000  {
+			reg = <0x0 0x4a900000 0x0 0x5D00000>;
+			no-map;
+		};
+
+		q6_code_data: q6_code_data@4A900000 {
+			reg = <0x0 0x4a900000 0x0 0x1900000>;
+			no-map;
+		};
+
+		q6_ipq5332_data: q6_ipq5332_data@4C200000 {
+			reg = <0x0 0x4C200000 0x0 0x1100000>;
+			no-map;
+		};
+
+		m3_dump: m3_dump@4D300000 {
+			reg = <0x0 0x4D300000 0x0 0x100000>;
+			no-map;
+		};
+
+		q6_etr_region: q6_etr_dump@4D400000 {
+			reg = <0x0 0x4D400000 0x0 0x100000>;
+			no-map;
+		};
+
+		q6_ipq5332_caldb: q6_ipq5332_caldb@4D500000 {
+			reg = <0x0 0x4D500000 0x0 0x300000>;
+			no-map;
+		};
+
+		q6_qcn6432_data_1: q6_qcn6432_data_1@4D800000 {
+			reg = <0x0 0x4D800000 0x0 0x1000000>;
+			no-map;
+		};
+
+		m3_dump_qcn6432_1: m3_dump_qcn6432_1@4E800000 {
+			reg = <0x0 0x4E800000 0x0 0x100000>;
+			no-map;
+                };
+
+		q6_qcn6432_etr_1: q6_qcn6432_etr_1@4E900000 {
+			reg = <0x0 0x4E900000 0x0 0x100000>;
+			no-map;
+		};
+
+		q6_qcn6432_caldb_1: q6_qcn6432_caldb_1@4EA00000 {
+			reg = <0x0 0x4EA00000 0x0 0x500000>;
+			no-map;
+		};
+
+		q6_qcn6432_data_2: q6_qcn6432_data_2@4EF00000 {
+			reg = <0x0 0x4EF00000 0x0 0x1000000>;
+			no-map;
+		};
+
+		m3_dump_qcn6432_2: m3_dump_qcn6432_2@4FF00000 {
+			reg = <0x0 0x4FF00000 0x0 0x100000>;
+			no-map;
+                };
+
+		q6_qcn6432_etr_2: q6_qcn6432_etr_2@50000000 {
+			reg = <0x0 0x50000000 0x0 0x100000>;
+			no-map;
+		};
+
+		q6_qcn6432_caldb_2: q6_qcn6432_caldb_2@50100000 {
+			reg = <0x0 0x50100000 0x0 0x500000>;
+			no-map;
+		};
+
+		mlo_global_mem0: mlo_global_mem_0@50600000 {
+			reg = <0x0 0x50600000 0x0 0xC00000>;
+			no-map;
+		};
+	};
+#else
+
+	/*  1G  Layout for IPQ5332 + QCN6432 + QCN6432
+	* +==========+==============+========================+
+	* |         |              |                         |
+	* |  Region | Start Offset |          Size           |
+	* |         |              |                         |
+	* +---------+--------------+-------------------------+
+	* |   Q6    |              |                         |
+	* |  code/  |  0x4A900000  |          25MB           |
+	* |  data   |              |                         |
+	* +---------+--------------+-------------------------+
+	* | IPQ5332 |              |                         |
+	* |  data   |  0x4C200000  |          21MB           |
+	* +---------+--------------+-------------------------+
+	* | IPQ5332 |              |                         |
+	* | M3 Dump |  0x4D700000  |           1MB           |
+	* +---------+--------------+-------------------------+
+	* | IPQ5332 |              |                         |
+	* |  QDSS   |  0x4D800000  |           1MB           |
+	* +---------+--------------+-------------------------+
+	* | IPQ5332 |              |                         |
+	* |  CALDB  |  0x4D900000  |           5MB           |
+	* +---------+--------------+-------------------------+
+	* |QCN6432_1|              |                         |
+	* |  data   |  0x4DE00000  |          21MB           |
+	* +---------+--------------+-------------------------+
+	* |QCN6432_1|              |                         |
+	* | M3 Dump |  0x4F300000  |           1MB           |
+	* +---------+--------------+-------------------------+
+	* |QCN6432_1|              |                         |
+	* |  QDSS   |  0x4F400000  |           1MB           |
+	* +---------+--------------+-------------------------+
+	* |QCN6432_1|              |                         |
+	* |  CALDB  |  0x4F500000  |           5MB           |
+	* +---------+--------------+-------------------------+
+	* |QCN6432_2|              |                         |
+	* |  data   |  0x4FA00000  |          21MB           |
+	* +---------+--------------+-------------------------+
+	* |QCN6432_2|              |                         |
+	* | M3 Dump |  0x50F00000  |           1MB           |
+	* +---------+--------------+-------------------------+
+	* |QCN6432_2|              |                         |
+	* |  QDSS   |  0x51000000  |           1MB           |
+	* +---------+--------------+-------------------------+
+	* |QCN6432_2|              |                         |
+	* |  CALDB  |  0x51100000  |           5MB           |
+	* +---------+--------------+-------------------------+
+	* |         |              |                         |
+	* |   MLO   |  0x51600000  |          12MB           |
+	* +==================================================+
+	* |                                                  |
+	* |                                                  |
+	* |                                                  |
+	* |             Rest of memory for Linux             |
+	* |                                                  |
+	* |                                                  |
+	* |                                                  |
+	* +==================================================+
+	*/
+	reserved-memory {
+
+		/delete-node/ m3_dump@4cc00000;
+		/delete-node/ q6_etr_dump@1;
+		/delete-node/ mlo_global_mem_0@0x4db00000;
+		/delete-node/ wcnss@4a900000;
+		/delete-node/ q6_caldb_region@4ce00000;
+
+		ramoops@49c00000 {
+			compatible = "ramoops";
+			reg = <0x0 0x49c00000 0x0 0x100000>;
+			record-size = <0x20000>;
+			console-size = <0x20000>;
+			pmsg-size = <0x20000>;
+		};
+
+		q6_mem_regions: q6_mem_regions@4A900000  {
+			no-map;
+			reg = <0x0 0x4a900000 0x0 0x6D00000>;
+		};
+
+		q6_code_data: q6_code_data@4A900000 {
+			no-map;
+			reg = <0x0 0x4a900000 0x0 0x1900000>;
+		};
+
+		q6_ipq5332_data: q6_ipq5332_data@4C200000 {
+			no-map;
+			reg = <0x0 0x4C200000 0x0 0x1500000>;
+		};
+
+		m3_dump: m3_dump@4D700000 {
+			no-map;
+			reg = <0x0 0x4D700000 0x0 0x100000>;
+		};
+
+		q6_etr_region: q6_etr_dump@4D800000 {
+			no-map;
+			reg = <0x0 0x4D800000 0x0 0x100000>;
+		};
+
+		q6_ipq5332_caldb: q6_ipq5332_caldb@4D900000 {
+			no-map;
+			reg = <0x0 0x4D900000 0x0 0x500000>;
+		};
+
+		q6_qcn6432_data_1: q6_qcn6432_data_1@4DE00000 {
+			no-map;
+			reg = <0x0 0x4DE00000 0x0 0x1500000>;
+		};
+
+		m3_dump_qcn6432_1: m3_dump_qcn6432_1@4F300000 {
+			no-map;
+			reg = <0x0 0x4F300000 0x0 0x100000>;
+        };
+
+		q6_qcn6432_etr_1: q6_qcn6432_etr_1@4F400000 {
+			no-map;
+			reg = <0x0 0x4F400000 0x0 0x100000>;
+		};
+
+		q6_qcn6432_caldb_1: q6_qcn6432_caldb_1@4F500000 {
+			no-map;
+			reg = <0x0 0x4F500000 0x0 0x500000>;
+		};
+
+		q6_qcn6432_data_2: q6_qcn6432_data_2@4FA00000 {
+			no-map;
+			reg = <0x0 0x4FA00000 0x0 0x1500000>;
+		};
+
+		m3_dump_qcn6432_2: m3_dump_qcn6432_2@50F00000 {
+			no-map;
+			reg = <0x0 0x50F00000 0x0 0x100000>;
+		};
+
+		q6_qcn6432_etr_2: q6_qcn6432_etr_2@51000000 {
+			no-map;
+			reg = <0x0 0x51000000 0x0 0x100000>;
+		};
+
+		q6_qcn6432_caldb_2: q6_qcn6432_caldb_2@51100000 {
+			no-map;
+			reg = <0x0 0x51100000 0x0 0x500000>;
+		};
+
+		mlo_global_mem0: mlo_global_mem_0@51600000 {
+			no-map;
+			reg = <0x0 0x51600000 0x0 0xC00000>;
+		};
+	};
+#endif
+
+	aliases {
+		serial0 = &blsp1_uart0;
+		serial1 = &blsp1_uart1;
+		ethernet0 = "/soc/dp1";
+		ethernet1 = "/soc/dp2";
+	};
+
+	chosen {
+		stdout-path = "serial0";
+	};
+
+	soc@0 {
+		mdio:mdio@90000 {
+			pinctrl-0 = <&mdio1_pins>;
+			pinctrl-names = "default";
+			/*gpio22 is for wan napa, gpio51 for lan napa*/
+			phy-reset-gpio = <&tlmm 51 GPIO_ACTIVE_LOW>;
+			status = "okay";
+
+			phy2: ethernet-phy@2 {
+				reg = <28>;
+			};
+		};
+
+		leds {
+			compatible = "gpio-leds";
+			pinctrl-0 = <&led_pins>;
+			pinctrl-names = "default";
+			led_blue{
+				label = "led_blue";
+				gpio = <&tlmm 22 GPIO_ACTIVE_HIGH>;
+				linux,default-trigger = "led_blue";
+				default-state = "off";
+			};
+			led_green {
+				label = "led_green";
+				gpio = <&tlmm 45 GPIO_ACTIVE_HIGH>;
+				linux,default-trigger = "led_green";
+				default-state = "on";
+			};
+			led_white {
+				label = "led_white";
+				gpio = <&tlmm 43 GPIO_ACTIVE_HIGH>;
+				linux,default-trigger = "led_white";
+				default-state = "off";
+			};
+			led_red {
+				label = "led_red";
+				gpio = <&tlmm 44 GPIO_ACTIVE_HIGH>;
+				linux,default-trigger = "led_red";
+				default-state = "off";
+			};
+		};
+
+		gpio_keys {
+			compatible = "gpio-keys";
+			pinctrl-0 = <&button_pins>;
+			pinctrl-names = "default";
+			status = "okay";
+
+			button@1 {
+				label = "reset";
+				linux,code = <KEY_RESTART>;
+				gpios = <&tlmm 30 GPIO_ACTIVE_LOW>;
+				linux,input-type = <1>;
+				debounce-interval = <60>;
+			};
+		};
+
+		ess-instance {
+			ess-switch@3a000000 {
+				switch_cpu_bmp = <0x1>;  /* cpu port bitmap */
+				switch_lan_bmp = <0x4>; /* lan port bitmap */
+				switch_wan_bmp = <0x0>; /* wan port bitmap */
+				switch_mac_mode = <0xf>; /* mac mode for uniphy instance0*/
+				switch_mac_mode1 = <0xc>; /* mac mode for uniphy instance1*/
+				switch_mac_mode2 = <0xff>; /* mac mode for uniphy instance2*/
+				qcom,port_phyinfo {
+					port@0 {
+						port_id = <2>;
+						phy_address = <28>;
+					};
+				};
+				qcom,port_ledinfo {
+					port@0 {
+						port = <2>;
+						led_source@0 {
+							source = <0>;
+							mode = "normal";
+							speed = "2500M";
+							active = "high";
+							blink_en = "enable";
+						};
+						led_source@1 {
+							source = <1>;
+							mode = "normal";
+							speed = "10M", "100M","1000M";
+							active = "high";
+							blink_en = "enable";
+						};
+					};
+				};
+			};
+		};
+
+		dp1 {
+			device_type = "network";
+			compatible = "qcom,nss-dp";
+			qcom,id = <2>;
+			reg = <0x3a504000 0x4000>;
+			qcom,mactype = <1>;
+			local-mac-address = [000000000000];
+			mdio-bus = <&mdio>;
+			qcom,phy-mdio-addr = <28>;
+			qcom,link-poll = <1>;
+			phy-mode = "sgmii";
+		};
+
+		nss-macsec0 {
+			compatible = "qcom,nss-macsec";
+			phy_addr = <28>;
+			mdiobus = <&mdio>;
+		};
+
+		/* EDMA host driver configuration for the board */
+		edma@3ab00000 {
+			qcom,txdesc-ring-start = <4>;		/* Tx desc ring start ID */
+			qcom,txdesc-rings = <12>;		/* Total number of Tx desc rings to be provisioned */
+			qcom,mht-txdesc-rings = <8>;            /* Extra Tx desc rings to be provisioned for MHT SW ports */
+			qcom,txcmpl-ring-start = <4>;		/* Tx complete ring start ID */
+			qcom,txcmpl-rings = <12>;		/* Total number of Tx complete rings to be provisioned */
+			qcom,mht-txcmpl-rings = <8>;            /* Extra Tx complete rings to be provisioned for mht sw ports. */
+			qcom,rxfill-ring-start = <4>;		/* Rx fill ring start ID */
+			qcom,rxfill-rings = <4>;		/* Total number of Rx fill rings to be provisioned */
+			qcom,rxdesc-ring-start = <12>;		/* Rx desc ring start ID */
+			qcom,rxdesc-rings = <4>;		/* Total number of Rx desc rings to be provisioned */
+			qcom,rx-page-mode = <0>;		/* Rx fill ring page mode */
+			qcom,tx-map-priority-level = <1>;	/* Tx priority level per port */
+			qcom,rx-map-priority-level = <1>;	/* Rx priority level per core */
+			qcom,ppeds-num = <2>;			/* Number of PPEDS nodes */
+			/* PPE-DS node format: <Rx-fill Tx-cmpl Rx Tx Queue-base Queue-count> */
+			qcom,ppeds-map = <1 1 1 1 32 8>,	/* PPEDS Node#0 ring and queue map */
+					<2 2 2 2 40 8>;		/* PPEDS Node#1 ring and queue map */
+			qcom,txdesc-map = <8 9 10 11>,		/* Port0 per-core Tx ring map */
+					<12 13 14 15>,        /* MHT-Port1 per-core Tx ring map */
+					<4 5 6 7>,            /* MHT-Port2 per-core Tx ring map/packets from  vp*/
+					<16 17 18 19>,        /* MHT-Port3 per-core Tx ring map */
+					<20 21 22 23>;        /* MHT-Port4 per-core Tx ring map */
+			qcom,txdesc-fc-grp-map = <1 2 3 4 5>;   /* Per GMAC flow control group map */
+			qcom,rxfill-map = <4 5 6 7>;		/* Per-core Rx fill ring map */
+			qcom,rxdesc-map = <12 13 14 15>;	/* Per-core Rx desc ring map */
+			qcom,rx-queue-start = <0>;		/* Rx queue start */
+			qcom,rx-ring-queue-map = <0 8 16 24>,	/* Priority 0 queues per-core Rx ring map */
+						<1 9 17 25>,	/* Priority 1 queues per-core Rx ring map */
+						<2 10 18 26>,	/* Priority 2 queues per-core Rx ring map */
+						<3 11 19 27>,	/* Priority 3 queues per-core Rx ring map */
+						<4 12 20 28>,	/* Priority 4 queues per-core Rx ring map */
+						<5 13 21 29>,	/* Priority 5 queues per-core Rx ring map */
+						<6 14 22 30>,	/* Priority 6 queues per-core Rx ring map */
+						<7 15 23 31>;	/* Priority 7 queues per-core Rx ring map */
+			interrupts = <0 163 4>,			/* Tx complete ring id #4 IRQ info */
+				   <0 164 4>,			/* Tx complete ring id #5 IRQ info */
+				   <0 165 4>,			/* Tx complete ring id #6 IRQ info */
+				   <0 166 4>,			/* Tx complete ring id #7 IRQ info */
+				   <0 167 4>,			/* Tx complete ring id #8 IRQ info */
+				   <0 168 4>,			/* Tx complete ring id #9 IRQ info */
+				   <0 169 4>,			/* Tx complete ring id #10 IRQ info */
+				   <0 170 4>,			/* Tx complete ring id #11 IRQ info */
+				   <0 171 4>,			/* Tx complete ring id #12 IRQ info */
+				   <0 172 4>,			/* Tx complete ring id #13 IRQ info */
+				   <0 173 4>,			/* Tx complete ring id #14 IRQ info */
+				   <0 174 4>,			/* Tx complete ring id #15 IRQ info */
+				   <0 139 4>,			/* Rx desc ring id #12 IRQ info */
+				   <0 140 4>,			/* Rx desc ring id #13 IRQ info */
+				   <0 141 4>,			/* Rx desc ring id #14 IRQ info */
+				   <0 142 4>,			/* Rx desc ring id #15 IRQ info */
+				   <0 191 4>,			/* Misc error IRQ info */
+				<0 160 4>,			/* PPEDS Node #1(TxComp ring id #1) TxComplete IRQ info */
+				<0 128 4>,			/* PPEDS Node #1(Rx Desc ring id #1) Rx Desc IRQ info */
+				<0 152 4>,			/* PPEDS Node #1(RxFill Desc ring id #1) Rx Fill IRQ info */
+				<0 161 4>,			/* PPEDS Node #2(TxComp ring id #2) TxComplete IRQ info */
+				<0 129 4>,			/* PPEDS Node #2(Rx Desc ring id #2) Rx Desc IRQ info */
+				<0 153 4>,                      /* PPEDS Node #2(RxFill Desc ring id #2) Rx Fill IRQ info */
+				<0 175 4>,                   /* MHT port Tx complete ring id #16 IRQ info */
+				<0 176 4>,                   /* MHT port Tx complete ring id #17 IRQ info */
+				<0 177 4>,                   /* MHT port Tx complete ring id #18 IRQ info */
+				<0 178 4>,                   /* MHT port Tx complete ring id #19 IRQ info */
+				<0 179 4>,                   /* MHT port Tx complete ring id #20 IRQ info */
+				<0 180 4>,                   /* MHT port Tx complete ring id #21 IRQ info */
+				<0 181 4>,                   /* MHT port Tx complete ring id #22 IRQ info */
+				<0 182 4>;                   /* MHT port Tx complete ring id #23 IRQ info */
+		};
+
+		wsi: wsi {
+			id = <0>;
+			num_chip = <2>;
+			chip_info = <0 1 1>,
+				    <1 1 0>;
+		};
+
+		q6v5_wcss: remoteproc@d100000 {
+			boot-args = <0x1 0x4 0x3 0x0 0x26 0x2>,
+					<0x1 0x4 0x4 0x1 0x2f 0x2>;
+			memory-region = <&q6_mem_regions>;
+
+			/delete-node/ remoteproc_pd1;
+			/delete-node/ remoteproc_pd2;
+			/delete-node/ remoteproc_pd3;
+
+			q6_wcss_pd4: remoteproc_pd4 {
+				compatible = "qcom,ipq5332-mpd-upd-text";
+				firmware = "IPQ5332/q6_fw4.mdt";
+
+				q6_wcss_pd1: remoteproc_pd1 {
+					compatible = "qcom,ipq5332-wcss-ahb-mpd";
+					firmware = "IPQ5332/q6_fw1.mdt";
+					m3_firmware = "IPQ5332/iu_fw.mdt";
+					interrupts-extended = <&wcss_smp2p_in 8 0>,
+							<&wcss_smp2p_in 9 0>,
+							<&wcss_smp2p_in 12 0>,
+							<&wcss_smp2p_in 11 0>;
+					interrupt-names = "fatal",
+							"ready",
+							"spawn-ack",
+							"stop-ack";
+
+					qcom,smem-states = <&wcss_smp2p_out 8>,
+							<&wcss_smp2p_out 9>,
+							<&wcss_smp2p_out 10>;
+					qcom,smem-state-names = "shutdown",
+								"stop",
+								"spawn";
+					memory-region = <&q6_ipq5332_data>,
+							<&m3_dump>,
+							<&q6_etr_region>,
+							<&q6_ipq5332_caldb>;
+				};
+
+				q6_wcss_pd2: remoteproc_pd2 {
+					compatible = "qcom,ipq5332-wcss-pcie-mpd";
+					firmware = "IPQ5332/q6_fw2.mdt";
+					m3_firmware = "qcn6432/iu_fw.mdt";
+					interrupts-extended = <&wcss_smp2p_in 16 0>,
+							<&wcss_smp2p_in 17 0>,
+							<&wcss_smp2p_in 20 0>,
+							<&wcss_smp2p_in 19 0>;
+					interrupt-names = "fatal",
+							"ready",
+							"spawn-ack",
+							"stop-ack";
+
+					qcom,smem-states = <&wcss_smp2p_out 16>,
+							<&wcss_smp2p_out 17>,
+							<&wcss_smp2p_out 18>;
+					qcom,smem-state-names = "shutdown",
+								"stop",
+								"spawn";
+					memory-region = <&q6_qcn6432_data_1>,
+							<&m3_dump_qcn6432_1>,
+							<&q6_qcn6432_etr_1>,
+							<&q6_qcn6432_caldb_1>;
+					status = "okay";
+				};
+
+				q6_wcss_pd3: remoteproc_pd3 {
+					compatible = "qcom,ipq5332-wcss-pcie-mpd";
+					firmware = "IPQ5332/q6_fw3.mdt";
+					interrupts-extended = <&wcss_smp2p_in 24 0>,
+							<&wcss_smp2p_in 25 0>,
+							<&wcss_smp2p_in 28 0>,
+							<&wcss_smp2p_in 27 0>;
+					interrupt-names = "fatal",
+							"ready",
+							"spawn-ack",
+							"stop-ack";
+
+					qcom,smem-states = <&wcss_smp2p_out 24>,
+							<&wcss_smp2p_out 25>,
+							<&wcss_smp2p_out 26>;
+					qcom,smem-state-names = "shutdown",
+								"stop",
+								"spawn";
+					memory-region = <&q6_qcn6432_data_2>,
+							<&m3_dump_qcn6432_2>,
+							<&q6_qcn6432_etr_2>,
+							<&q6_qcn6432_caldb_2>;
+					status = "okay";
+				};
+			};
+		};
+	};
+};
+
+&blsp1_uart0 {
+	pinctrl-0 = <&serial_0_pins>;
+	pinctrl-names = "default";
+	status = "okay";
+};
+
+&blsp1_uart1 {
+        pinctrl-0 = <&serial_1_pins>;
+        pinctrl-names = "default";
+        status = "disabled";
+};
+
+&blsp1_i2c1 {
+	clock-frequency  = <400000>;
+	pinctrl-0 = <&i2c_1_pins>;
+	pinctrl-names = "default";
+	status = "disabled";
+};
+
+&blsp1_spi0 {
+	pinctrl-0 = <&spi_0_data_clk_pins &spi_0_cs_pins>;
+	pinctrl-names = "default";
+	status = "okay";
+
+	flash@0 {
+		compatible = "n25q128a11", "micron,n25q128a11", "jedec,spi-nor";
+		reg = <0>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		spi-max-frequency = <50000000>;
+	};
+};
+
+&sdhc {
+	bus-width = <4>;
+	max-frequency = <192000000>;
+	mmc-ddr-1_8v;
+	mmc-hs200-1_8v;
+	non-removable;
+	pinctrl-0 = <&sdc_default_state>;
+	pinctrl-names = "default";
+	status = "disabled";
+};
+
+&sleep_clk {
+	clock-frequency = <32000>;
+};
+
+&xo {
+	clock-frequency = <24000000>;
+};
+
+&qpic_bam {
+	status = "okay";
+};
+
+&qpic_nand {
+	pinctrl-0 = <&qspi_default_state>;
+	pinctrl-names = "default";
+	status = "okay";
+
+	nandcs@0 {
+		reg = <0>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		nand-ecc-strength = <8>;
+		nand-ecc-step-size = <512>;
+		nand-bus-width = <8>;
+	};
+};
+
+/* PINCTRL */
+
+&tlmm {
+
+	led_pins: led_pins {
+		board_info {
+			pins = "gpio2", "gpio3";
+			function = "gpio";
+			drive-strength = <8>;
+			bias-pull-down;
+			input-enable;
+		};
+
+		apd_dc_in {
+			pins = "gpio24";
+			function = "gpio";
+			drive-strength = <8>;
+			bias-pull-down; //Adapter un-plug
+			input-enable;
+		};
+
+		poe_status {
+			pins = "gpio34";
+			function = "gpio";
+			drive-strength = <8>;
+			bias-pull-up; //AF
+			input-enable;
+		};
+
+		/* To MR pin */
+		rst_mb {
+			pins = "gpio29";
+			function = "gpio";
+			drive-strength = <8>;
+			output-high;
+		};
+
+		led_blue {
+			pins = "gpio22";
+			function = "gpio";
+			drive-strength = <8>;
+			bias-pull-down;
+		};
+
+		led_green {
+			pins = "gpio45";
+			function = "gpio";
+			drive-strength = <8>;
+			bias-pull-down;
+		};
+
+		led_white {
+			pins = "gpio43";
+			function = "gpio";
+			drive-strength = <8>;
+			bias-pull-down;
+		};
+
+		led_red {
+			pins = "gpio44";
+			function = "gpio";
+			drive-strength = <8>;
+			bias-pull-down;
+		};
+	};
+
+	qspi_default_state: qspi-default-state {
+		qspi_clock {
+			pins = "gpio13";
+			function = "qspi_clk";
+			drive-strength = <8>;
+			bias-pull-down;
+		};
+
+		qspi_cs {
+			pins = "gpio12";
+			function = "qspi_cs";
+			drive-strength = <8>;
+			bias-pull-up;
+		};
+
+		qspi_data {
+			pins = "gpio8", "gpio9", "gpio10", "gpio11";
+			function = "qspi_data";
+			drive-strength = <8>;
+			bias-pull-down;
+		};
+	};
+
+	serial_1_pins: serial1-pinmux {
+		pins = "gpio33", "gpio34", "gpio35", "gpio36";
+		function = "blsp1_uart2";
+		drive-strength = <8>;
+		bias-pull-up;
+	};
+
+	i2c_1_pins: i2c-1-state {
+		pins = "gpio29", "gpio30";
+		function = "blsp1_i2c0";
+		drive-strength = <8>;
+		bias-pull-up;
+	};
+
+	button_pins: button-state {
+		pins = "gpio35";
+		function = "gpio";
+		drive-strength = <8>;
+		bias-pull-up;
+	};
+
+	pwm_pins: pwm-state {
+		pins = "gpio46";
+		function = "pwm0";
+		drive-strength = <8>;
+	};
+
+	sdc_default_state: sdc-default-state {
+		clk-pins {
+			pins = "gpio13";
+			function = "sdc_clk";
+			drive-strength = <8>;
+			bias-disable;
+		};
+
+		cmd-pins {
+			pins = "gpio12";
+			function = "sdc_cmd";
+			drive-strength = <8>;
+			bias-pull-up;
+		};
+
+		data-pins {
+			pins = "gpio8", "gpio9", "gpio10", "gpio11";
+			function = "sdc_data";
+			drive-strength = <8>;
+			bias-pull-up;
+		};
+	};
+
+	spi_0_data_clk_pins: spi-0-data-clk-state {
+		pins = "gpio14", "gpio15", "gpio16";
+		function = "blsp0_spi";
+		drive-strength = <2>;
+		bias-pull-down;
+	};
+
+	spi_0_cs_pins: spi-0-cs-state {
+		pins = "gpio17";
+		function = "blsp0_spi";
+		drive-strength = <2>;
+		bias-pull-up;
+	};
+
+	mdio1_pins: mdio1-state {
+		mux_0 {
+			pins = "gpio27";
+			function = "mdc1";
+			drive-strength = <2>;
+			bias-pull-up;
+		};
+		mux_1 {
+			pins = "gpio28";
+			function = "mdio1";
+			drive-strength = <2>;
+			bias-pull-up;
+		};
+	};
+};
+
+&license_manager {
+	status = "okay";
+};
+
+&usb3 {
+	qcom,select-utmi-as-pipe-clk;
+	status = "okay";
+
+	dwc3@8a00000 {
+		/delete-property/ #phy-cells;
+		/delete-property/ phys;
+		/delete-property/ phy-names;
+	};
+};
+
+&pwm {
+	pinctrl-0 = <&pwm_pins>;
+	pinctrl-names = "default";
+	status = "okay";
+};
+
+&hs_m31phy_0 {
+	status = "okay";
+};
+
+&wifi0 {
+	qcom,multipd_arch;
+	qcom,rproc = <&q6_wcss_pd1>;
+	qcom,rproc_rpd = <&q6v5_wcss>;
+	qcom,userpd-subsys-name = "q6v5_wcss_userpd1";
+	qcom,bdf-addr = <0x4C200000 0x4C200000 0x4C200000 0x0 0x0 0x0>;
+	qcom,caldb-addr = <0x4D900000 0x4D500000 0x0 0x0 0x0 0x0>;
+#ifdef __IPQ_MEM_PROFILE_512_MB__
+	qcom,tgt-mem-mode = <1>;
+	qcom,caldb-size = <0x300000>;
+#else
+	qcom,tgt-mem-mode = <0>;
+	qcom,caldb-size = <0x500000>;
+#endif
+	qcom,board_id = <0x12>;
+#if defined(__CNSS2__)
+	mem-region = <&q6_ipq5332_data>;
+#else
+	memory-region = <&q6_ipq5332_data>;
+#endif
+	qcom,wsi = <&wsi>;
+	qcom,wsi_index = <0>;
+	status = "okay";
+};
+
+&wifi1 {
+	qcom,multipd_arch;
+	qcom,rproc = <&q6_wcss_pd2>;
+	qcom,rproc_rpd = <&q6v5_wcss>;
+	qcom,userpd-subsys-name = "q6v5_wcss_userpd2";
+	qcom,bdf-addr = <0x4DE00000 0x4D800000 0x0 0x0 0x0 0x0>;
+	qcom,caldb-addr = <0x4F500000 0x4EA00000 0x0 0x0 0x0 0x0>;
+	qcom,umac-irq-reset-addr = <0x20000884>;
+	qcom,caldb-size = <0x500000>;
+#ifdef __IPQ_MEM_PROFILE_512_MB__
+	qcom,tgt-mem-mode = <1>;
+#else
+	qcom,tgt-mem-mode = <0>;
+#endif
+	qcom,board_id = <0x060>;
+#if defined(__CNSS2__)
+	mem-region = <&q6_qcn6432_data_1>;
+#else
+	memory-region = <&q6_qcn6432_data_1>;
+#endif
+	qcom,wsi = <&wsi>;
+	qcom,wsi_index = <1>;
+	status = "disabled";
+	interrupts = <GIC_SPI 33 IRQ_TYPE_EDGE_RISING>;
+	interrupt-names = "umac_reset";
+};
+
+&wifi2 {
+	qcom,multipd_arch;
+	qcom,rproc = <&q6_wcss_pd3>;
+	qcom,rproc_rpd = <&q6v5_wcss>;
+	qcom,userpd-subsys-name = "q6v5_wcss_userpd3";
+	qcom,bdf-addr = <0x4FA00000 0x4EF00000 0x4FA00000 0x0 0x0 0x0>;
+	qcom,caldb-addr = <0x51100000 0x50100000 0x51100000 0x0 0x0 0x0>;
+	qcom,umac-irq-reset-addr = <0x18000884>;
+	qcom,caldb-size = <0x500000>;
+#ifdef __IPQ_MEM_PROFILE_512_MB__
+	qcom,tgt-mem-mode = <1>;
+#else
+	qcom,tgt-mem-mode = <0>;
+#endif
+	qcom,board_id = <0x070>;
+#if defined(__CNSS2__)
+	mem-region = <&q6_qcn6432_data_2>;
+#else
+	memory-region = <&q6_qcn6432_data_2>;
+#endif
+	qcom,wsi = <&wsi>;
+	qcom,wsi_index = <1>;
+	qcom,wide_band = <1>;
+	status = "okay";
+	interrupts = <GIC_SPI 410 IRQ_TYPE_EDGE_RISING>;
+	interrupt-names = "umac_reset";
+};

feeds/qca-wifi-7/ipq53xx/image/ipq53xx.mk

@@ -162,6 +162,22 @@ define Device/zyxel_nwa130be
 endef
 TARGET_DEVICES += zyxel_nwa130be
 
+
+define Device/zyxel_nwa50be
+  DEVICE_TITLE := Zyxel NWA50BE
+  DEVICE_DTS := ipq5332-zyxel-nwa50be
+  DEVICE_DTS_DIR := ../dts
+  DEVICE_DTS_CONFIG := config@mi01.3
+  IMAGES := sysupgrade.tar nand-factory.bin nand-factory.ubi
+  BLOCKSIZE := 128k
+  PAGESIZE := 2048
+  IMAGE/sysupgrade.tar := sysupgrade-tar | append-metadata
+  IMAGE/nand-factory.bin := append-ubi | qsdk-ipq-factory-nand
+  IMAGE/nand-factory.ubi := append-ubi
+  DEVICE_PACKAGES := ath12k-wifi-zyxel-nwa50be ath12k-firmware-ipq5332-peb-peb -ath12k-firmware-qcn92xx
+endef
+TARGET_DEVICES += zyxel_nwa50be
+
 define Device/cig_wf672
   DEVICE_TITLE := CIG WF672
   DEVICE_DTS := ipq5332-cig-wf672

feeds/qca-wifi-7/mac80211/patches-zyxel_nwa50be/ath12k/0001-thermal-thermal-setting.patch

@@ -0,0 +1,74 @@
+From 357da3320f8bcad056b905fb85cad3a29c343d31 Mon Sep 17 00:00:00 2001
+From: YenLin Pan <yenlin.pan@zyxel.com.tw>
+Date: Tue, 12 Aug 2025 15:41:39 +0800
+Subject: [PATCH] thermal: thermal setting
+
+lo0 -100 -hi0 105 -off0 0
+lo1 95 -hi1 110 -off1 20
+lo2 100 -hi2 115 -off2 60
+lo3 105 -hi3 119 -off3 98
+
+Signed-off-by: YenLin Pan <YenLin.Pan@zyxel.com.tw>
+---
+ drivers/net/wireless/ath/ath12k/thermal.h | 34 +++++++++++------------
+ 1 file changed, 17 insertions(+), 17 deletions(-)
+
+diff --git a/drivers/net/wireless/ath/ath12k/thermal.h b/drivers/net/wireless/ath/ath12k/thermal.h
+index 5c91906..e81f9a4 100644
+--- a/drivers/net/wireless/ath/ath12k/thermal.h
++++ b/drivers/net/wireless/ath/ath12k/thermal.h
+@@ -13,34 +13,34 @@
+ 
+ /* Below temperatures are in celsius */
+ #define ATH12K_THERMAL_LVL0_TEMP_LOW_MARK -100
+-#define ATH12K_THERMAL_LVL0_TEMP_HIGH_MARK 100
++#define ATH12K_THERMAL_LVL0_TEMP_HIGH_MARK 105
+ #define ATH12K_THERMAL_LVL1_TEMP_LOW_MARK 95
+-#define ATH12K_THERMAL_LVL1_TEMP_HIGH_MARK 105
++#define ATH12K_THERMAL_LVL1_TEMP_HIGH_MARK 110
+ #define ATH12K_THERMAL_LVL2_TEMP_LOW_MARK 100
+-#define ATH12K_THERMAL_LVL2_TEMP_HIGH_MARK 110
++#define ATH12K_THERMAL_LVL2_TEMP_HIGH_MARK 115
+ #define ATH12K_THERMAL_LVL3_TEMP_LOW_MARK 105
+-#define ATH12K_THERMAL_LVL3_TEMP_HIGH_MARK 120
++#define ATH12K_THERMAL_LVL3_TEMP_HIGH_MARK 119
+ 
+ #define ATH12K_THERMAL_LVL0_V2_TEMP_LOW_MARK -100
+-#define ATH12K_THERMAL_LVL0_V2_TEMP_HIGH_MARK 95
+-#define ATH12K_THERMAL_LVL1_V2_TEMP_LOW_MARK 90
+-#define ATH12K_THERMAL_LVL1_V2_TEMP_HIGH_MARK 100
+-#define ATH12K_THERMAL_LVL2_V2_TEMP_LOW_MARK 95
+-#define ATH12K_THERMAL_LVL2_V2_TEMP_HIGH_MARK 105
+-#define ATH12K_THERMAL_LVL3_V2_TEMP_LOW_MARK 100
+-#define ATH12K_THERMAL_LVL3_V2_TEMP_HIGH_MARK 110
++#define ATH12K_THERMAL_LVL0_V2_TEMP_HIGH_MARK 105
++#define ATH12K_THERMAL_LVL1_V2_TEMP_LOW_MARK 95
++#define ATH12K_THERMAL_LVL1_V2_TEMP_HIGH_MARK 110
++#define ATH12K_THERMAL_LVL2_V2_TEMP_LOW_MARK 100
++#define ATH12K_THERMAL_LVL2_V2_TEMP_HIGH_MARK 115
++#define ATH12K_THERMAL_LVL3_V2_TEMP_LOW_MARK 105
++#define ATH12K_THERMAL_LVL3_V2_TEMP_HIGH_MARK 119
+ #define ATH12K_THERMAL_LVL4_V2_TEMP_LOW_MARK 105
+ #define ATH12K_THERMAL_LVL4_V2_TEMP_HIGH_MARK 120
+ 
+ #define ATH12K_THERMAL_LVL0_DUTY_CYCLE 0
+-#define ATH12K_THERMAL_LVL1_DUTY_CYCLE 50
+-#define ATH12K_THERMAL_LVL2_DUTY_CYCLE 90
+-#define ATH12K_THERMAL_LVL3_DUTY_CYCLE 100
++#define ATH12K_THERMAL_LVL1_DUTY_CYCLE 20
++#define ATH12K_THERMAL_LVL2_DUTY_CYCLE 60
++#define ATH12K_THERMAL_LVL3_DUTY_CYCLE 98
+ 
+ #define ATH12K_THERMAL_LVL0_V2_DUTY_CYCLE ATH12K_THERMAL_LVL0_DUTY_CYCLE
+-#define ATH12K_THERMAL_LVL1_V2_DUTY_CYCLE ATH12K_THERMAL_LVL0_DUTY_CYCLE
+-#define ATH12K_THERMAL_LVL2_V2_DUTY_CYCLE ATH12K_THERMAL_LVL1_DUTY_CYCLE
+-#define ATH12K_THERMAL_LVL3_V2_DUTY_CYCLE ATH12K_THERMAL_LVL2_DUTY_CYCLE
++#define ATH12K_THERMAL_LVL1_V2_DUTY_CYCLE ATH12K_THERMAL_LVL1_DUTY_CYCLE
++#define ATH12K_THERMAL_LVL2_V2_DUTY_CYCLE ATH12K_THERMAL_LVL2_DUTY_CYCLE
++#define ATH12K_THERMAL_LVL3_V2_DUTY_CYCLE ATH12K_THERMAL_LVL3_DUTY_CYCLE
+ #define ATH12K_THERMAL_LVL4_V2_DUTY_CYCLE ATH12K_THERMAL_LVL3_DUTY_CYCLE
+ 
+ #define THERMAL_CONFIG_POUT0                        0
+-- 
+2.34.1
+

feeds/qca-wifi-7/qca-ssdk-qca/files-zyxel_nwa50be/qca-ssdk

@@ -0,0 +1,315 @@
+#!/bin/sh /etc/rc.common
+# Copyright (c) 2018, 2021, The Linux Foundation. All rights reserved.
+# Copyright (c) 2022-2024, Qualcomm Innovation Center, Inc. All rights reserved.
+#
+# Permission to use, copy, modify, and/or distribute this software for any
+# purpose with or without fee is hereby granted, provided that the above
+# copyright notice and this permission notice appear in all copies.
+#
+# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+# ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+# ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+# OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+#
+
+START=16
+
+#!/bin/sh
+ruletype="ip4 ip6"
+side="wan lan"
+qwan="1 3 2 0 5 7 6 4"
+qlan="0 1 2 3 4 5 6 7"
+
+function create_war_acl_rules(){
+	for lw in $side
+	do
+		#echo $lw
+		if [ "$lw" == "wan" ];then
+			listid=254
+			queue=$qwan
+			portmap=0x20
+		else
+			listid=255
+			queue=$qlan
+			portmap=0x1e
+		fi
+		#echo $queue
+		#echo "creating list $listid"
+		ssdk_sh acl list create $listid 255
+		ruleid=0
+		for rt in $ruletype
+		do
+			for qid in $queue
+			do
+				cmd="ssdk_sh acl rule add $listid $ruleid  1 n 0 0"
+				#echo $cmd
+				if [ "$rt" == "ip4" ];then
+					cmd="$cmd ip4 n n n n n n n n n n n n n n n n n n n n n n n n n n n n n"
+					#echo $cmd
+				else
+					cmd="$cmd ip6 n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n"
+					#echo $cmd
+				fi
+				if [ $ruleid -le 3 ];then
+					#non-zero dscp
+					cmd="$cmd y 0x0 0xff"
+				elif [ $ruleid -le 7 ];then
+					#zero dscp
+					cmd="$cmd n"
+				elif [ $ruleid -le 11 ];then
+					#non-zero dscp
+					cmd="$cmd y 0x0 0xff"
+				else
+					#zero dscp
+					cmd="$cmd n"
+				fi
+				p=$((ruleid/2))
+				cmd="$cmd y mask $((ruleid%2)) 0x1 y mask $((p%2)) 0x1 n n n n n n n n n n n n n n n y n n n n n n n y $qid n n 0 0 n n n n n n n n n n n n n n n n n n n n 0"
+				#echo $cmd
+				$cmd
+				ruleid=`expr $ruleid + 1`
+			done
+		done
+		ssdk_sh acl list bind $listid 0 1 $portmap
+	done
+}
+
+function create_war_cosmap(){
+	ssdk_sh cosmap pri2q set 0 0
+	ssdk_sh cosmap pri2q set 1 0
+	ssdk_sh cosmap pri2q set 2 0
+	ssdk_sh cosmap pri2q set 3 0
+	ssdk_sh cosmap pri2q set 4 1
+	ssdk_sh cosmap pri2q set 5 1
+	ssdk_sh cosmap pri2q set 6 1
+	ssdk_sh cosmap pri2q set 7 1
+	ssdk_sh cosmap pri2ehq set 0 0
+	ssdk_sh cosmap pri2ehq set 1 0
+	ssdk_sh cosmap pri2ehq set 2 0
+	ssdk_sh cosmap pri2ehq set 3 0
+	ssdk_sh cosmap pri2ehq set 4 1
+	ssdk_sh cosmap pri2ehq set 5 1
+	ssdk_sh cosmap pri2ehq set 6 1
+	ssdk_sh cosmap pri2ehq set 7 1
+}
+
+function create_acl_byp_egstp_rules(){
+	chip_ver=$1
+	cmd="ssdk_sh servcode config set 1 n 0 0xfffefc7f 0xffbdff 0 0 0 0 0 0"
+	if [ "$chip_ver" == "0x2000" ] || [ "$chip_ver" = "0x2001" ] || [ "$chip_ver" = "0x2100" ]; then
+		cmd="$cmd 0"
+	fi
+	#echo $cmd
+	$cmd
+
+	ssdk_sh acl list create 56 48
+	#action bypass eg stp check
+	action="y n n n n n n n n n n 0 0 n n n n n n n n n n n n n y n n n n n n n n n n n n y n n n n n n n n n n n n n n n n n n"
+	if [ "$chip_ver" == "0x2000" ]; then
+		action="$action n n 0"
+	elif [ "$chip_ver" = "0x2001" ] || [ "$chip_ver" = "0x2100" ]; then
+		action="$action n n n 0"
+	else
+		action="$action 0"
+	fi
+
+	for ruleid in $( seq 0 2 )
+	do
+		if [ "$ruleid" == "0" ];then
+			cmd="ssdk_sh acl rule add 56 0 1 n 0 0 mac n n n n n y 01-80-c2-00-00-00 ff-ff-ff-ff-ff-ff n n n n n n n n n n n n n n n n n n n n n n n"
+		elif [ "$ruleid" == "1" ];then
+			cmd="ssdk_sh acl rule add 56 1 1 n 0 0 mac n n n n n n n yes 0x8809 0xffff n n n n n n n n n n n n n n n n n n n n n"
+		else
+			cmd="ssdk_sh acl rule add 56 2 1 n 0 0 mac n n n n n n n yes 0x888e 0xffff n n n n n n n n n n n n n n n n n n n n n"
+		fi
+		if [ "$chip_ver" == "0x2000" ] || [ "$chip_ver" = "0x2001" ] || [ "$chip_ver" = "0x2100" ]; then
+			cmd="$cmd n $action"
+		else
+			cmd="$cmd $action"
+		fi
+		#echo $cmd
+		$cmd
+	done
+	ssdk_sh acl list bind 56 0 2 1
+}
+
+function delete_war_acl_rules(){
+	for lw in $side
+	do
+		#echo $lw
+		if [ "$lw" == "wan" ];then
+			listid=254
+			queue=$qwan
+			portmap=0x20
+		else
+			listid=255
+			queue=$qlan
+			portmap=0x1e
+		fi
+		ssdk_sh acl list unbind $listid 0 1 $portmap
+		for rt in $ruletype
+		do
+			for qid in $queue
+			do
+				cmd="ssdk_sh acl rule del $listid 0 1"
+				echo $cmd
+				$cmd
+			done
+		done
+		#echo "deleting list $listid"
+		ssdk_sh acl list destroy $listid
+	done
+}
+
+function delete_war_cosmap(){
+	ssdk_sh cosmap pri2q set 0 0
+	ssdk_sh cosmap pri2q set 1 0
+	ssdk_sh cosmap pri2q set 2 1
+	ssdk_sh cosmap pri2q set 3 1
+	ssdk_sh cosmap pri2q set 4 2
+	ssdk_sh cosmap pri2q set 5 2
+	ssdk_sh cosmap pri2q set 6 3
+	ssdk_sh cosmap pri2q set 7 3
+	ssdk_sh cosmap pri2ehq set 0 1
+	ssdk_sh cosmap pri2ehq set 1 0
+	ssdk_sh cosmap pri2ehq set 2 2
+	ssdk_sh cosmap pri2ehq set 3 2
+	ssdk_sh cosmap pri2ehq set 4 3
+	ssdk_sh cosmap pri2ehq set 5 3
+	ssdk_sh cosmap pri2ehq set 6 4
+	ssdk_sh cosmap pri2ehq set 7 5
+}
+
+function delete_acl_byp_egstp_rules(){
+	chip_ver=$1
+	cmd="ssdk_sh servcode config set 1 n 0 0xfffefcff 0xffbfff 0 0 0 0 0 0"
+	if [ "$chip_ver" == "0x2000" ] || [ "$chip_ver" = "0x2001" ] || [ "$chip_ver" = "0x2100" ]; then
+		cmd="$cmd 0"
+	fi
+	#echo $cmd
+	$cmd
+	ssdk_sh acl list unbind 56 0 2 1
+	ssdk_sh acl rule del 56 0 1
+	ssdk_sh acl rule del 56 1 1
+	ssdk_sh acl rule del 56 2 1
+	ssdk_sh acl list destroy 56
+}
+
+function edma_war_config_add(){
+	create_war_cosmap
+	ssdk_sh acl status set enable
+	create_war_acl_rules
+}
+
+function edma_war_config_del(){
+	delete_war_acl_rules
+	delete_war_cosmap
+}
+
+function ipq50xx_serdes_monitor () {
+	#if qca808x phy exist, need to monitor the serdes to avoid the effect for WIFI
+	port_id=2
+	old_linkstatus="DISABLE"
+	phy_id_info=`ssdk_sh port phyid get $port_id | grep Org | awk -F '!' '{print $2}'`
+	if [ "$phy_id_info" = "[Org ID]:0x004d[Rev ID]:0xd101" ]; then
+		ssdk_sh debug phy set 29 0xb 0x300d
+		ssdk_sh debug uniphy set 0 0x7ac 0x300d 4
+
+		while true
+		do
+			cur_linkstatus=`ssdk_sh port linkstatus get $port_id | grep Status | awk -F ':' '{print $2}'`
+			#when qca808x phy link status is from down to up, serdes tx would be enabled
+			if [ "$cur_linkstatus" = "ENABLE" ] && [ "$old_linkstatus" = "DISABLE" ]; then
+				ssdk_sh debug phy set 29 0xb 0xb00d
+				ssdk_sh debug uniphy set 0 0x7ac 0xb00d 4
+			fi
+			#when qca808x phy link status is from up to down, serdes tx would be disabled
+			if [ "$cur_linkstatus" = "DISABLE" ] && [ "$old_linkstatus" = "ENABLE" ]; then
+				ssdk_sh debug phy set 29 0xb 0x300d
+				ssdk_sh debug uniphy set 0 0x7ac 0x300d 4
+			fi
+			old_linkstatus=$cur_linkstatus
+		done
+	fi
+}
+
+function ipq53xx_phy_amplitude_set () {
+	#PHY (8081->5321): Full amplitude (bit[7:5]=000), half swing (bit[4]=1)
+	#for qca808x phy sgmii, set half amplitude with src_half_swing register
+	port_id=2
+	phy_addr=0x1d
+	phy_id_info=`ssdk_sh port phyid get $port_id | grep Org | awk -F '!' '{print $2}'`
+	if [ "$phy_id_info" = "[Org ID]:0x004d[Rev ID]:0xd101" ]; then
+		ssdk_sh debug phy set $phy_addr 0x40010087 0x208a
+		#Set the Reg0x67 bits[7:5]=3’b000 and bit4=1’b1
+		ampl_val=$(ssdk_sh debug phy get $phy_addr 0x40010067 | grep SSDK | grep -oE '0x[0-9a-fA-F]+' | sed 's/\(0x..\)./\11/')
+		ssdk_sh debug phy set $phy_addr 0x40010067 $ampl_val
+	fi
+}
+
+function ipq53xx_uniphy_amplitude_set () {
+        #UniPhy (5321->8081): Custom amplitude (bit[8:4]=21) = 0xb15d
+	#for ipq53xx sgmii, set half amplitude with tx_emp_lvl/margin_index and tx_margin
+	ssdk_sh debug uniphy set 1 0x7ac 0xb15d 4
+	ssdk_sh debug uniphy set 1 0x24 0 4
+}
+
+ssdk_dependency() {
+	counter=0
+	[ -e /lib/modules/$(uname -r)/qca-ssdk.ko ] && [ ! -d /sys/module/qca_ssdk ] && {
+		insmod qca-ssdk.ko
+	}
+	while [ ! -d /sys/ssdk ] && [ "$counter" -le 5 ]
+	do
+		sleep 1
+		counter=$((counter+1))
+	done
+}
+
+start() {
+	ssdk_dependency
+	chip_ver=`ssdk_sh debug reg get 0 4 | grep Data | tr -d 'SSDK Init OK![Data]:'`
+	#The following commands should be uncommented to enable EDMA WAR
+	if [ "$chip_ver" = "0x1401" ]; then
+		#edma_war_config_add
+		echo ''
+	fi
+	#The following commands should be uncommented to add acl egress stp bypass rules
+	if [ "$chip_ver" = "0x1500" ] || [ "$chip_ver" = "0x1501" ] || [ "$chip_ver" = "0x2000" ] || [ "$chip_ver" = "0x2001" ] || [ "$chip_ver" = "0x2100" ]; then
+		#create_acl_byp_egstp_rules $chip_ver
+		echo ''
+	fi
+	#The following commands should be uncommented to enable WAR for ipq50xx
+	chip_type_info=`cat tmp/sysinfo/model`
+	result=$(echo $chip_type_info | grep "IPQ5018")
+	if [ "$result" != "" ]; then
+		#ipq50xx_serdes_monitor &
+		#ipq50xx_uniphy_amplitude_set
+		#ipq50xx_phy_amplitude_set
+		echo ''
+	fi
+	if [ "$chip_ver" = "0x2001" ]; then
+		ipq53xx_uniphy_amplitude_set
+		ipq53xx_phy_amplitude_set
+		echo ''
+	fi
+	echo starting
+}
+
+stop() {
+	chip_ver=`ssdk_sh debug reg get 0 4 | grep Data | tr -d 'SSDK Init OK![Data]:'`
+	#The following commands should be uncommented to disable EDMA WAR
+	if [ "$chip_ver" = "0x1401" ]; then
+		#edma_war_config_del
+		echo ''
+	fi
+	#The following commands should be uncommented to delete acl egress stp bypass rules
+	if [ "$chip_ver" = "0x1500" ] || [ "$chip_ver" = "0x1501" ] || [ "$chip_ver" = "0x2000" ] || [ "$chip_ver" = "0x2001" ] || [ "$chip_ver" = "0x2100" ]; then
+		#delete_acl_byp_egstp_rules $chip_ver
+		echo ''
+	fi
+	echo stoping
+}

feeds/qca-wifi-7/qca-ssdk-qca/patches-zyxel_nwa50be/0001-pinctrl-make-the-switch-LED-works.patch

@@ -0,0 +1,47 @@
+From 7fa9e9b683f1c573c58a14755347988919bc7d06 Mon Sep 17 00:00:00 2001
+From: YenLin Pan <yenlin.pan@zyxel.com.tw>
+Date: Wed, 14 May 2025 13:47:06 +0800
+Subject: [PATCH] pinctrl: make the switch LED works
+
+Enable switch LED pin definition for LED0/LED1/LED2 control
+
+Signed-off-by: YenLin Pan <YenLin.Pan@zyxel.com.tw>
+---
+ src/init/ssdk_mht_pinctrl.c | 10 ++++++++--
+ 1 file changed, 8 insertions(+), 2 deletions(-)
+
+diff --git a/src/init/ssdk_mht_pinctrl.c b/src/init/ssdk_mht_pinctrl.c
+index 2debe59..1ae0002 100755
+--- a/src/init/ssdk_mht_pinctrl.c
++++ b/src/init/ssdk_mht_pinctrl.c
+@@ -33,11 +33,17 @@ static struct mht_pinctrl_setting mht_pin_settings[] = {
+     /*PINs default MUX Setting*/
+     MHT_PIN_SETTING_MUX(0,  MHT_PIN_FUNC_INTN_WOL),
+     MHT_PIN_SETTING_MUX(1,  MHT_PIN_FUNC_INTN),
+-#if 0
++#if 1
+     MHT_PIN_SETTING_MUX(2,  MHT_PIN_FUNC_P0_LED_0),
+     MHT_PIN_SETTING_MUX(3,  MHT_PIN_FUNC_P1_LED_0),
+     MHT_PIN_SETTING_MUX(4,  MHT_PIN_FUNC_P2_LED_0),
+     MHT_PIN_SETTING_MUX(5,  MHT_PIN_FUNC_P3_LED_0),
++    MHT_PIN_SETTING_MUX(6,  MHT_PIN_FUNC_P0_LED_2),
++    MHT_PIN_SETTING_MUX(7,  MHT_PIN_FUNC_P1_LED_2),
++    MHT_PIN_SETTING_MUX(8,  MHT_PIN_FUNC_P2_LED_2),
++    MHT_PIN_SETTING_MUX(9,  MHT_PIN_FUNC_P3_LED_2),
++#endif
++#if 0
+     MHT_PIN_SETTING_MUX(6,  MHT_PIN_FUNC_PPS_IN),
+     MHT_PIN_SETTING_MUX(7,  MHT_PIN_FUNC_TOD_IN),
+     MHT_PIN_SETTING_MUX(8,  MHT_PIN_FUNC_RTC_REFCLK_IN),
+@@ -49,7 +55,7 @@ static struct mht_pinctrl_setting mht_pin_settings[] = {
+     MHT_PIN_SETTING_MUX(13, MHT_PIN_FUNC_P0_TOD_OUT),
+     MHT_PIN_SETTING_MUX(14, MHT_PIN_FUNC_P0_CLK125_TDI),
+     MHT_PIN_SETTING_MUX(15, MHT_PIN_FUNC_P0_SYNC_CLKO_PTP),
+-#if 0
++#if 1
+     MHT_PIN_SETTING_MUX(16, MHT_PIN_FUNC_P0_LED_1),
+     MHT_PIN_SETTING_MUX(17, MHT_PIN_FUNC_P1_LED_1),
+     MHT_PIN_SETTING_MUX(18, MHT_PIN_FUNC_P2_LED_1),
+-- 
+2.34.1
+

profiles/zyxel_nwa50be.yml

@@ -0,0 +1,16 @@
+---
+profile: zyxel_nwa50be
+target: ipq53xx
+subtarget: generic
+description: Build image for the zyxel nwa50be
+image: bin/targets/ipq53xx/generic/openwrt-ipq53xx-zyxel_nwa50be-squashfs-sysupgrade.tar
+feeds:
+  - name: qca
+    path: ../../feeds/qca-wifi-7
+packages:
+  - ipq53xx
+  - qca-ssdk-shell
+include:
+  - ucentral-ap
+diffconfig: |
+  CONFIG_KERNEL_IPQ_MEM_PROFILE=0