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Author SHA1 Message Date
YenLin Pan
ef598c9b01 zyxel_nwa130be: fine tune thermal setting
Signed-off-by: YenLin Pan <YenLin.Pan@zyxel.com.tw>
2025-07-09 14:48:03 +08:00

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@@ -1,6 +1,6 @@
From 1a46aa106a50a06bfa4b669d87a8143c3d59f2f4 Mon Sep 17 00:00:00 2001
From f117d369cecadedefd2eb1467d52e9df76c14dc6 Mon Sep 17 00:00:00 2001
From: YenLin Pan <yenlin.pan@zyxel.com.tw>
Date: Wed, 14 May 2025 14:14:22 +0800
Date: Wed, 9 Jul 2025 14:46:13 +0800
Subject: [PATCH] thermal: thermal setting
lv0 -100 -hi0 105 -off0 0
@@ -10,11 +10,11 @@ lv3 105 -hi3 120 -off3 100
Signed-off-by: YenLin Pan <YenLin.Pan@zyxel.com.tw>
---
drivers/net/wireless/ath/ath12k/thermal.h | 16 ++++++++--------
1 file changed, 8 insertions(+), 8 deletions(-)
drivers/net/wireless/ath/ath12k/thermal.h | 24 +++++++++++------------
1 file changed, 12 insertions(+), 12 deletions(-)
diff --git a/drivers/net/wireless/ath/ath12k/thermal.h b/drivers/net/wireless/ath/ath12k/thermal.h
index 5c91906..a493cd5 100644
index 5c91906..dae4488 100644
--- a/drivers/net/wireless/ath/ath12k/thermal.h
+++ b/drivers/net/wireless/ath/ath12k/thermal.h
@@ -13,28 +13,28 @@
@@ -34,15 +34,19 @@ index 5c91906..a493cd5 100644
#define ATH12K_THERMAL_LVL0_V2_TEMP_LOW_MARK -100
-#define ATH12K_THERMAL_LVL0_V2_TEMP_HIGH_MARK 95
+#define ATH12K_THERMAL_LVL0_V2_TEMP_HIGH_MARK 105
#define ATH12K_THERMAL_LVL1_V2_TEMP_LOW_MARK 90
-#define ATH12K_THERMAL_LVL1_V2_TEMP_LOW_MARK 90
-#define ATH12K_THERMAL_LVL1_V2_TEMP_HIGH_MARK 100
+#define ATH12K_THERMAL_LVL1_V2_TEMP_HIGH_MARK 110
#define ATH12K_THERMAL_LVL2_V2_TEMP_LOW_MARK 95
#define ATH12K_THERMAL_LVL2_V2_TEMP_HIGH_MARK 105
#define ATH12K_THERMAL_LVL3_V2_TEMP_LOW_MARK 100
-#define ATH12K_THERMAL_LVL2_V2_TEMP_LOW_MARK 95
-#define ATH12K_THERMAL_LVL2_V2_TEMP_HIGH_MARK 105
-#define ATH12K_THERMAL_LVL3_V2_TEMP_LOW_MARK 100
-#define ATH12K_THERMAL_LVL3_V2_TEMP_HIGH_MARK 110
+#define ATH12K_THERMAL_LVL3_V2_TEMP_HIGH_MARK 115
+#define ATH12K_THERMAL_LVL0_V2_TEMP_HIGH_MARK 105
+#define ATH12K_THERMAL_LVL1_V2_TEMP_LOW_MARK 95
+#define ATH12K_THERMAL_LVL1_V2_TEMP_HIGH_MARK 110
+#define ATH12K_THERMAL_LVL2_V2_TEMP_LOW_MARK 100
+#define ATH12K_THERMAL_LVL2_V2_TEMP_HIGH_MARK 115
+#define ATH12K_THERMAL_LVL3_V2_TEMP_LOW_MARK 105
+#define ATH12K_THERMAL_LVL3_V2_TEMP_HIGH_MARK 120
#define ATH12K_THERMAL_LVL4_V2_TEMP_LOW_MARK 105
#define ATH12K_THERMAL_LVL4_V2_TEMP_HIGH_MARK 120