When the AP or EC is off, the RX line is low. Holding the UART RX line
low causes an interrupt storm. This change disables the UART TX and RX
on the peripheral when the device is powered off so the interrupts wont
be triggered.
BUG=chrome-os-partner:53514,b:28885578
BRANCH=none
TEST=run taskinfo on cr50 and make sure the IRQ count for 181 is a
reasonable number.
Change-Id: I42c779253860a2b1dd27ab41fb7097c887cc23ff
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/347355
Use the power and servo connection states to enable and disable the
EC and AP UART output. Contention between the cr50 and servo
can prevent either uart from working, and possibly damage kevin or
servo. If both UARTs are enabled, then cr50 cant know if servo is
connected, so it is best if the UARTs are disabled before connecting
servo.
If servo is connected or if a device is not powered on then the UART
output wont be enabled. The two UARTs are enabled separately and one can
be enabled without the other. Any disabled UART will be monitored for a
servo connection. If servo is detected, then all UARTs will be disabled.
BUG=chrome-os-partner:52056,chrome-os-partner:52322
BRANCH=none
TEST=manual
Power on the EC only. Check only the EC UART is enabled.
Without disabling the uarts power on the AP and verify both are
now enabled.
Turn of the AP. run 'uart enable. Verify only the EC UART is
enabled. Then attach servo and check that the AP and EC UART
are disabled.
Change-Id: Ife27c9360e91b07f86ff8bfcec7f4fd423c31d25
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/342828
There are a couple of issues that cr50 has when it cannot know the state
of servo, the EC, and the AP. This change adds support so we can detect
when the AP or EC has been powered on and when servo has been connected.
It uses the UART RX signals to monitor the power state of the AP and EC.
The TX signals are used to monitor the state of servo.
BUG=chrome-os-partner:52056,chrome-os-partner:52322
BRANCH=none
TEST=verify device states are correct when the AP and EC are powered on
or off and when Servo is attached or detached
Change-Id: Id0a2281b65cb367ecc8d0ca2f9a576672318a5fb
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/344019
Used #define CONFIG_FLASH_NVMEM to have functions in
/board/tpm2/NVMem.c utlitize on chip Nvmem functions.
On chip NV Memory availability is tied to an internal nvmem
error state which itself only depends on finding at least one
valid partition.
Added nvmem_is_different and nvmem_move functions which were
needed to complete the tpm2 platform interface. In addition,
added unit tests to support these two new functions.
BUG=chrome-os-partner:44745
BRANCH=none
TEST=manual
make runtests TEST_LIST_HOST=nvmem and verify that all tests pass.
Tested with tcg_test utility to test reads/writes using the
command "build/test-tpm2/install/bin/compliance --ntpm
localhost:9883 --select CPCTPM_TC2_3_33_07_01".
Change-Id: I475fdd1331e28ede00f9b674c7bee1536fa9ea48
Signed-off-by: Scott <scollyer@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/346236
Commit-Ready: Scott Collyer <scollyer@chromium.org>
Tested-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
Enabled CONFIG_FLASH_NVMEM and its associated configs. Added
user definitions along with buffer lengths. Added board
specific functions for sha computation and getting user
buffer lengths required by the NvMem module.
This CL does not include calls from cr50/board/tpm2/NVMem.c.
Those calls will be modified in a subsequent CL.
BUG=chrome-os-partner:44745
BRANCH=none
TEST=manual
The only call to any NvMem functions is nvmem_init().
Loaded code and verified via console that it boots
up properly. Also executed 'make runtests', but
that really only tests regression and not the new
board specific changes.
Change-Id: Iddc8d05703707247d26a8f22dca3ac9cc3c6ad1e
Signed-off-by: Scott <scollyer@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/345633
Commit-Ready: Scott Collyer <scollyer@chromium.org>
Tested-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
This change provides a console command for setting,
and loading a usb serial number from flash. This
feature adds CONFIG_USB_SERIALNO, and currently only
has a useful implementation when PSTATE is present.
BUG=chromium:571477
TEST=serialno set abcdef; serialno load; reboot
BRANCH=none
Change-Id: I3b24cfa2d52d54118bc3fd54b276e3d95412d245
Signed-off-by: Nick Sanders <nsanders@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/337359
Reviewed-by: Randall Spangler <rspangler@chromium.org>
The counter used for prime generation should be
incremented after each success / failure. Not doing
so results in duplicate primes being picked when
a label is explicitly specified.
BRANCH=none
BUG=chrome-os-partner:43025,chrome-os-partner:47524
TEST=all tests in test/tpm_test/tpmtest.py pass
Change-Id: Ib2fd0e7fa6255b04946e6d2808e8c67a2199fb55
Signed-off-by: nagendra modadugu <ngm@google.com>
Reviewed-on: https://chromium-review.googlesource.com/346056
Commit-Ready: Nagendra Modadugu <ngm@google.com>
Tested-by: Nagendra Modadugu <ngm@google.com>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
These must be initialized in order for charge_manager to select a port +
input current limit.
BUG=chrome-os-partner:53578
BRANCH=None
TEST=Attach 5V USB-C charger on Reef, verify "New chg" print is seen
along with "CL: p0 s1 i3000 v5000]" print.
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: Ia6139d9e9c6acd17ac587b32280f11927741672d
Reviewed-on: https://chromium-review.googlesource.com/347043
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: David Hendricks <dhendrix@chromium.org>
The gpio settings for the USB_PD_RST_ODL signal had the default
state high while the power enable, EN_USB_TCPC_PWR, was low. This
is combination of settings is invalid for the part. Therefore,
keep USB_PD_RST_ODL low until board_set_tcpc_power_mode() is called
to bring the pd chip online.
BUG=chrome-os-partner:53035
BRANCH=None
TEST=Rachel confirmed things still working.
Change-Id: I8b6b54a474c00165a4d0af944fb60f2923b9ef5c
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/347000
Reviewed-by: Shawn N <shawnn@chromium.org>
The USB_C0_PD_INT signal is actually at 3.3V levels. Don't mark
the voltage sensitivity to 1.8V.
BUG=chrome-os-partner:53035
BRANCH=None
TEST=Rachel ran with resulting image. Nothing bad observed.
Change-Id: I36bc3f911b715dc967cc8f23dfc70c3d0e5023d2
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/346734
Reviewed-by: Shawn N <shawnn@chromium.org>
board_reset_pd_mcu() was provided to ensure a microcontroller USB PD
implmenetation was reset. However, performing this sequence without
coordinating with the analogix driver results in a mismatch of
expectations regarding the internal polarity. The driver already
sets the expected interrupt polarity, but performing this reset
in chipset_pre_init() changes the expected setting which results
in occasional power sequence state machine hangs since
tcpc_get_alert_status() was always returning true. Lastly, added
comment to board_reset_pd_mcu() indicating how that sequence is likely
not needed if it's only invoked in the EC reset path.
Getting the analogix chip out of reset works in conjunction with the
default gpio settings for USB_PD_RST_ODL as well as the implementation
of board_set_tcpc_power_mode().
BUG=chrome-os-partner:53035
BRANCH=None
TEST=Rachel tested with change. Consistent power sequencing completes
without any hangs.
Change-Id: I9ffabaf85f33d6a361caef631e3e6d86c4cf8081
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/346733
Reviewed-by: Shawn N <shawnn@chromium.org>
updated the following based on amenia 1.2 hardware change:
gpio change
invert kbd col 2
g782 temp sensor
adc ch0, 2 reading
kx022 base accel
lid gyro/accel/mag i2c port change
bd99955 charger
bc1.2 support (CL:341030)
tcpc support (CL:341535)
BUG=none
BRANCH=none
TEST=make buildall
Change-Id: I178baf326c8edd8e0dadac6a6480625177d90a09
Signed-off-by: Kevin K Wong <kevin.k.wong@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/341534
Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
Enabled CONFIG_CMD_RTC_ALARM. EC_HOST_EVENT_RTC
is enabled when the rtc_alarm goes off,
alerting the AP to transition from S3->S0.
BUG=chrome-os-partner:52218
BRANCH=None
TEST=rtc_alarm <num> and see event set in ec console
after <num> seconds. Also, check if new bit set
through hostevent command in ec before/after
rtc_alarm goes off.
Change-Id: I53b1705ce0925000f35b9f80752035d198db3310
Signed-off-by: Shelley Chen <shchen@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/345474
Reviewed-by: Shawn N <shawnn@chromium.org>
This adds the basic framework for Reef including full GPIO listing,
board config file, and rudimentary functionality. It has not been
fully tested and still has several TODOs/FIXMEs. For now we just need
something that will build and can be incrementally improved.
BUG=chrome-os-partner:53035
BRANCH=none
TEST=EC and AP both boot, seems reasonably stable for now
Change-Id: I4934ad00917e251dd1d7eb759207a92c45a36136
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/339292
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
LPC access interrupt only enabled when EC entering deep doze mode. This
will reduce interrupt of LPC access. Also, this interrupt is always
enabled for LPC platform to support "CONFIG_LOW_POWER_S0".
Signed-off-by: Dino Li <dino.li@ite.com.tw>
BRANCH=none
BUG=none
TEST=Tested ectool command 'version' x 10000.
Change-Id: I9053c4018b38a8a852c3c6254e1fcde625f3fa3a
Reviewed-on: https://chromium-review.googlesource.com/336112
Commit-Ready: Dino Li <dino0303@gmail.com>
Tested-by: Dino Li <dino0303@gmail.com>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Update battery parameters to match the batteries actually present on
these devices.
BUG=chrome-os-partner:53002
BRANCH=None
TEST=Manual on kevin. Verify battery successfully charges and discharges
from AC.
Change-Id: I84579c23fe9fec1aecf133887a2d5b880047772f
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/344935
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
The EC code expects console commands to be no longer than 14
characters, otherwise the alignment of the help command output breaks.
This patch replaces flash_spi_sel_lock with flash_spi_lock and
fake_disconnect with fakedisconnect to make sure the command names
fit.
BRANCH=none
BUG=none
TEST=the 'help' command output is not misaligned any more
Change-Id: Ia65f1535850a07adccbef0812c8a0922c0264cea
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/345570
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Mulin Chao <mlchao@nuvoton.com>
Some axes of base and lid accelerometers on EVT needs to be reversed
to match the standard reference frame.
BUG=chrome-os-partner:52776
BRANCH=none
TEST=accelinfo on and check the lidangle reported is correct when I am
changing the lid angle
Change-Id: Id340d28a740d00c7ff4508f5f804fe90fd8ba18c
Signed-off-by: Koro Chen <koro.chen@mediatek.com>
Signed-off-by: Ricky Liang <jcliang@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/343490
coreboot will enable AP_OVERTEMP signal when AP
has surpassed a temperature threshold. These
changes has the EC do an apshutdown when it
detects this signal going high.
BUG=chrome-os-partner:51926
BRANCH=None
TEST=lower AP_OVERTEMP threshold and make sure
that AP shutdown occurs.
CQ-DEPEND=CL:342797
Change-Id: Ib9c9d03d2df0d670830c0b4eea3eea3ba5bae0b8
Signed-off-by: Shelley Chen <shchen@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/343060
Reviewed-by: Shawn N <shawnn@chromium.org>
Add generic PWM host commands for setting + getting duty cycle. PWMs can
be controlled through index (board-specific meaning) or by type
(currently KB backlight and display backlight are supported, more can be
added as needed).
BUG=chrome-os-partner:52002
BRANCH=None
TEST=Manual on chell.
`ectool pwmsetduty kb 100` - Verify KB backlight goes to 100%
`ectool pwmgetduty kb` - Prints 100
`ectool pwmgetduty 0` - Prints 100
`ectool pwmsetduty 0 0` - Verify KB backlight goes to 0%
`ectool pwmgetduty kb` - Prints 0
`ectool pwmgetduty disp` - Error res 3 (unsupported PWM type)
`ectool pwmsetduty 1` - Error res 3 (non-existent PWM index)
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: I607c92a291e6c2e3af8238eaf22ad2bb81ffc805
Reviewed-on: https://chromium-review.googlesource.com/344012
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
The tracing runs a higher priority task (SNIFFER) than the packet
injection (on CONSOLE task) and both RX and TX are using the same buffer,
so when we are sending a packet, we are getting immediately preempted by
the tracer and bad stuffs happen.
Now, we can manually inject packets and get the text trace of the
response.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=none
BUG=none
TEST=with the SOP' experimental patch, plug a full-featured cable into
Samus with Twinkie as an interposer, then do the following sequence:
Pretend there is a device
> tw resistor rd 0
Enable the text tracing
> tw trace on
Send discover identity to the cable (and get the descriptors)
> tw sendprime 1 0x104f ff008001
Sent CC1 104f + 1 = 381
165.939687 SRC/0 [0141]GOODCRC
165.942520 SRC/0 [514f]VDM Vff00:DISCID,ACK:ff008041 1c00050d 00000000 030a0000 11082032
Change-Id: Ie0ad57341c6476e983229b532716986dffefa8a1
Reviewed-on: https://chromium-review.googlesource.com/342512
Commit-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Benson Leung <bleung@chromium.org>
Kevin is code space constrained, so use RAM normally used for data
instead for code.
BUG=chrome-os-partner:52876
BRANCH=None
TEST=Verify free code RAM becomes 5732 bytes (was 1636) and free data
RAM becomes 3072 bytes (was 7168 bytes) (measured with pending changes
to add sensor task). Also, verify kevin continues to boot + power sequence.
Change-Id: Ia6470a76f95e87d6cda1bf7273deaab6344f8ee9
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/343191
Commit-Ready: Wonjoon Lee <woojoo.lee@samsung.com>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
Two permission registers are already lowered. This adds the
remaining two.
BUG=chrome-os-partner:52994
BRANCH=none
TEST=make buildall; run on Cr50
USB works, SPI works, sleep and deep sleep work, tpmtest.py works.
Change-Id: Ifb27d5be81f10537114f4702addb58c6d7e1630c
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/342455
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Using HOOK_PRIO_DEFAULT for peripheral initialization necessitates using
HOOK_PRIO_DEFAULT+1 for board-level code. Instead, use a
higher-than-default relative priority for peripheral initialization
outside of board.
BUG=None
TEST=Verify PWM and ADC are functional on kevin.
BRANCH=None
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: Ia8e90a7a866bdb0a661099dd458e3dfcaaa3f6bb
Reviewed-on: https://chromium-review.googlesource.com/342171
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
Use input signals to verify power state and determine power state after
sysjump.
BUG=chrome-os-partner:52878
BRANCH=None
TEST=Manual on kevin.
- Verify AP powers up on 'powerbtn'.
- AP shuts down on 'apshutdown'.
- AP re-powers / resets on 'powerbtn' + 'apreset'.
- AP doesn't shutdown on 'sysjump rw' while in S0.
Change-Id: Id24feb0f8490aa7cb73c46178085ff2e46f8d0a6
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/341704
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: David Schneider <dnschneid@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
BUG=chrome-os-partner:52576
BRANCH=none
TEST=make buildall; try on Cr50
I manually tested both highsec and highperf variants, as well as
forcing the bootrom init to run. All the bank registers were
loaded with meaningful values, and none of the SPI or USB
functionality showed any problems.
Change-Id: Ia91ba98ef4c667aec74195c4a7bbf72a5d1c8b2d
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/342030
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Remove buffer size checks in _cpri__GenerateKeyRSA().
The TPM stack passes in TPM2B buffers that
may have the size field uninitialized.
Callees are expected to assume that the
buffer size is sufficient for the requested
operation.
BRANCH=none
BUG=chrome-os-partner:43025,chrome-os-partner:47524
TEST=TCG test CPCTPM_TC2_2_20_03_02 reliably passes
Change-Id: I3d9bc2475b82dfaa9ed1d2617b1c333ff4df409d
Signed-off-by: nagendra modadugu <ngm@google.com>
Reviewed-on: https://chromium-review.googlesource.com/340883
Commit-Ready: Nagendra Modadugu <ngm@google.com>
Tested-by: Nagendra Modadugu <ngm@google.com>
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
When system on
.always blue
When system is off
.discharging : off
.charging : red
.full-charged : green
Error : red - green switching
BUG=None
TEST=See LED behavier on kevin
Change-Id: I93f0dbb503c68999825c455c8dc81b6bdaf397b4
Signed-off-by: Wonjoon Lee <woojoo.lee@samsung.com>
Reviewed-on: https://chromium-review.googlesource.com/341113
Reviewed-by: Shawn N <shawnn@chromium.org>
