Add usb_i2c_board_is_enabled().
On Cr50, this is now also connected to the I2C CCD capability. The
USB-I2C bridge can only be used when the capability is available.
On other platforms (Servo V4, etc.) where usb_i2c_board_enable() is
a no-op, add a dummy implementation which always returns true.
See go/cr50-ccd-wp for more information.
BUG=b:62537474
BRANCH=cr50
TEST=manual with CR50_DEV=1
Connect host PC to dev board USB port
On host PC:
sudo servod -c ccd_cr50.xml -c reef_r1_inas.xml
dut-control pp3300_ec_shv_reg --> fail, error 0x8001
ccdoops --> reset I2C config
ccd i2c disable --> I2C disabled
On host PC:
sudo servod -c ccd_cr50.xml -c reef_r1_inas.xml
dut-control pp3300_ec_shv_reg --> fail, error 0x0006
ccd i2c enable --> I2C enabled
ccdunlock --> I2C disabled
ccdoops --> I2C enabled
ccdset i2c unlesslocked
ccdlock --> I2C disabled
ccdunlock --> I2C enabled
Change-Id: Ia3df32e239a5f7c5915bc6c7e408ce0dc8b26c89
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/590577
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
In eSPI systems, when the Host performs a data read from the Shared
Memory space, the returned data may be corrupted. This is a result of
the Core-to-Host access enable bit being toggled (by toggling CSAE bit
in SIBCTRL register) during an eSPI transaction.
The workaround in this CL is to set CSAE bit to 1 during initialization
and remove the toggling of CSAE bit from other EC firmware code.
(i.e., let the CSAE bit be always 1.)
BRANCH=none
BUG=none
TEST=No build errors for make buildall. Flash poppy ec image, make sure
it can boot to OS. Run "ectool version" over 100000 times, no error
occurs.
Change-Id: I7aac6805ece64e8f77964d4acb026d9871cd2ebe
Signed-off-by: CHLin <CHLIN56@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/590396
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: CH Lin <chlin56@nuvoton.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
The primary purpose of the Pericom PI3USB9281 is for BC1.2 detection.
Therefore, move the driver to the bc12/ directory.
Additonally, rename the config option to match.
CONFIG_USB_SWITCH_PI3USB9281 => CONFIG_BC12_DETECT_PI3USB9281
BUG=None
BRANCH=None
TEST=`make -j buildall`
Change-Id: I02f17064c0625e62d6779f895e69899c24898f74
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/594710
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
The BQ24932 is a dual single-pole single-throw USB 2.0 high-speed
isolation switch with charger detection capabilities. The device's
charger detection circuitry can support USB Battery Charging
Specification version 1.2 (BC1.2), Apple, TomTom, and other non-standard
chargers.
BUG=None
BRANCH=None
TEST=`make -j buildall`
TEST=Enable support for the BQ24392 on a board. Verify that it
complies.
Change-Id: I82f426f1eedabdbb6b951a6ce0252135de3368db
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/592133
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Benson Leung <bleung@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
id only really needs 4 bits (16 touch events should be more than
enough), so we can steal 2 bits from that field.
We also reorder the fields to make sure that width/x are aligned
on 8-bit boundary.
BRANCH=none
BUG=b:63936194
TEST=Flash hammer, touchpad works, ABS_PRESSURE > 255 is reported
when a palm is pressed on the touchpad.
Change-Id: I1abf1bf53cc9dd998082cea5dc7cd3be17f99ec6
Reviewed-on: https://chromium-review.googlesource.com/583297
Commit-Ready: Nicolas Boichat <drinkcat@chromium.org>
Tested-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Chun-ta Lin <itspeter@chromium.org>
Reviewed-by: KT Liao <kt.liao@emc.com.tw>
This version will be bettter sutied for chip manufacturing environment
(no contention with the test rig GPIO settings and formal confirmation
of successful certificate installation).
BRANCH=cr50
BUG=b:63686091
TEST=none
Change-Id: I6d394493b824c9d79bca4785d3d44b33f322b899
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/583990
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
When in factory mode, we should not be trying to figure out board
strapping options, just enable SPI interface so that the tester can
communicate with the chip.
Also, to close the loop with the tester, let's add indication of the
cert installation result, by setting the two top bits of the DUMMY
(aka underrun) character to 1 and the lower bits to the endorsement
operation result (0 means success, nonzero values communicate
different failure modes) and by preventing the TPM driver from sending
anything but underrun chars on the SPI interface.
BRANCH=cr50
BUG=b:63686091
TEST=pending
Change-Id: I1a22ed6988ad87dd929a393359c4604e6ecd3b58
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/578651
Reviewed-by: Nick Sanders <nsanders@chromium.org>
When installed in the factory test rig, the DIOB4 pin is set to high
by the moment the RW section starts.
Software behavior needs to change to comply with the factory test rig
requirements. Define the GPIO and add a function to report the factory
mode state.
BRANCH=cr50
BUG=b:63686091
TEST=tested along with the rest of the stack of patches.
Change-Id: I8c4158fc75138d717fc009496365c8e61b42a890
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/579584
Reviewed-by: Nick Sanders <nsanders@chromium.org>
Because that's what it means. That is, it reports the state of
uartn_tx_connect(), not uartn_enable().
No functional changes; just a rename.
BUG=none
BRANCH=cr50
TEST=make buildall -j
Change-Id: Ie2273b277bd73a40307be7ec215417c1225cd567
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/590859
SPI access now depends on CCD_CAP_AP_FLASH and CCD_CAP_EC_FLASH.
usb_spi_state.enabled_host and .enabled_device are now bitfields which
depend on which SPI interface is enabled. This was implied before by
a single & comparing enabled_host to enabled_device, but is now
explicit so that the device can decide to enable just a subset of
buses.
BUG=b:62537474
BRANCH=cr50
BRANCH=cr50
TEST=manual with CR50_DEV=1
Connect host PC to dev board USB port
On host PC:
sudo servod -c ccd_cr50.xml -c reef_r1_inas.xml
In test protocol below, (test EC) means this command:
sudo flashrom -p raiden_debug_spi:target=EC --wp-status
And (test AP) means this command:
sudo flashrom -p raiden_debug_spi:target=AP --wp-status
"pass" means no console warning about "SPI access denied"
"fail" means console warnings about "SPI access denied"
To get even more confirmation, in chip/g/usb_spi.c temporarily
put this debug statement at the end of usb_spi_deferred():
CPRINTS("SPI res=%d", (int)res);
Pass is res=0, fail is res=5.
ccdoops
(test AP) --> pass
(test EC) --> pass
ccdunlock
(test AP) --> fail
(test EC) --> fail
ccdoops
ccdset flashap unlesslocked
ccdunlock
(test AP) --> pass
(test EC) --> fail
ccdoops
ccdset flashec unlesslocked
ccdunlock
(test AP) --> fail
(test EC) --> pass
Change-Id: I3d37d088b748832f164f2ca0ff29a93d6532ebed
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/590858
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Add support for OTP memory: if needed store serial number in first bank.
BUG=chromium:746471
BRANCH=none
TEST=On sweetberry, check we can write serial number with serialno
command. Check serial number survive a firmware update.
First, check without write protect, check we can write 0s (but not 1s)
serialno
Serial number: NNNNNNNNNNNNNNNNNNNNNN
>
> serial set MMMMMMMMMMMMMMMMMMMMMMMMMMMMM
Saving serial number
Serial number: LLLLLLLLLLLLLLLLLLLLLL
After lock enabled, check we can not overwrite.
> serial set AMMMMMMMMMMMMMMMMMMMMMMMMMMMM
Saving serial number
Serial number: LLLLLLLLLLLLLLLLLLLLLL
Access Denied
Check that serialno returns "Uninitialized" if it was never set.
Change-Id: I9ab08486a7c3e1958e964649640d69b5b70947e3
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/580290
Reviewed-by: Nick Sanders <nsanders@chromium.org>
One Time Programmable memory can be used to store permanent data like
serial numbers.
Reorganize the code to support writing serial number to OTP, in
addition to pstate (if using its own memory bank) or autogenerate from
unique id (hammer).
+ Add CONFIG_OTP to enable OTP code
+ Add CONFIG_SERIALNO_LEN to indicate the size of the serial number
string. Currently set to 28, when USB serial number is needed.
+ Expose flash_read|write_pstate_serial and add otp_read|write_serail,
remove more generic flash_read|write_serial.
+ Make board_read|write_serial generic, declared outside of USB subsystem.
Priority order to read|write serial string:
- board definition (like hammer)
- pstate location, if stored in its private memory bank
- otp area
If none of these methods are available, a compilation error is raised.
BUG=chromium:746471
BRANCH=none
TEST=compile
Change-Id: I3d16125a6c0f424fb30e38123e63cf074b3cb2d3
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/580289
Reviewed-by: Nick Sanders <nsanders@chromium.org>
board.h and config-chip.h should only be called from config.h, otherwise
some #define may not be set properly.
BUG=chromium:746471
BRANCH=none
TEST=Found a bug while compiling OTP changes (c/580289/)
(https://luci-milo.appspot.com/buildbot/chromiumos.tryserver/
no_vmtest_pre_cq/81548)
The size of the serial number string is set in config.h when
CONFIG_USB_SERIALNO is needed.
Compile with ec-utils with cr50_onboard USE flag set.
Change-Id: I5a2306bd0dc1dea29265226f2986829b768cfb61
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/581887
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
For boards with POWER_SEQUENCING_VERSION = 2 (and likely future
versions), allow the host to request "wakeable suspend", which will
leave rails enabled to allow wake-on-usb.
BUG=b:63037490
BRANCH=kevin
TEST=With subsequent commit, compile on scarlet w/ power sequencing
version = 2.
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: Iaadd371b1d1509d185c8c8306b72760dcfe9989f
Reviewed-on: https://chromium-review.googlesource.com/572211
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Philip Chen <philipchen@chromium.org>
Allow host to request a higher-power S3 variant, "wakeable S3", in which
more wakeup sources will be enabled by the EC. The actual implementation
and list of wake sources is left up to the chipset power driver and/or
board code.
BUG=b:63037490
BRANCH=gru
TEST=With subsequent commit, compile on scarlet w/ power sequencing
version = 2.
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: I469f0cd969052f173cb176196bb6d05f6f76fdb5
Reviewed-on: https://chromium-review.googlesource.com/572210
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Philip Chen <philipchen@chromium.org>
LTE_GPS_OFF_L and LTE_BODY_SAR_L are both currently configured as
push-pull output, but they should be OD. Let's also set the default
value to high.
BRANCH=none
BUG=b:64126879
TEST=Flash poppy.
Change-Id: I2e9297c567e74f7d2656557c306337e90a4410c1
Signed-off-by: Nicolas Boichat <drinkcat@google.com>
Reviewed-on: https://chromium-review.googlesource.com/590908
Commit-Ready: Nicolas Boichat <drinkcat@chromium.org>
Tested-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Turns out PCH_RTCRST is never used, and its location is either
GPIOE7 (rev 0-3), or GPIO27 (rev 4-).
- Leaving this pin configured as input (default) for rev0-3 should
be fine as there is an external pull-down.
- We still drive it low from rev4, for consistency.
Also, LED_YELLOW_C0 only moved from GPIO32 to GPIO24 (not GPIO27)
from rev5.
BRANCH=none
BUG=b:63048710
TEST=Boot poppy/soraka
Change-Id: I1c474fe8abb97c75210b81662ba1d1af0a7ee82e
Signed-off-by: Nicolas Boichat <drinkcat@google.com>
Reviewed-on: https://chromium-review.googlesource.com/588428
Commit-Ready: Nicolas Boichat <drinkcat@chromium.org>
Tested-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
gpio_interrupt_type_sel() is guaranteed to be called with at least one
GPIO_INT_ANY bit set, but our new toolchain doesn't seem to realize it.
BUG=chromium:747553
BRANCH=None
TEST=`make BOARD=gru -j` with next_gcc, also verify kevin boots to OS.
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: Ice2a9963983dca2ee9c0c543bf55c27753c42933
Reviewed-on: https://chromium-review.googlesource.com/584820
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
The sysrst and ecrst commands are now protected by the RebootECAP
capability. They can print the state of the reset lines when the
capability is not allowed, but can only change the state or pulse the
reset lines when the capability is allowed.
See go/cr50-ccd-wp for more information.
BUG=b:62537474
BRANCH=cr50
TEST=manual with CR50_DEV=1 build:
ccdoops --> reset CCD config and go to Opened state
ecrst pulse --> works
sysrst pulse --> works
ccdunlock
ecrst pulse --> access denied
sysrst pulse --> access denied
ecrst --> prints state
sysrst --> prints state
ccdoops
ccdset rebootecap unlesslocked
ccdunlock
ecrst pulse --> works
sysrst pulse --> works
Change-Id: Ia9ebe67bdc1e85129051caf94f20fb2fb84b76da
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/590071
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
The WP command is now controlled by CCD configuration (ccdset
wpoverride). In addition to enabling/disabling/following battery for
the current boot (counting deep sleep resume), it is also possible to
set the WP override at boot. That's needed to support persistently
disabling WP for RMA without needing to persistently remove the
battery.
Restricted console commands are now controlled by CCD configuration
(ccdset cr50fullconsole).
The old 'lock' console command has been removed, now that
ccdopen/ccdunlock/ccdlock replace it.
The old TPM vendor commands for set_lock is gone; it will be replaced
by CCD configuration TPM vendor commands in a subsequent CL. The
get_lock command still exists, but only reports the console lock
state; it will be removed too.
See go/cr50-ccd-wp for more information.
BUG=b:62537474
BRANCH=cr50
TEST=manual with CR50_DEV=1 build
ccdinfo --> State = Opened, WPOverride = default(IfOpened)
plug in battery (or jumper DIOM2 to ground on a dev board)
gpioget --> make sure GPIO_BATT_PRES_L=0
wp --> enabled, at boot follow battery
remove battery (or jumper DIOM2 to JTAG pin3 on a dev board)
gpioget --> make sure GPIO_BATT_PRES_L=1
wp --> disabled, at boot follow battery
wp enable --> forced enabled, at boot follow battery
idle d
(wait for restart)
wp --> forced enabled, at boot follow battery
reboot
wp --> disabled, at boot follow battery
plug in battery (or jumper DIOM2 to ground on a dev board)
wp --> enabled, at boot follow battery
wp disable --> forced disabled, at boot follow battery
idle d
(wait for restart)
wp --> forced disabled, at boot follow battery
reboot
wp --> enabled, at boot follow battery
wp disable atboot --> forced disabled, at boot forced disabled
reboot
wp --> forced disabled, at boot forced disabled
wp enable --> forced enabled, at boot forced disabled
idle d
(wait for restart)
wp --> forced enabled, at boot forced disabled
wp follow_batt_pres --> enabled, at boot forced disabled
wp follow_batt_pres atboot --> enabled, at boot follow battery
ccdunlock
wp disable --> access denied
help --> commands like 'crash' are disabled
ccdoops
ccdset cr50fullconsole unlesslocked
ccdset wpoverride always
ccdunlock
help --> commands like 'crash' are still enabled
ccdlock
help --> commands like 'crash' are disabled
wp disable --> forced disabled
ccdoops
Change-Id: Ic441f490bdd7a19dd646fe8338e5d608b42ce72c
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/575997
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
If there is a board ID mismatch and rollback is not possible Cr50
firmware will enter a limited mode which only support Cr50 firmware
upgrade. All other features must be disabled, because it is not
possible to know which features should be allowed on the mismatched
board.
See go/cr50-ccd-wp for more information.
BUG=b:62537474
BRANCH=cr50
TEST=manual with CR50_DEV=1 build, define CONFIG_CMD_CCDDISABLE
ccdinfo --> state=opened
ccddisable --> state=locked(disabled), all capabilities disabled
ccdunlock --> access denied
ccdopen --> access denied
ccdreset --> access denied
ccdpassword --> access denied
ccdset --> access denied
ccdoops
ccdinfo --> state=opened, back to defaults
Change-Id: Idb66fb1f3d5106aa0c2cb6addf2404ea9942b0d6
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/590070
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
Define two bits in a long-life register to hold the current CCD state
across deep sleep. Update the bits on CCD config change, and restore
them on init.
This is necessary because Cr50 loses RAM contents on deep sleep. It
would be really inconvenient to open CCD, get a cup of coffee, and
come back to find CCD has locked again because Cr50 was idle too long.
See go/cr50-ccd-wp for more information.
BUG=b:62537474
BRANCH=cr50
TEST=manual with CR50_DEV=1 build
ccdinfo --> state=opened
idle d
ccdunlock
ccdinfo --> state=unlocked
(wait for deep sleep)
sysinfo --> reset flags = hibernate wake-pin
ccdinfo --> state=unlocked
reboot
sysinfo --> reset flags = hard
ccdinfo --> state=opened
Change-Id: I7864f374af5c159bc9691b094958fb030f3cb8ad
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/575996
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
BUG=chromium:736603
BRANCH=none
TEST=Follow the steps below
1) add MAX17055 config to Scarlet and build the code
2) hook up max17055 eval board and a single cell battery
3) battery command from ec console shows reasonable numbers
for temperature, voltage, and charge percentage
Change-Id: I3f838ff92c591665e9f1d0a7ba636ff83d9b7612
Signed-off-by: Philip Chen <philipchen@google.com>
Reviewed-on: https://chromium-review.googlesource.com/578300
Commit-Ready: Philip Chen <philipchen@chromium.org>
Tested-by: Philip Chen <philipchen@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
Some chips require special operations before flash can be accessed
(read, write, erase), without it the flash operations could be
corrupted. The chip that requires this should enable the
CONFIG_FLASH_SELECT_REQUIRED config, which exposes
EC_FLASH_INFO_SELECT_REQUIRED in flashinfo flags. Before any flash
operations is executed on the chip, EC_CMD_FLASH_SELECT should be issued
to notify the chip to prepare for the flash operations.
BRANCH=none
BUG=b:63685022
TEST=with depended CLs, touchpad interrupt should be disabled when
flashrom is in progress.
CQ-DEPEND=CL:*416548
Change-Id: I96455adbe739d5f924edf382a2752404a7c5ad04
Signed-off-by: Wei-Ning Huang <wnhuang@google.com>
Reviewed-on: https://chromium-review.googlesource.com/582374
Commit-Ready: Wei-Ning Huang <wnhuang@chromium.org>
Tested-by: Wei-Ning Huang <wnhuang@chromium.org>
Reviewed-by: Wei-Ning Huang <wnhuang@chromium.org>
This will officially kill the support for rev0 boards.
The major changes include:
1) Massive GPIO rename/reallocation
2) New power sequencing
3) Reconfigure peripherals (e.g. I2C, SPI, ADC)
4) Drop usb_charger_task
5) Remove lid switch
6) Display BL not driven by PWM
7) Move bmp280 from I2C to SPI
8) Remove SPI flash
9) Some placeholders for follow-up changes.
BUG=b:62640322, b:62269890
BRANCH=none
TEST=build scarlet
Change-Id: Idc0a854a0935089295b67da106ba1b35359f146d
Signed-off-by: Philip Chen <philipchen@google.com>
Reviewed-on: https://chromium-review.googlesource.com/572684
Commit-Ready: Philip Chen <philipchen@chromium.org>
Tested-by: Philip Chen <philipchen@chromium.org>
Reviewed-by: David Schneider <dnschneid@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
100us is hard to measure reliably on poppy side, let's increase to
500us, and widen the range.
BRANCH=none
BUG=b:63818321
TEST=Flash staff and soraka EC, check that pulses are detected
correctly.
Change-Id: I1c29a42c70da0efa0318a619bb83e451b9f168f4
Reviewed-on: https://chromium-review.googlesource.com/581572
Commit-Ready: Nicolas Boichat <drinkcat@chromium.org>
Tested-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
The EC cannot control warm vs cold reset of the chipset using the
SYS_RST_L pin; it's just a reset request. This commit changes the
behaviour of chipset_reset to assert SYS_RST_L regardless if a cold or a
warm reset is requested.
BUG=b:63508740
BRANCH=None
TEST=make -j buildall; Flash a modified image on npcx7_evb, verify that
no panics or asserts are hit.
Change-Id: Idfd6f556bf909c7df4e8bd50a79b60719478cde7
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/585573
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
If we have no ISR for an enabled GPIO interrupt (eg. for a UART GPIO
interrupt that wakes from low-power idle) then clear it, to avoid
interrupt storm.
BUG=b:63958831
BRANCH=eve
TEST=Verify we can repeatedly wake from low-power idle on eve by hitting
'enter' on the EC console.
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: I6a01cae33e3bf1a3b5b42c0389c4613dc1cb9b7d
Reviewed-on: https://chromium-review.googlesource.com/584011
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Duncan Laurie <dlaurie@google.com>
Reviewed-by: Mulin Chao <mlchao@nuvoton.com>
This commit adds the GPIOs for determining the GPIOs.
Additionally, this adds some alternate functions for the PWM and ADC
pins.
BUG=b:63508740
BRANCH=None
TEST=Flash modified version on EVB and verify that it boots without any
panics or assertions.
Change-Id: I34161ad075ad88f940a21c2ee94219ea6a878d63
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/584052
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
Currently sweetberry hits an integer truncation issue
at 2.4 ohm when uA per div goes below 1. We can use 100ths
of a uA as the current per div scale.
BRANCH=None
BUG=chromium:608039
TEST=log from sweetberry with 10 ohm config.
Signed-off-by: Nick Sanders <nsanders@chromium.org>
Change-Id: I9e9216230329483fd0bfcb44ce23cd15bae864b3
Reviewed-on: https://chromium-review.googlesource.com/577051
Commit-Ready: Nick Sanders <nsanders@chromium.org>
Tested-by: Nick Sanders <nsanders@chromium.org>
Reviewed-by: Nick Sanders <nsanders@chromium.org>
In the recent change to flash_ec, there was a problem with they way that
common_stm32_VARS was defined. This commit fixes the issue.
BUG=chromium:740026
BRANCH=potentially some FW branches.
TEST=Using servo_v2, flash elm.
Change-Id: I2e14f1f45525f494d9912b420d36d02d89b9dc5a
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/583540
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
EC currently uses a host command from kernel to enter s0ix.
This patch waits for the SLP_S0 interrupt to come after receiving
the host command before entering S0ix.
On the exit path, the SLP_S0 interrupt directly triggers the
exit rather than waiting for the host command.
BRANCH=none
BUG=b:37443151
TEST=check in EC logs for SLP_S0 entry and powerindebug output,
check suspend_stress_test on reef and soraka works fine,
make -j8 buildall runs fine
Change-Id: Ie5507b7a1e723532f07bc0671c2abd364f6224a2
Signed-off-by: Subramony Sesha <subramony.sesha@intel.com>
Signed-off-by: Archana Patni <archana.patni@intel.com>
Signed-off-by: Jenny TC <jenny.tc@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/513705
Commit-Ready: Jenny Tc <jenny.tc@intel.com>
Tested-by: Jenny Tc <jenny.tc@intel.com>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
1) Don't assert prochot by default, this signal has an inverter
and driving it high is asserting prochot until it gets deasserted
during S3->S0 transition.
2) Clear PMIC power source interrupts in pmic_init in case they
were inadvertently set by misbehaving PMIC. The BATTSHORT event
that matters for PROCHOT assertion is masked so it should never
be set anyway, but I found a system where it was set. This register
does not seem to get cleared by an LDO reset so PROCHOT was stuck on
until battery cutoff.
BUG=b:63913242
BRANCH=eve
TEST=manual testing on Eve unit
Change-Id: I5c7f7ca528160972f65bd714deea98357fa43a53
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://chromium-review.googlesource.com/579904
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
The original _CHIPNAME for npcx ec in the openocd configuration file
is npcx5m5g. As we introduce more npcx ec SKUs, it is not appropriate
to keep using this name. This CL modifies the _CHIPNAME to a generic
name(npcx_ec).
BRANCH=none
BUG=none
TEST=./util/flash_ec --board=npcx7_evb; check the openocd log and make
sure the _CHIPNAME is npcx_ec now.
Signed-off-by: CHLin <CHLIN56@nuvoton.com>
Change-Id: I49d298de1e43ac29f3e5535702595ee27225ac23
Signed-off-by: CHLin <CHLIN56@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/576604
Commit-Ready: Jun Lin <riverq@gmail.com>
Tested-by: Jun Lin <riverq@gmail.com>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Support a level shifter for both 1.8v and 3.3v
uarts on SBU.
BRANCH=None
BUG=b:35849284
TEST=ran on tigertail, both 1.8v and 3.3v detected.
Change-Id: I76d545b582c6ed15086941513d5de4cd6783ac16
Signed-off-by: Nick Sanders <nsanders@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/575595
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
