Just a clean up patch attempting to make it easier to new users to
come up to speed with cr50 use of H1 GPIO subsystem.
BRANCH=none
BUG=none
TEST=none
Change-Id: I539e7629ee94ddef26ae1616dc6eb5c151e9d97e
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/412412
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
From the USBC spec 1.2 "Table 4-14 Precedence of power source usage"
USB Type-C 3.0 A & 1.5 A takes precedence over BC1.2 hence updated
the power supplier priority of charger manager.
BUG=chrome-os-partner:61420
BRANCH=none
TEST=Manually tested on reef. Donette bottom port can switch
from 1.5A to 3A upon high load.
Change-Id: Iff936d6a8643e88e0b2738251254e896fe8562fe
Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/430153
Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Benson Leung <bleung@chromium.org>
In rare case, if a bus error indicates a conflict on the data
line (SDA) is detected during transmission of the byte. (i.e.,
SDA is toggling during holding data period.) and SDAST are
set at the same time, the i2c driver is not good enough to handle
it. Ec will get stuck in i2c ISR forever since SDAST util
watchdog reset occurs.
This CL includes:
1. Do a dummy read to make sure i2c slave doesn't hold i2c bus.
It makes sure i2c master can generate STOP successfully.
2. Disable smb's interrupts in "A Bus Error has been identified".
Once bus error occurred, it's better to forbid ec to enter
ISR again. Let i2c_recovery() disable the module and reset
hardware state machine to the default.
BRANCH=none
BUG=chrome-os-partner:59294
TEST=test i2c console commands on wheatley for hours.
Change-Id: Iecadcd866e115e31b18dfd68359a018867cac40e
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/428482
Reviewed-by: Shawn N <shawnn@chromium.org>
The magnetometer online calibration requires these two
functions and taken from newlib.
Signed-off-by: Dino Li <dino.li@ite.com.tw>
BRANCH=none
BUG=none
TEST=fabsf():
fabsf(1.23) = 1.23
fabsf(-1.23) = 1.23
sqrtf():
sqrtf(4.56) = 2.135
sqrtf(0.123) = 0.350
sqrtf(-0.123) = an exception is triggered.
Change-Id: I808ca7f1bd03c6d6c1b32861ede4ecbfeeaa3da6
Reviewed-on: https://chromium-review.googlesource.com/429730
Commit-Ready: Dino Li <Dino.Li@ite.com.tw>
Tested-by: Dino Li <Dino.Li@ite.com.tw>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
DCRYPTO_HMAC_SHA256_init makes two calls to DCRYPTO_SHA256_init()
without an intervening HASH_final() call. This is incorrect usage
of the the hashing API, and results in the hardware SHA engine
getting locked for the life-time of the process (and resulting
in all future hash calls falling back to the software implementation).
This bug manifested itself when introducing NVRAM encryption, which
requires the hardware SHA engine to be available for key generation.
BRANCH=none
BUG=chrome-os-partner:55331
TEST=TCG tests pass
Change-Id: Ia4ccb6a6d64636c4618ef775291442975f3f1f92
Signed-off-by: nagendra modadugu <ngm@google.com>
Reviewed-on: https://chromium-review.googlesource.com/430154
Commit-Ready: Nagendra Modadugu <ngm@google.com>
Tested-by: Nagendra Modadugu <ngm@google.com>
Reviewed-by: Marius Schilder <mschilder@chromium.org>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
- revert the change for issue 61431 as main build systems have
updated resistor values
- enable CONFIG_CHARGER_BD9995X_CHGEN, with the necessary changes
in battery.c to support the custom battery present functions
- enable CONFIG_CHARGER_MAINTAIN_VBAT
- enable CONFIG_CHARGE_MANAGER_EXTERNAL_POWER_LIMIT for testing
- set pre-charge current to 256mA to better wake up batteries
- set voltage-min to 6.1V to account for charger inaccuracies since
the battery expects >= 6V to wake up
- enable CONFIG_BACKLIGHT_LID to enforce backlight off with lid closed
- put all CONFIG_CMD enables in the same place
- make PCH_ACOK open drain (pull-up to be enabled on PCH)
BUG=chrome-os-partner:61431,chrome-os-partner:61676
BRANCH=none
TEST=manual testing on P1 boards at the factory
Change-Id: Ib20693c8200d253819873d03b54f91e12bda8270
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://chromium-review.googlesource.com/428902
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
When debug enabled cr50 image is signed, the default manifest passed
to the signer is util/signer/ec_RW-manifest-dev.json. Images signed
with this manifest will not run on devices where the RO part is fused
for production.
It is possible to build node locked images for such devices, but the
manifest must include the lines
"DEV_ID0": <value>.
"DEV_ID1": <value>,
with the values matching the chip the image is built for.
This patch allows to pass the values in the make command line or the
environment, defined as follows:
H1_DEVIDS='<num 1> <num 2>'
When this value is defined, the default manifest is edited to add the
required lines.
One side effect of this patch is that the temp file where the edited
manifest is placed to is not deleted.
BRANCH=none
BUG=none
TEST=verified that images still can be built for both dev RW and prod
RO (node locked) with both debug features enabled and disabled
(CR50_DEV set and not set)
Change-Id: I0e81fc9aa65aa4d239e60de6047e2470f6eeaf50
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/428337
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Enable reading temperature from BMI160.
BUG=chrome-os-partner:58894
BRANCH=master
TEST=EC Console:
> temps
Battery : Error 1
Ambient : 304 K = 31 C
Charger : 303 K = 30 C
DRAM : 305 K = 32 C
eMMC : 307 K = 34 C
Gyro : 308 K = 35 C
Unknown error
TEST=AP Console:
localhost ~ # ectool tempsinfo 5
Sensor name: Gyro
Sensor type: 1
localhost ~ # ectool temps 5
Reading temperature...308
Change-Id: I2e943ec664745fec5923df67515b96ba569e05ad
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Signed-off-by: Alexandru M Stan <amstan@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/430210
Commit-Ready: Alexandru Stan <amstan@chromium.org>
Tested-by: Alexandru Stan <amstan@chromium.org>
This function belongs in dcrypto as it relies heavily on the crypto
hardware; also, it will be handy to be able to use this function in
other cases.
BRANCH=none
BUG=chrome-os-partner:55331
TEST=buildall still builds. TPM manufacturing still works too.
Change-Id: If2e70eaa71a76e8374b98f4667cb54ea6253b760
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/428169
Reviewed-by: Marius Schilder <mschilder@chromium.org>
This patch mostly is rearranging the code to make it easier to add
encryption layer in the upcoming change.
One substantial change is making sure that in case when NVMEM contents
are corrupted for whatever reason, the initialization function
re-creates a blank NVMEM space; it was just bailing out before not
leaving any initialized partitions behind.
There is no need in two separate tables - one for base absolute
addresses of the NVMEM partitions, and one for their flash memory
offsets, one can be easily derived from the other.
Code erasing the destination partition, calculating the SHA1 of the
new blob and writing it into the flash was separated into own
function.
BRANCH=none
BUG=chrome-os-partner:55331
TEST=make buildall -j still passes (which means NVMEM tests succeed).
TPM TCG test suite also passes.
Change-Id: I378265d8b49b81398aece2eadf9698abb05caaa1
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/428172
Reviewed-by: Scott Collyer <scollyer@chromium.org>
Boards that have plt_rst_l had sys_rst_l currently use the two signals
to detect resets and reset the TPM. That meant that the TPM could reset
twice depending on the timing of those signals. On boards with
plt_rst_l, we should really just use that to detect system resets and
not sys_rst_l. On boards with plt_rst_l, sys_rst_l should only be used
as an output to trigger warm resets.
This change makes both boards use the gpio tpm_rst_l_in to detect AP
resets. That gpio will be connected to a different pin depending on
which board we are using. On Gru the gpio will be connected to diom0
which is sys_rst_l, and reef will use diom3 which is plt_rst_l.
BUG=chrome-os-partner:61789
BRANCH=none
TEST=manual
Use cr50 servo to verify the contents of /var/cache survive
reset after 'dut-control warm_reset:on sleep:0.5000
warm_reset:off'
test on gru and reef
verify that the system can boot to kernel
run 'sysrst pulse' and check that you only see one system reset
use 'pinmux' to verify the pins for the two types of boards are
setup properly
on reef diom0 is an input, diom3 is an input with wake_falling,
and gpio1_gpio1 uses diom3
on gru check that diom0 is an input with wake_falling, diom3 is
not configured, and gpio1_gpio1 uses diom0
Change-Id: I1f6e8bfa525ffa5585a18282b78014f36f0cfee6
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/428130
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Backdrop:
Touchpad power source disabling should be constrained in tablet mode
and S0->S3 transition only, in case that disable it in the S0 state
of tablet mode, it would cause disaster while touchpad driver of AP
tries to perform suspend procedure.
Solution: follow CL:421275
This change takes away control of trackpad from EC entirely. This will
prevent EC from interfering with the OS's interaction with the trackpad
for firmware update, device detection at boot, or entering S3.
Disadvantages are the trackpad will stay on (thus can wake up the system
unintentionally) when the system enters S3 in laptop mode then
transitions to tablet mode, or vice versa: the trackpad will stay off
(thus cannot wake up the system) when the system enters S3 in tablet mode
then transitions to laptop mode.
However, these corner cases can be handled by waking up the system upon
mode transition. The OS can then disable or enable the trackpad depending
on the transition direction (laptop <-> tablet) and re-enters S3. Or the
OS can leave the system running because mode transition implies a user's
intention to start interacting with the device.
The keyboard will continue to be managed by EC and disabled or enabled
upon mode transition.
BUG=chrome-os-partner:61058, chrome-os-partner:61618,
chrome-os-partner:61636, chrome-os-partner:61506
BRANCH=reef
TEST=suspend device in tablet mode then wake it up,
examine touchpad function; hint: root shell to execute command
'ectool gpioget EN_P3300_TRACKPAD_ODL' to examine trackpad power
integrity.
Change-Id: I0c0b9deffe83aef012f685618b3cbc5dd5303c3a
Signed-off-by: Harry Pan <harry.pan@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/428791
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Benson Leung <bleung@chromium.org>
Updating variable name from smi_enabled to
power_button_pulse_enabled, which is a more accurate
description of the intended functionality.
BUG=chrome-os-partner:61275
BRANCH=None
TEST=reboot reef and try using power button for selection
during the detachable menus and ensure that the
DUT doesn't turn off.
Change-Id: Ia04e032818c73439d2aeacdb8fcabbe3bce7c151
Signed-off-by: Shelley Chen <shchen@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/429070
Reviewed-by: Duncan Laurie <dlaurie@google.com>
Increase the sysrst pulse to be long enough to reset the AP. This change
increases it to 20ms by default, but adds a parameter to set the
interval in the sysrst pulse command.
BUG=none
BRANCH=none
TEST='sysrst pulse' will cause the AP to reset and 'sysrst pulse 1000'
shows that sys_rst_l is asserted and 1 second later it is deasserted.
Change-Id: I66b0d627480852dc166f62dc0fddd02f094b6162
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/429150
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
VDO_CMD_GET_LOG is sent for each port from a host command handler, so we
must ensure that it returns quickly to prevent host timeout.
BUG=chrome-os-partner:61910
BRANCH=gru
TEST=Manual on kevin, attach hoho and verify 'cros-ec-spi' timeout
errors are not seen every 60s. Also verify that zinger pdlogs are
correctly retrieved.
Change-Id: Ie0466a8b614ec6bfe5874cde9d700e80a15d298e
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/428164
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Todd Broch <tbroch@chromium.org>
We get a lot of these errors when running the EC Makefile from an ebuild.
They are not useful since of course there is no git repo when the source
code is built from a copy. An empty date (as produced in this case) is
presumably good enough.
Suppress these errors by redirecting stderr.
BUG=chromium:680243
BRANCH=none
TEST=V=0 emerge-reef chromeos-ec; See that the git output is gone
Change-Id: Ia3d1e2046c87e0ca88d0c18e432467f9d23b7e9f
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/428156
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Relying on the AP sending a PCR read as an indication of the completed
boot process does not work on the resume path. Let's just enable
commits 3 s after they were stopped to process tpm reset.
BRANCH=none
BUG=chrome-os-partner:61795
TEST=observed the following on the cr50 console on a reef during reboot:
[0.018692 tpm_init]
tpm_manufactured: manufactured
[0.021180 tpm_reset_now: done]
.
.
[1.166496 Skipping commit]
[1.425888 Skipping commit]
[1.439112 Skipping commit]
.
.
[3.021892 Committing NVMEM changes.]
and verified that reef booted normally.
Change-Id: I5f64fe24b961a9d0366f8e4f40a0e44d4e7263fa
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/427328
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
These pins should be moved to AP in a later HW revision, keep them
always active for now. Also, leave CAM_PMIC_RST_L as input as
there is an internal pull-up in the PMIC, and driving it high
breaks WLAN+LTE.
BRANCH=none
BUG=chrome-os-partner:61098
TEST=ectool gpioget: Both signals are high
Change-Id: I66115daec57ca4d89c1c664e6b35825b20fa0c1a
Reviewed-on: https://chromium-review.googlesource.com/427743
Commit-Ready: Nicolas Boichat <drinkcat@chromium.org>
Tested-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Specifically, we are using a bit to disable the
SMI pulse on x86 systems so that we can use the
power button for menu selection.
BUG=chrome-os-partner:61275
BRANCH=None
TEST=Try running with depthcharge sending the host command
during detachable FW menus and making sure power
button select doesn't turn off device on reef.
Change-Id: I4a68cf514d514a4abe98beb99e7934d6fb0f44bd
Signed-off-by: Shelley Chen <shchen@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/427413
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
When the EC does a sysjump it redoes the PD negotiation. This changes
the voltage levels on the CC lines. Debounce the rdd disconnect signal
for 2 seconds so cr50 will ignore the negotiation and keep CCD enabled.
BUG=chrome-os-partner:60924
BRANCH=none
TEST=connect suzyq. Make sure usb does not drop out during a EC sysjump
or reboot.
Change-Id: I95b9bc81f736e3b7a65103817c140874b1ed34ec
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/426398
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
A valid charge port is always detected as VBUS supplier type, 'USB charger'
can detect the same port as BC1.2 DCP supplier type & also 'TCPC' can
detect the same port as TYPEC supplier type. Thus a valid port is detected
as 2 or 3 supplier types. Depending on the supplier's priority and the
power that the supplier can provide, charge manager choses the charge
supplier type of the port.
If the USB charger detected supplier is BC1.2 DCP and the TCPC detected
supplier is TYPEC then the supplier can provide stable current from TYPEC
supplier's advertised current hence start ramping from TYPEC supplier's
advertised current.
BUG=chrome-os-partner:61420
BRANCH=none
TEST=Manually tested on reef. Donette bottom port can switch
from 1.5A to 3A upon high load.
Change-Id: I871eca3ae4041f00bb3fd50e6aa939643f30a1f2
Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/427961
Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
Use the 'echo' command to suppress unwanted build output when V=0.
Signed-off-by: Simon Glass <sjg@chromium.org>
BUG=chromium:680243
BRANCH=none
TEST=V=0 emerge-reef chromeos-ec; See that the tpm output is gone
Change-Id: Ia742b0b5270b969ec4f51967810e616348e39dbd
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/427365
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Add a 'echo' command which can be called to generate output. If V=0 then
it is suppressed. This drops the unwanted output when V=0.
Signed-off-by: Simon Glass <sjg@chromium.org>
BUG=chromium:680243
BRANCH=none
TEST=V=0 emerge-reef chromeos-ec; See that the BUILD lines are gone
Change-Id: Ie4474024c84345d427f4d95a9ff194dc740f860f
Reviewed-on: https://chromium-review.googlesource.com/427364
Commit-Ready: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
At present the EC Makefile supports two levels of verbosity:
V unset: Show an abbreviated build log (operation and file only)
V=1: Show the full build log, including all commands
However, even the abbreviated build log includes a lot of output. It is
basically a long list of filenames and is of little use during
development. It is more useful to show just warnings and errors.
Add a new setting, V=0, which provides this.
BUG=chromium:680243
BRANCH=none
TEST=emerge-reef chromeos-ec; test each of V=, V=0, V=1 and see that the
Makefile does the correct thing.
Change-Id: I85c0423c5299fa3ab624ed9f7f7b6b7f73236611
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/427363
Reviewed-by: Randall Spangler <rspangler@chromium.org>
BRANCH=reef
BUG=chrome-os-partner:61849
TEST=1. DC mode, enter battery cutoff.
2. After system shutdown, wait 10sec.
3. Plug in AC to check system power on.
Change-Id: I5f4cf023fa70cff42c2d1cc888b1d2ee39226af4
Signed-off-by: David Huang <David.Huang@quantatw.com>
Reviewed-on: https://chromium-review.googlesource.com/427441
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Detachable devices need firmware help to process battery disconnect
requests promptly.
The request happens when the user keeps pressed both power and "volume
up" buttons and yanks the charger cable.
Once this condition is detected a 5 s timeout is started, and if the
charger cable is not plugged back in during this interval, the code
initiates a low polarity pulse on both EC_RST_L and BAT_EN outputs.
Lowering BAT_EN level will cause the battery cut off which is supposed
to cause an immediate system power down.
BRANCH=none
BUG=chrome-os-partner:59833
TEST=verified desired behavior on an H1 dev board with a H1B2-D chip.
Change-Id: Iecdcc93e228f4bc18734569bd896b0afa4bb752a
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/426345
Reviewed-by: Marius Schilder <mschilder@chromium.org>
There are three different H1 B2 chips SKUs in the wild now, one
version is for clamshell Chromebooks, one is for experimental build of
Poppy and one for detachable devices.
The SKUs differ by some fuse settings, as outlined by the comment in
the code.
This patch maps fuse settings into the chip revision string and also
makes sure that the revision is determined once and then used for all
following invocations of system_get_chip_revision().
BRANCH=none
BUG=chrome-os-partner:59833
TEST=verified that on dev boards with three different H1 B2 SKUs the
revision is reported as expected (B2-C, B2-D and B2-P).
Change-Id: I7d588d7326c28e9fa4921351254ad60a21c3f6b8
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/426344
Reviewed-by: Marius Schilder <mschilder@chromium.org>
Reviewed-by: Carl Hamilton <carlh@chromium.org>
Add CONFIG_CHARGER_PROFILE_OVERRIDE, and it can check battery state
to set charge or discharge between battery capacity 95-100%.
BUG=chrome-os-partner:61767,chrome-os-partner:57571
BRANCH=reef
TEST=check unit can charge to 100%, then discharge to 95%, then
swich to charge until 100%. Loop charge and discharge between
95-100%.
Change-Id: I4f68e5a2d51e26f62ed7f6bd6ae7af061225f8cb
Signed-off-by: Bruce.Wan <Bruce.Wan@quantatw.com>
Reviewed-on: https://chromium-review.googlesource.com/426444
Commit-Ready: Keith Tzeng <keith.tzeng@quantatw.com>
Tested-by: Keith Tzeng <keith.tzeng@quantatw.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Workaround to Pyro DVT system can not power on when system at G3 state.
Hardware has leakage with LID_OPEN pin to touch control board if system
turns off PP3300 power rail, so enable CONFIG_POWER_BUTTON_IGNORE_LID
on temporarily.
BRANCH=reef
BUG=chrome-os-partner:61707,chrome-os-partner:61696
TEST=Manual.
Verify power button can power on system on pyro DVT touch sku.
Change-Id: I23608ae508ca419cecc3642d36eeee089a870778
Signed-off-by: Devin Lu <Devin.Lu@quantatw.com>
Reviewed-on: https://chromium-review.googlesource.com/426309
Commit-Ready: Keith Tzeng <keith.tzeng@quantatw.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* Rename PRIVATE_HOST_COMMAND_VALUE to EC_PRIVATE_HOST_COMMAND_VALUE to
make it clear it is part of EC and reduce the likelihood of collisions.
* Move PRIVATE_HOST_COMMAND_VALUE macro to ec_commands.h. This reduces the
transitive dependencies required to determine the value of a private host
command. This is beneficial for code outside of the ChromiumOS build
environment that needs to send private commands to an EC.
* Define DECLARE_PRIVATE_HOST_COMMAND when there is no host command task.
This will prevent builds with private commands from failing when the host
command task is not configured.
BUG=chromium:570895
BRANCH=none
TEST=make -j buildall
Change-Id: Iad938cb6a1521b65e4f893439d592ef375caace9
Reviewed-on: https://chromium-review.googlesource.com/426737
Commit-Ready: Carl Hamilton <carlh@chromium.org>
Tested-by: Carl Hamilton <carlh@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
Very similar to CL:424846, enable sensor FIFO, accel interrupt.
BUG=chrome-os-partner:61098
TEST=Not test on actual hardware.
BRANCH=none
Change-Id: Ie5c7304fcc00919cce62ed47a548104e8d0ac454
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/426880
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
Fix cros_workon_make --board eve chromeos-ec --install
The test phase would fail at compilation because TASK_ID_MOTIONSENSE
is not defined.
BUG=chromium:61748
TEST=Check that with the change cros_workon_make pass.
BRANCH=none
Change-Id: Ib50aad492e9cfb38c56a3c6c8d4f2bb2b297ea85
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/426879
Tested-by: Todd Broch <tbroch@chromium.org>
Reviewed-by: Todd Broch <tbroch@chromium.org>
Callers may not need computation of the public key.
Making this optional speeds this routine up.
Cr50 never passes in NULL for any argument, so is not affected.
BUG=none
TEST=build
BRANCH=none
Change-Id: Ia0077a35064f53b53f51867254aaa51eac6c55d8
Reviewed-on: https://chromium-review.googlesource.com/427058
Reviewed-by: Marius Schilder <mschilder@chromium.org>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Tested-by: Marius Schilder <mschilder@chromium.org>
We don't need to loop and waiting ADC's data valid flag
after the change was made.
Signed-off-by: Dino Li <dino.li@ite.com.tw>
BRANCH=none
BUG=none
TEST=1. We build a EC binary for PD EVB (declared two ADC channels
for VBUS measurement of PD task and priority is highest)
2. Use console command "adc" continually to read ADC channels
and check if any error.
Change-Id: I1379e0b4c9ef721c29cb053d7d85e1a8ece9471b
Reviewed-on: https://chromium-review.googlesource.com/421307
Commit-Ready: Dino Li <Dino.Li@ite.com.tw>
Tested-by: Dino Li <Dino.Li@ite.com.tw>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
When depthcharge invokes a Host command that needs EC to access
flash, the response is delayed by approx 150 ms because EC is
busy with another flash operation to determine size of RW image
for computing hash. We can eliminate this delay and also speed up the
flash operation by using the same mechanism that is used for mec1322
based designs which also use external SPI flash.
The changes are:
a) We access 4 bytes from SPI flash at a time instead of a single byte
b) We split flash accesses into smaller parts which means that mutex lock
is acquired for a short duration.
BUG=chrome-os-partner:59875
BRANCH=none
TEST=make buildall -j
After sysjump to RW, in EC Log the "hash start" is printed approx
120 ms earlier.
Change-Id: Icb633379c992e795ba40eaf54fe9ec31747d4be6
Signed-off-by: Shamile Khan <shamile.khan@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/426016
Reviewed-by: Shawn N <shawnn@chromium.org>
We have hard timing requirements once we begin to output our host
command response, and most of the time is spent copying our response to
OBUF. Optimize our copy loops to remove needless increments and to avoid
needless struct dereference.
BUG=chrome-os-partner:61304
BRANCH=gru
TEST=Manual on kevin, verify the following performance metrics:
Time spent in shi_fill_out_status(): Was 40us, now 28us
Time spent in shi_write_half_obuf(): Was 60us, now 31us
Time spent in shi_write_first_pkg_outbuf:
Was 90us, now 37us (bad case)
Was 26us, now 16us (better case / less data copied)
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: I04075c92744eeefe8f2be009e6598718c45143c4
Reviewed-on: https://chromium-review.googlesource.com/425330
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
Follow reef setting.
This patch changes the entry/exit model for S0ix from a PCH
SLP_S0 signal based model to a hybrid host event/direct interrupt
model. The kernel will send host events on kernel freeze/thaw exit;
EC will initiate the S0ix entry based on host command and exit via
another host command from kernel.
The assertion of SLP_S0 comes later than HC(suspend) and deasserion
of SLP_S0 comes earlier than HC(resume).
________ ________
SLP_S0 |______________________|
_____ ________
HC |___________________________|
BUG=none
BRANCH=reef
TEST=make buildall
Change-Id: I1073b5cb2cbb8492cec0967f2a6004c5ce368ecb
Signed-off-by: Bruce.Wan <Bruce.Wan@quantatw.com>
Reviewed-on: https://chromium-review.googlesource.com/426558
Commit-Ready: Bruce Wan <Bruce.Wan@quantatw.com>
Tested-by: Bruce Wan <Bruce.Wan@quantatw.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Follow reef setting.
On the bd9995*, back boosting may occur when actual battery voltage
drops below VBAT register setting. Maintain the VBAT register at the
battery-requested charge voltage even when not charging to ensure the
bd9995* doesn't become a back boosted animal.
BUG=none
BRANCH=reef
TEST=make buildall
Change-Id: Ie7aaffc38fef65721886d00be3d6827e9e124efa
Signed-off-by: Bruce.Wan <Bruce.Wan@quantatw.com>
Reviewed-on: https://chromium-review.googlesource.com/426499
Commit-Ready: Bruce Wan <Bruce.Wan@quantatw.com>
Tested-by: Bruce Wan <Bruce.Wan@quantatw.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
When we switch to a state where the sensor is not powered,
we don't call set_data_rate(0), because we may trigger an i2c/spi access
to a sensor already powered off. It has the side effect to leave
data->odr to the last set sensor frequency.
When we init the BMI160, it starts in suspend mode. We will set it to
normal mode only if data->odr is 0. Therefore, we must set odr to 0 in
the init routine.
BUG=chrome-os-partner:61502
BRANCH=reef,kevin
TEST=On reef, without this change. When going to S5 (shutdown -h 0) and
power back up, sensor is stuck (on EC, accelread 1 reads old value).
With this fix, sensor is active and working.
This fix a regression due to CL:411964.
Check others driver do not check odr for setting suspend/normal mode.
Change-Id: Ibc7519d49e55a0b43b4c12ed545bd75ab0260766
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/426766
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
It is not proper to use SET_BIT macro to clear a "write 1 to clear" bit
in a register. It will also clear other bits if they are also set.
BRANCH=none
BUG=chrome-os-partner:34346
TEST=make buildall; boot up on gru, run ectool stress test for a while
without problem.
Change-Id: I0c5a850e85e41820515b1a8f15bb43d77397737f
Signed-off-by: CHLin <CHLIN56@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/425589
Commit-Ready: CH Lin <chlin56@nuvoton.com>
Tested-by: CH Lin <chlin56@nuvoton.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
