Would be useful to expose more of the GProbe commands to developers
who have access to boards console (hoho, honeybuns). This CL adds
a console command and seeds it the 'mcdp info' command.
Signed-off-by: Todd Broch <tbroch@chromium.org>
BRANCH=samus
BUG=chrome-os-partner:35939
TEST=manual, with CONFIG_CMD_MCDP defined in board/hoho/board.h
- Enter info console command multiple times and see correct
return value.
mcdp info
family:000e chipid:0001 irom:1.0.0 fw:0.0.0
Change-Id: Iaf2c088d5da1af7b2dab11abcfb6e32e289066ea
Reviewed-on: https://chromium-review.googlesource.com/272692
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Commit-Queue: Todd Broch <tbroch@chromium.org>
Tested-by: Todd Broch <tbroch@chromium.org>
Add first version of TCPCI (type-C port controller interface),
which is an I2C protocol for interfacing with TCPCs.
This is roughly tracking version 0.56 of the PD Interface spec.
BUG=none
BRANCH=none
TEST=tested on oak. modified oak EC to be TCPM and oak PD to
be TCPC and tested we can negotiate with hoho and zinger.
Change-Id: I83644ca83f2d3ce69d5d8356beca20a7ab155a87
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/270172
Fix master i2c when sending partial transfers using I2C_XFER_START
and I2C_XFER_STOP.
BUG=none
BRANCH=none
TEST=Tested i2c transfers on oak. tested transfers with
I2C_XFER_SINGLE (I2C_XFER_START | I2C_XFER_STOP) and tested
partial transfers with just one flag. For partial transfers
I tested two different types:
- i2c_xfer START only transmitting, then another i2c_xfer with
more trasnmitting followed by a STOP. verified with logic
analyzer that there is not restart in the middle.
- i2c_xfer START with transmitting and receiving, then another
i2c_xfer with more receiving followed by a STOP. verified with
logic analyzer that there is one restart in between
transmitting and receving and no restart in between the two
calls to i2c_xfer.
Change-Id: Ie4146d1cf7d39f7dc56fd02e65add6bf02772e67
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/272690
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Add config options for various parts of USB PD stack:
CONFIG_USB_POWER_DELIVERY: The use of this option has changed
slightly. It now represents whether or not to include the USB
PD protocol and policy layers of the software stack.
CONFIG_USB_PD_TCPC: Compile in type-C port controller module
which performs the phy layer of the PD stack.
CONFIG_USB_PD_TCPM_STUB and CONFIG_USB_PD_TCPM_TCPCI: If
CONFIG_USB_POWER_DELIVERY is defined, then one TCPM needs to
be defined to declare which port management module to use
to drive the TCPC.
BUG=none
BRANCH=none
TEST=make -j buildall
Change-Id: I41aa65a478e36925745cd37a6707f242c0dfbf91
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/270171
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Initial split of the USB PD protocol code to create the new port
controller (TCPC) and port management (TCPM) blocks. The intention
is that the TCPC code will eventually reside on a different MCU,
along with the USB PD phy layer. The TCPM will stay with the protocol
and policy layers and provide a standard interface to TCPC (over
i2c).
As a first step, this CL merely splits up the files and directly
calls functions to reach across between TCPM and TCPC.
BUG=none
BRANCH=none
TEST=tested on samus using zinger, hoho, another samus, donette,
and a third party PD charger. Tested the following:
- dual-role toggling
- forming a connection as a source and as a sink
- power negotiation at different voltages
- charging
- sourcing power to USB stick
- soft reset
- hard reset
- power swap
- data swap
- bist mode 2
- zinger remote firmware updates
Change-Id: I70bd68a003c81e075310913f10351b792f76d7e0
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/266923
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
The battery of cyan only support specific shipmode command.
BUG=chrome-os-partner:40464
BRANCH=cyan
TEST=verify that "ectool batterycutoff" and "ectool batterycutoff
at-shutdown" are workable.
Change-Id: I48538d57eda77ae798b3b843252df297c2d8fa81
Signed-off-by: Henry Hsu <Henry.Hsu@quantatw.com>
Reviewed-on: https://chromium-review.googlesource.com/272414
Reviewed-by: Mohammed Habibulla <moch@google.com>
stm32f051 I2C slave does not clear transmit interrupt status (TXIS) on
receiving NACK. That fails to support I2C master repeated-start read.
This change moves slave transmit from host command thread's TXIS loop to
interrupt event loop. And enables NACK interrupt to handle master
restart. On the I2C master side, this CL adds i2c_xfer flags.
With this CL, stm32f0 EC can talk to stm32f051 PD through host commands.
BRANCH=None
BUG=None
TEST=make BOARD=<board with stm32f0 EC and PD>
Verify EC console command "pdcmd 1 0 0x10 0x20 0x30 0x40"
Change-Id: I771b4fb3de3732f18da90ea5e27a79afb09689b0
Signed-off-by: Rong Chang <rongchang@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/267041
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Trybot-Ready: Vincent Palatin <vpalatin@chromium.org>
EVT board should enable it (low) since we need a workable track pad in factory.
Pre-EVT board work fine because of unstuffed resistor.
BUG=none
BRANCH=cyan
TEST=Check the pin is low by ec console.
Change-Id: I9602534aeadca76e24915d12701b3cd4e801746a
Signed-off-by: Henry Hsu <Henry.Hsu@quantatw.com>
Reviewed-on: https://chromium-review.googlesource.com/272103
Reviewed-by: Shawn N <shawnn@chromium.org>
Add CONFIG_LTO to use GCC Link-Time Optimizations to try to reduce the
flash footprint of the firmware.
Add additional protection to some functions/data to avoid removal by the
linker when their usage is not obvious.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=none
BUG=none
TEST=make buildall (with and without LTO enable on all boards)
Change-Id: I586b8c1eda4592b416c85383b65153c1d5ab0059
Reviewed-on: https://chromium-review.googlesource.com/271291
Trybot-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
Debounce time for the GPIO SYS_RESET_L is 16ms hence increased the time
delay between SYS_RESET_L pin toggling to 20ms.
BUG=chrome-os-partner:40246
TEST=Tested "apreset cold" EC console command on Kunimitsu
BRANCH=none
Change-Id: If17229ce485de708b550ec84939e2696e451cb0c
Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/270776
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Common battery cut-off host command / console command infrastructure
already exists behind CONFIG_BATTERY_CUT_OFF, so add the config rather
duplicating the code at the board level.
BUG=chromium:488157
TEST=Manual on Squawks. Verify that both "cutoff" on the ec console and
"ectool batterycutoff" succeed to cut-off the battery.
BRANCH=None
Change-Id: I159026d54924e058ea0262db04d8770c663ee613
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/271513
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Correct image offsets to reflect our actual layout.
BUG=chrome-os-partner:39741
TEST=Manual on Cyan. Verify EC image boots and FMAP RO_FRID and RW_FWID
point to our actual IDs.
BRANCH=None
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: If0c4e44f45cac1cdc0a99cf0ae4c17e0ead95486
Reviewed-on: https://chromium-review.googlesource.com/270353
Reviewed-by: Bernie Thompson <bhthompson@chromium.org>
The HotPlug Detect signal generated by the PD stack in DisplayPort
alternate mode is connected to a 1.8V GPIO on the T210 AP, we need to
set the GPIO output as open-drain.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=none
BUG=none
TEST=manual, probe the level with a voltmeter and see 1.8V.
Change-Id: I627befc61ed06c75dd7e32a8541bd6d8f8e95642
Reviewed-on: https://chromium-review.googlesource.com/271553
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
- Use CONFIG_*_MEM when dealing with images in program memory.
- Use CONFIG_*_STORAGE when dealing with images on storage.
- Use CONFIG_WP when dealing with the entire WP RO region.
BUG=chrome-os-partner:39741,chrome-os-partner:23796
TEST=Manual on Cyan with subsequent commit. Verify that FMAP matches
actual layout of image. Verify flashrom succeeds flashing + verifying EC
image using host command interface.
BRANCH=None
Change-Id: Iadc02daa89fe3bf07b083ed0f7be2e60702a1867
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/270269
Added firmware version check to handle the following cases:
- when the data table version is the same and fw version is newer
or
- when the fw version is the same and data table version is newer.
BUG=chrome-os-partner:36310
BRANCH=none
TEST=Verified on Glimmer.
crosh> battery_firmware check
crosh> battery_firmware update
Change-Id: If3d28f6ae7a89fc7c41fd60214ab3616f1abfe5a
Signed-off-by: Sheng-Liang Song <ssl@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/270387
Reviewed-by: Shawn N <shawnn@chromium.org>
If can get battery info, enable updates if it is Simplo Battery.
If can not get battery info, assume a Simplo Battery is a bad state.
BUG=chrome-os-partner:36310
BRANCH=none
TEST=Verified on Glimmer.
crosh> battery_firmware check
crosh> battery_firmware update
Change-Id: I0db6b50b5a382b72fd9682621990d0a6dd9e6a2b
Signed-off-by: Sheng-Liang Song <ssl@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/266044
Reviewed-by: Shawn N <shawnn@chromium.org>
Detect if the last full charge is zero or not.
BUG=chrome-os-partner:36310
BRANCH=none
TEST=Verified on Glimmer.
crosh> battery_firmware check
crosh> battery_firmware update
Change-Id: I078b860acc96f60830c82af8f85cfb98e27095cb
Signed-off-by: Sheng-Liang Song <ssl@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/263156
Reviewed-by: Shawn N <shawnn@chromium.org>
When the EC is built using "emerge-<board> chromeos-ec" on a developer
workstation with the chromeos-ec package "cros-worked'on", put
"1.1.9999-<git-sha1>" rather than "no_version" in the version string.
Emerge is exporting the current git SHA-1 hash in the VCSID id but the
.git repository is not available during the build.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=none
BUG=none
TEST=try the following build setups:
- local emerge
$ emerge-smaug chromeos-ec
$ strings /build/smaug/firmware/ec.bin | grep ryu
ryu_p4p5_1.1.9999-ebe18ef
- local build
$ make BOARD=ryu_p4p5
$ strings build/ryu_p4p5/ec.bin | grep ryu
ryu_p4p5_v1.1.3127-ebe18ef-dirt
- trybot build
$ cbuildbot --remote -g 270554 smaug-firmware
$ tar xvjf firmware_from_sources.tar.bz2
$ strings ec.bin | grep ryu
ryu_p4p5_v1.1.3137-9b52578
Change-Id: I386f80d82d95b5e99a1660a1eb242c47c54d17ef
Reviewed-on: https://chromium-review.googlesource.com/270554
Trybot-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
Add Primitive support for Bosh Sensor.
Neither gesture nor FIFO are supported.
BUG=chrome-os-partner:39900
BRANCH=none
TEST=Running accelinfo.
From user space, check values via /sys/class/iio/devices/...
Change-Id: I62dbe230c9064ec7c0fa8e343bbe6eae843e3ac0
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/270455
Reviewed-by: Sheng-liang Song <ssl@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Basic initialization of BMI160.
Fit into the existing accel/gyro framework.
BUG=chrome-os-partner:36018
BRANCH=none
TEST=Ability to read samples with accelinfo.
Change-Id: I5c86d4c3964eb6f876dd4042e5019195ffcca4ed
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/270454
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Move structure used by lms6ds0 to motion_sense.h,
so that bosh driver can use the same mechanism.
Use code to avoid reading chip range when reading data.
BUG=none
BRANCH=none
TEST=Check Bosh driver is working as expected.
Change-Id: Id8b5bb8735e479a122ef32ab9a400fba189d7488
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/270453
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Rename image geometry configs with a uniform naming scheme to make their
purposes more clear.
CONFIG_RO_MEM_OFF (was CONFIG_FW_RO_OFF) - RO image offset in program memory
CONFIG_RO_STORAGE_OFF (was CONFIG_RO_SPI_OFF) - RO image offset on storage
CONFIG_RO_SIZE (was CONFIG_FW_RO_SIZE) - Size of RO image
CONFIG_RW_MEM_OFF (was CONFIG_FW_RW_OFF) - RW image offset in program memory
CONFIG_RW_STORAGE_OFF (was CONFIG_RW_SPI_OFF) - RW image offset on storage
CONFIG_RW_SIZE (was CONFIG_FW_RW_SIZE) - Size of RW image
CONFIG_WP_OFF (was CONFIG_FW_WP_RO_OFF) - Offset of WP region on storage
CONFIG_WP_SIZE (was CONFIG_FW_WP_RO_SIZE) - Size of WP region on storage
BUG=chrome-os-partner:39741,chrome-os-partner:23796
TEST=Set date / version strings to constants then `make buildall -j`.
Verify that each ec.bin image is identical pre- and post-change.
BRANCH=None
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: I6ea0a4e456dae71c266fa917a309b9f6fa4b50cd
Reviewed-on: https://chromium-review.googlesource.com/270189
Reviewed-by: Anton Staaf <robotboy@chromium.org>
Sorted symbol maps are useful when one wants to look up an address to
associate it with a function or a variable, or to estimate how much
room certain components of the image take.
This patch adds a rule and creates a dependency to make sure that
sorted maps (assigned extension .smap) are generated during builds.
BRANCH=none
BUG=none
TEST=make buildall -j
observed 91 .elf files and 89 .smap files generated.
the two images not triggering .smap file generation are
build/npcx_evb/chip/npcx/lfw/ec_lfw
build/npcx_evb/chip/npcx/spiflashfw/ec_npcxflash
they could be added in a follow up patch if deemed necessary.
Change-Id: I196a2ffe059a83481b7a313617d516634762dc60
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/270117
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
- allow power swap only when we are dual-role toggling (ie in S0).
- enable the VCONN swap feature to support more type-C dongles.
and allow it using the same rule as power swap.
- become a power sink when we are connected to an externally powered
DRP.
- by default, try to be a data UFP for USB.
so Dual Role Device such as laptops can get our data.
- add a message to inform the AP that our USB role has changed
(but the host events are fully wired yet on Ryu)
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=none
BUG=none
TEST=make buildall
Change-Id: Id0f9027b140cb20f105bcdbc00cac5cb5f44c9e0
Reviewed-on: https://chromium-review.googlesource.com/269857
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Trybot-Ready: Vincent Palatin <vpalatin@chromium.org>
Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
The CR50 device will have to have two different drivers, for SPI slave
and master modes. This patch adds the slave driver which is called
SPS.
CR50 SPS controller uses 2KB buffer split evenly between receive and
transmit directions as two FIFOs. RX write and TX read pointers are
maintained by hardware, RX read and TX write pointers are maintained
by software.
The FIFO area allows only 32 bit writes from the CPU core, which
complicates the function placing TX data into the FIFO. There is no
limit to read access size.
Another complication is that the hardware pointers in the FIFO in fact
have 11 bits (instead of 10 required to address 1K), so the software
needs to use 10 bits when accessing the FIFO, but 11 bits when writing
the pointers into the registers.
Driver API provides three functions:
- transmit a packet of a certain size, runs on the task context and can
exit before the entire packet is transmitted.,
- register a receive callback. The callback is running in interrupt
context. Registering the callback (re)initializes the interface.
- unregister receive callback.
A CLI command is added to help testing this driver. When invoked, it
installs the callback function to handle receive data. The data is
expected to be of the following format:
<size/256> <size%256> [<size> bytes of payload]
where size should not exceed 1098 bytes.
Received frames are saved in a buffer and once received are
transmitted back to the host.
BRANCH=none
BUG=none
TEST=used the enhanced 'spiraw' utility which sends frames of random
size in 10..1010 bytes, and then clocks the line to receive the
same amount of bytes back, syncs up in the returning stream of
bytes and compares received and transmitted data.
# run 'sps 100' on the target
$ src/examples/spiraw.py -l 100 -f 2000000
FT232H Future Technology Devices International, Ltd initialized at 2000000 hertz
$
which is an indication of the successful loop back of 100 frames.
The cli command on the target exits and reports the stats:
> sps 100
Processed 100 frames
rx count 108532, tx count 51366, tx_empty count 100, max rx batch 11
Change-Id: I62956753eb09086b5fca7504f2241605c0afe613
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/269794
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
The code in board/cr50 and board/cr50_a1 directories is pretty much
identical apart from a few lines related to USB. Let's consolidate the
both board variants in the same source directory.
The command to build the cr50 board remains the same. The command to
build cr50_a1 becomes
$ make BOARD=cr50 CHIP_VARIANT=cr50_a1 out=build/cr50_a1
This is a small inconvenience to pay to avoid duplicating many patches
in two subdirectories.
BRANCH=none
BUG=none
TEST='make buildall' still succeeds
compared map files for cr50_a1 before and after the change. They
are identical modulo addition of the empty function
send_hid_event() in board.o.
Change-Id: I7584c8f215945b8b33eea4eff50c872a09ef349d
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/269160
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-by: Sheng-liang Song <ssl@chromium.org>
Add command that list supported features by the firmware.
Also let the firmware indicates if more features are expected in the RW
version.
This will help the cros_ec framework load the right driver(s) for
exposing information via sysfs.
BUG=chromium:428364
BRANCH=none
TEST=Test on samus on both ec and pd:
localhost ~ # ectool inventory
EC supported features:
1 : Flash support
2 : Direct Fan power management support
3 : Keyboard backlight support
4 : Lightbar support
6 : Motion Sensors support
7 : Keyboard support
9 : BIOS Port 80h access support
10 : Thermal management support
11 : Switch backlight on/off support
12 : Switch wifi on/off support
13 : Host event support
14 : GPIO support
15 : I2C master support
16 : Charger support
17 : Simple Battery support
18 : Smart Battery support
21 : Control downstream MCU support
localhost ~ # ectool --name cros_pd inventory
EC supported features:
1 : Flash support
14 : GPIO support
15 : I2C master support
22 : USB Cros Power Delievery support
Change-Id: Ib6eaac91fda86835e754c5316ecf81fbc27786e5
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/263463
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Sameer Nanda <snanda@chromium.org>
Enable the support to be a USB-PD alternate mode DFP and add
configuration for the DisplayPort alternate mode and the GFU mode.
Only on Ryu P6 as the P5 board is using the HPD line for the power
sequencing workaround.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=none
BUG=chrome-os-partner:39946 chrome-os-partner:38689
TEST=on Ryu P6, plug a Hoho dongle, see that the superspeed muxes are in
DP1 or DP2 mode (using the "typec 0" command), plug and unplug an HDMI
monitor and see the HPD line moving when typing "gpioget USBC_DP_HPD".
> pd 0 state
Port C0, Ena - Role: SRC-DFP-VC Polarity: CC1 Flags: 0x1150, State:
SRC_READY
> adc
VBUS = 4980
CC1_PD = 992
CC2_PD = 57
> typec 0
Port C0: CC1 993 mV CC2 58 mV (polarity:CC1)
Superspeed DP1
> gpioget USBC_DP_HPD
0 USBC_DP_HPD
<--- PLUG monitor --->
> gpioget USBC_DP_HPD
1* USBC_DP_HPD
Change-Id: Ie25a3bb0d6331c1d931b7f542fbc637270c20b3b
Reviewed-on: https://chromium-review.googlesource.com/269855
Trybot-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Reviewed-by: Todd Broch <tbroch@chromium.org>
Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
The same code exists in four (soon to be five!) different power
sequencing drivers, so move it up to common.
BUG=None
TEST=Manual on Samus. Run "pause_in_s5 on" on EC console, verify that
system stops in S5 on shutdown. Run "pause_in_s5 off" on EC console,
verify that system again goes to G3 on shutdown.
BRANCH=None
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: Iaf05ef7ce017be4f9d173e83e985a7a879ba278c
Reviewed-on: https://chromium-review.googlesource.com/269566
Reviewed-by: Randall Spangler <rspangler@chromium.org>
ModemManager likes to play with serial ports it shouldn't
play with, mark our serial ports as off limits.
This also bumps the ordering of this rules file just past
the udev default rules because it uses environment variables
populated by that file.
Signed-off-by: Anton Staaf <robotboy@chromium.org>
BRANCH=None
BUG=None
TEST=install new rules file, delete old rules file
verify that symlinks to TTY's are still created
verify that ModemManager leaves them alone now
Change-Id: I4ded95192d78b5b1bbc661ca5b762e18307d2d60
Reviewed-on: https://chromium-review.googlesource.com/269743
Trybot-Ready: Anton Staaf <robotboy@chromium.org>
Tested-by: Anton Staaf <robotboy@chromium.org>
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
Commit-Queue: Anton Staaf <robotboy@chromium.org>
Add setting the Pericom D+/D- switch state to board_set_usb_mux().
This is useful on Ryu because we have to fully debounce the type-C
CC lines before setting the SS muxes, ~100ms, and we don't want
the host to give up on enumerating SS while we are debouncing. So,
instead, we keep the D+/D- lines disconnected until after we
debounce and right before setting type-C muxes for SS.
BUG=none
BRANCH=none
TEST=make -j buildall
Change-Id: Ifb7c06d82e35c312ebfce871bff0056a83b4887a
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/269250
Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
The charger chip is supposed to handle this feature in hardware.
Let's disable the software version to exercise the hardware.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=none
BUG=chrome-os-partner:38603
TEST=on Ryu P6, plug BC1.2 chargers through legacy A-to-C cable.
Change-Id: I074eee0621ba8d23c7ef87dd251ce8fbf86a0265
Reviewed-on: https://chromium-review.googlesource.com/269518
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
