Refactor ADC code and move board/chip-specific part to corresponding
directories.
Implement function and console command to read Link charger current.
BUG=chrome-os-partner:7527
TEST=Read EC temperature and POT input on BDS.
Change-Id: I7fafd310ea49d9b2781f10c3453f5488da29a08a
Expand the macros before building the priority variable name in order to
ensure we have a valid name.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BUG=None
TEST=check manually preprocessor expansion for several combinations.
Change-Id: I926821d42c966ac674e7d24254c9f22779f93ca2
Run from internal clock at 16Mhz, but enable PLL to get a better
precision.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BUG=None
TEST=run on discovery board and check software is still alive after
clock initialization.
Change-Id: I8425482825015adf96c30e67a9320d0df2f4f2b7
Define IRQs and register addresses for basic peripherals to do STM32L
bringup.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BUG=None
TEST=mostly untested, there should be typos over there...
Change-Id: Ib6d90436e25be74f724112619cdae7acccfaf085
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=chrome-os-partner:7718
TEST=manual
// enable fan
gpioset enable_vs 1
// set fan speed to 7000
fanset 7000
faninfo
// should report duty cycle about 65%, fan speed about 7000 rpm, status = 2
fanset 4000
faninfo
// should report duty cycle about 25%, fan speed about 4000 rpm, status = 2
fanset -1
// should report duty cycle 100%, fan speed about 8800 rpm, status = 3
Change-Id: Ib7d7df14ad240811e6e79bc1fc4ecf0e6841c334
I keep hitting the darn arrow keys. Until we can do something more
elegant like a real command history, this will at least keep me from
corrupting the display and input buffer.
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=none
TEST=type 'help' and some arrow keys, then enter. Should print help, not an error.
Change-Id: Idb552e9c22876fc2dc1f349f0038e94048f00aa7
To assist in x86 chipset bringup, there are 4 GPIOs we weren't
printing state transitions for.
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=none
TEST=reboot; should see state transitions in the high nibble (mask 0xF000), for example:
[x86 power state 1 = S5, in 0x2001]
[x86 power state 1 = S5, in 0x3001]
[x86 power state 1 = S5, in 0x7001]
Change-Id: I0527e4698425d845e8b08589e89592f95d8bee41
Keyboard scanning was not properly configuring GPIOs on link. Among
the problems, it was setting GPIO level then direction, when it needs
to set direction first. Also fixed this in gpio pre-init.
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=chrome-os-partner:7761
TEST=1) press keys on keyboard; see keyboard state change on console
2) 'gpioget PCH_PWRBTNn' should report 1 after boot, not 0
Change-Id: I54010aa6eef1de4822574f964de369b459ee6d0f
All hardware drivers code is stubbed excepted a few configuration
settings.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BUG=None
TEST=make BOARD=discovery
Change-Id: Ic9e88a0f51ab626679c8aeb6192272e66a3f79b8
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=chrome-os-partner:7528
TEST=x86power s0; should turn on all power rails (check via gpioget)
Change-Id: I284ac2104e02748ed69408873fbcebb9d54cdcff
Preparatory work to introduce a second SoC : 3rd series 2/2
All the RO/A/B firmware copy code could be generic to all our platforms.
The console commands are a 'standard' API.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BUG=None
TEST=on BDS EC console, check the reset cause with the 'sysinfo' command.
Change-Id: Ieeb84571085d88b5747a09da4c33d3852bb0da96
Preparatory work to introduce a second SoC : 3rd series 1/2
Most of the code is handling the buffering and the printf, thus put it
in an hardware independant location and only implement the UART
dependant portions in the chip driver.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BUG=None
TEST=run on BDS and stress the console.
Change-Id: I9376f2fa1dad341eac808e1756dbeff32900bd51
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=none
TEST=push and release power button; should see debug messages
Change-Id: I4a08b56247baa85555514623db7a04ab4638ca0e
with x86 power module enabled, it no longer fits in 32KB.
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=none
TEST=make
Change-Id: I38c9054efd8a072cc5800cc87936e53e2df00e58
Preparatory work to introduce a second SoC : 2nd series 4/4
Add a build time assertion which checks whether the UART used in the C
uart code is the same one as the one defined for assembly panic code.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BUG=None
TEST=build for BDS with both good and bad address in CONFIG_UART_ADDRESS
Change-Id: I28dd6089bc938f06be0654d7bed75d7d698fafe0
Preparatory work to introduce a second SoC : 2nd series 3/4
Some modules won't be used on other designs, make them optional.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BUG=None
TEST=run the EC firmware on BDS and check that the commands from the
optional features are still available and working.
Change-Id: I979864ed94dc4da90c1010bd2e4589d84bc2d046
Preparatory work to introduce a second SoC : 2nd series 2/4
Avoid introducing platform specific dependencies in common files where
they are not necessary.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BUG=None
TEST=build for BDS and Link
Change-Id: If2ccd022e4956425222b55a5a48ca7522857e7f0
Preparatory work to introduce a second SoC : 2nd series 1/4
The atomic operations are SoC independant since they are only using
LDREX/STREX instructions which are just core specific ARMv7-M).
The watchdog header defines the API which is common to all platforms.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BUG=None
TEST=run EC firmware on BDS and check a few console commands
Preparatory work to introduce a second SoC : 5/5
All Cortex-M3/4 have the same NVIC registers at the same address.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BUG=None
TEST=run EC firmware on BDS and check a few console commands
Change-Id: I6b03c4c1fb21850be8c8afb711ea44134c8cdea1
Preparatory work to introduce a second SoC : 4/5
Allow to use the common code for most SoC.
Also simplify the UART code, we don't need speed on the panic path.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BUG=None
TEST=trigger a panic and check the UART output on BDS
Change-Id: I11f7bbc571ab9efbc21fb7b805bf4e271b192c3b
Preparatory work to introduce a second SoC : 3/5
We split the drivers files which contain SoC specific drivers from the
OS files which only depend the actual CPU core.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BUG=None
TEST=run EC firmware on BDS and test a few commands on the console.
Change-Id: I598f8b23e074da9bd6b0e2ce6689c1075fe854f0
Preparatory work to introduce a second SoC : 2/5
The hwtimer.* files implement the driver for the SoC timer block.
The timer.* files provides the OS level clock/timer functions.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BUG=None
TEST=on BDS, check 'waitms' and 'gettime' on the EC console.
Change-Id: Icbc58d9be59ee268e2d5a94f8b20de0cabcdc91d
Preparatory work to introduce a second SoC : 1/5
Instead of putting hardcoded IRQ SoC name in the vector table,
upgrade the DECLARE_IRQ macro to expand its argument.
Also add a parameter to set the size of the NVIC table to save flash
memory.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BUG=None
TEST=run EC on BDS and see timer IRQs firing.
Change-Id: I44fefdabdd37d756492a71f24554979c72c1b50f
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=none
TEST=at EC console, gpioget twice, then toggle an output using gpioset, then gpioget again
May see *'s the first time. Second time, should see no *'s. Third
time, should see a * only the toggled output (and any input signals
which respond to it).
Change-Id: Ibc1870839201008592b7982049cc352c1779a0e3
This fixes linker errors when the X86_POWER and/or POWERBTN tasks are disabled.
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=none
TEST=remove X86POWER and POWERBTN tasks from ec.tasklist and make
Change-Id: I8a95020925e32ac4f80b9363f5aa6ab0a2d9ccd1
Exercise all basic use cases on mutexes.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BUG=None
TEST=make qemu-tests
Change-Id: I40de3ae59862db96b40a067c9ad54a978f5646b8
They are designed to protect shared hardware resources (e.g. I2C
controller).
Please refrain using them as a general purpose synchronization primitive
for the tasks to avoid unintended slippery effects (e.g. priority inversion),
use the provided message-passing functions instead for that purpose.
The mutex variable (ie the "struct mutex") should be initially filled
with 0, but this is the default compiler behavior if you declare it as a
global variable.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BUG=None
TEST=make qemu-tests
Change-Id: I328f7eadf5257560944dbbbeda0b99d5b24520e8
This script is automatically loaded when launching 'openocd -f
openocd.cfg'.
It adds 'flash_bds', 'ramboot_bds' commands to the openOCD console. The
former is writing the current EC firmware inside the internal flash, the
latter is loading a RAM only firmware on the chip.
There are similar commands for the Link Proto-0 board :
'flash_link', 'ramboot_link'.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BUG=none
TEST=type 'flash_bds' from openocd telnet console
Change-Id: Ic63281a99ee1d083986696675ed0a82da7c033ee
You can now enable/disable tasks more easily.
To conditionally compile a C file depending on the task FOO activation,
just write something like that in the build.mk file :
common-$(CONFIG_TASK_FOO)+=foo_source.o
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BUG=None
TEST=make all BOARD=link && make qemu-tests
Change-Id: I760fb248e1599d13190ccd937a68ef47da17b510
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=chrome-os-partner:7703
TEST=reboot; look for "Hello on UART1" message on UART1 (which is uart2 on servo)
Change-Id: Ie497af48e62c28174b69adca5bea52d2f68d494f
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=chrome-os-partner:7527
TEST=run 'temps' from console. Should print info on 4 sensors.
Change-Id: I8e0165235f9a12233bc3ac1fbde55c8eb3cfbb00
Instead of using a runtime callback to register the console commands,
put them in a special linker section. So we can do a macro to "register"
them during the build.
It saves 684 bytes and a few microseconds at startup.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BUG=None
TEST=run a few commands from the BDS command line.
Change-Id: Id33ea210b9035bf76ed720373c74c5dd24ccd1b1
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=chrome-os-partner:7697
TEST=if it runs, it works
Change-Id: I36ab37a8cf1c3e4bf41bfb38e622e766cee8a4c4
This works around a chip errata where the internal oscillator on early
EC parts (as used on proto0) is untrimmed.
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=chrome-os-partner:7693
TEST=if it runs, it works
Change-Id: Ie82a524543f4cf25efd0de7998dbdae103bd126b
When code is compiled for RAM (by re-enabling the flag in board.mk),
use the following openocd commands to load it:
reset halt
load_image ../../../build/link/ec.RO.flat 0x20000000 bin
reg 15 0x20000400
resume
Note that you'll also usually need to disable a bunch of modules to make
the code small enough to fit in RAM.
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=chrome-os-partner:7681
TEST=if it runs, it works
Change-Id: I2b3cc69b361ad73706af3ff6de1ce952e8d5a0a9
Ensure that all the code ends up in the expected place.
This bug beat us for the RAM only version but it is present
even in the flash version (though probably harmless).
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BUG=None
TEST=run the resulting image on BDS and inspect manually the .map file.
Change-Id: Iefe505bc507547b1043cb493ba7e8f210bb1ebc4
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=chrome-os-partner:7677
TEST=if it runs, it works
Change-Id: Ib4f28505f6b9a21375f9c3ba97c6e8d56722c051
Implement TPS2543 USB charging control.
It contains routine for setting each USB port as dedicated charging port
or standard downstream port. To allow us controlling the current
distributed to each port, we can select whether to allow 500mA or 1500mA
for each port.
BUG=chrome-os-partner:7476
TEST=Added USB port definition for BDS and tested GPIO output voltage
level is correct for all modes.
Change-Id: I19bc4b30d333aa802f868ebfc3a398b30e99ba0f
