Enable low power idle for veyron (with uart wakeup as well).
Low power idle is only active in S5/S3.
Also sorted options from board.h
BUG=chrome-os-partner:31226
BRANCH=none
TEST=load onto pinky-proto1, use idlestats command to verify that we are going
into deep sleep (STOP mode). Run 30 min. and verify no watchdog reboots or
anything out of ordinary.
Change-Id: Id14b04f33ea46b1e6cca1c8e812b5875e9ee0446
Signed-off-by: Alexandru M Stan <amstan@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/219044
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Fix potential bug in pd_soft_reset() function. That function is
part of a global API and as such can be called by other tasks.
For example, a sysjump which takes place as part of host command
task. So, this function should not directly initiate PD communication
because if it is interrupted by the PD task, then there will
be unpredictable behavior since the send_validate_message() is not
designed to be re-entrant for a given port.
This changes pd_soft_reset() to simply change the PD state to
SOFT_RESET and then wake up the task to actually send the command.
BUG=none
BRANCH=none
TEST=you can test this with a type-C to A receptacle dongle. The
dongle has a pulldown on the CC line, but no device to respond to
PD comms. When you plug in C to A cable, samus should send source
cap repeatedly for 5 seconds. During that time, if you do a sysjump
from RO to RW, it will call pd_soft_reset(), which will send the
soft reset command. But, since there is no device it will timeout
and retry 3 times. During that period, the PD task will wake up
and try to do it's own thing, causing craziness and eventually a
hang and watchdog reset.
With this fix, I can plug in a C to A adapter, and sysjump to RW
cleanly.
Change-Id: Icab936ab8ab930e8e37b5a23825f7f054a50c177
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/219893
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Vic Yang <victoryang@chromium.org>
Fix potential bug in ADC initialization. After setting ADEN bit to
enable ADC module, we must wait for ADRDY (ADC ready) bit before
continuing. This bug only affects a few chips, and only some of
the time.
BUG=chrome-os-partner:31978
BRANCH=none
TEST=Used a samus board where the PD MCU fails ADC initialization
quite often. Without this fix, if you reboot the PD MCU, it will
sometimes come up with all ADC's reading 0 and ADEN reading 0.
With this fix, it always boots with the ADC's working
Change-Id: Iba1d0e56006ba1ad6d9f0eee964a70ef2d0f8dcf
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/219522
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Vic Yang <victoryang@chromium.org>
This diff allows the user to send small programs to the EC and
gain control of the lightbar. Right now, this is only exposed
through ectool, and sysfs support will come later.
To send a program to the EC, use
$ ectool lightbar program /path/to/program.bin
and then start running the program with
$ ectool lightbar seq program
BUG=None
BRANCH=ToT
TEST=Using the above steps with hand-assembled programs.
Checked that infinite bytecode loops do not hang the EC.
Checked that bad opcodes exit with an error.
Stress tested pushing programs and changing sequences.
Signed-off-by: Eric Caruso <ejcaruso@chromium.org>
Change-Id: I635fb041a5dc5c403f7c26fb9a41b5563be9b6b7
Reviewed-on: https://chromium-review.googlesource.com/219558
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
This code is used to find the orientation of the sensor.
Given sensor are aligned with the edges of the device,
it is not too dificult to find manually.
BRANCH=ToT
BUG=None
TEST=Check ACCEL_CALIBRATE is not used anymore.
Check 'make buildall -j' works.
Change-Id: I81ffcb4f6b01c530ef16baf13113a5942f615092
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/219527
Reviewed-by: Alec Berg <alecaberg@chromium.org>
RX DMA seems to get misaligned sometimes yielding to extra bytes before the
first byte on the wire.
in_msg=[00 00 00 03 f4 09 00 00 ...]
^ real first byte
To fix this we want to reset and reinit the SPI peripheral after every packet,
in the same place where setup_for_transaction() is called.
This bug applies to the STM32F0 line but resetting the peripheral on other STM32
ECs should not break anything.
BUG=chrome-os-partner:31390
TEST=On STM32F0:
ap# cd /sys/class/power_supply/sbs-20-000b/; while true; do grep "" * >/dev/null 2>&1; done
You should not see "SPI rx bad data" with in_msg packets that have extra bytes
in the beggining. Wait though, it might take up to a few minutes for stuff to
break.
BRANCH=None
Change-Id: If9ab93c5c9040a2c7bda33d7cc990603f1121f3f
Signed-off-by: Alexandru M Stan <amstan@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/217527
Reviewed-by: Randall Spangler <rspangler@chromium.org>
This task echo's all bytes from any console stream back to all
other console streams. It is a test case for the new
multi-USART and USB stream drivers.
Signed-off-by: Anton Staaf <robotboy@chromium.org>
BRANCH=None
BUG=None
TEST=make buildall -j
Manual testing of cutting and pasting large blocks of text
into the echo'ed usarts, and verifying no dropped characters.
Change-Id: I408c77e40931d3a473657326f9772e71a7ae8a60
Reviewed-on: https://chromium-review.googlesource.com/213178
Reviewed-by: Vic Yang <victoryang@chromium.org>
Commit-Queue: Anton Staaf <robotboy@chromium.org>
Tested-by: Anton Staaf <robotboy@chromium.org>
STM32F and STM32F0 series require an MOE bit to be set to enable PWM
output. In addition, require that the PWM alternate function # be
manually specified for STM32F0 -- there seems to be no logical mapping
here, unlike other STM32* parts.
BUG=chrome-os-partner:32089
TEST=Manual on samus-pd. Set ILIM PWM output to 50% duty cycle with pwm
driver functions, probe and verify avg. 1.62V on pin.
BRANCH=None
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: Icb13a153fa3eee52be938d76a6c980fe6fd2bb3e
Reviewed-on: https://chromium-review.googlesource.com/219570
Reviewed-by: Alexandru Stan <amstan@chromium.org>
Tested-by: Alexandru Stan <amstan@chromium.org>
Reviewed-by: Alec Berg <alecaberg@chromium.org>
The 'power' console command is entirely redundant:
- 'power on' can be replaced by 'powerbtn'.
- 'power off' can be replaced by 'apshutdown'.
- 'power' can be replaced by 'powerinfo'.
Let's remove this command to save flash space.
BUG=chrome-os-partner:32203
TEST=Build Ryu.
BRANCH=None
Change-Id: Ib33804c1748dd44bbb89277fed938b50f0f946c4
Signed-off-by: Vic Yang <victoryang@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/219491
Reviewed-by: Alec Berg <alecaberg@chromium.org>
The warning should only warn if there's an actual danger(in order to give a
clue to developers that something might be amiss). Messages like "Overriding
SPI1_NSS with SPI1_NSS on EXTI4" are just spammy. This patch makes it so it only
warns if the interrupt is different.
BUG=chrome-os-partner:31390
TEST=spam gpio_enable_interrupt(GPIO_SPI1_NSS); in a bunch of places (like
spi_event), it should not complain about the interrupt being set to the same
thing before. Whereas before it was so spammy it did not even have time to reply
to SPI.
BRANCH=None
Change-Id: I786a821eb8167e3568d0be371c4de26bb124431a
Signed-off-by: Alexandru M Stan <amstan@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/218563
Reviewed-by: Randall Spangler <rspangler@chromium.org>
'powerindebug' is only used when there is a problem with power
sequencing. 'taskready' is rarely used and the same info can be
retrieved by 'taskinfo'.
Put both behind config flags and disable 'taskready' by default. Also
disable 'powerindebug' for Ryu.
BUG=chrome-os-partner:32203
TEST=Build Ryu and check flash space used.
BRANCH=None
Change-Id: I753a1f5411d6e840a80aba03afc94f9640d381a8
Signed-off-by: Vic Yang <victoryang@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/219490
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Just after a bad data error the EC will print the packet(pretty much the whole thing):
in_msg=[02 00 0f 03 f4 09 00 00 ]
I found it very helpful when debugging SPI TX/RX to know what the EC sees.
BUG=chrome-os-partner:31390
TEST=Load spidev and send the EC bytes manually(malformed packets)
BRANCH=None
Change-Id: I037ab909076dc454379040e2e927dc6a0b5c5ea9
Signed-off-by: Alexandru M Stan <amstan@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/218442
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Fix accel calibration bug from refactoring. The motion_get_accel_lid()
function used by calibrate routine to get lid accel data was actually
returning base accel data.
BUG=none
BRANCH=none
TEST=load onto samus, run accel calibration routine.
Change-Id: I095381390267aa6ea3b3a74311c27f30d70e9c81
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/219520
Reviewed-by: Sheng-liang Song <ssl@chromium.org>
Reviewed-by: Gwendal Grignou <gwendal@chromium.org>
Not every chip that we use has FPU. To make it easier to enable lightbar
on chips other than LM4, let's remove floating point usage in lightbar
code. Instead, scale those numbers by a factor of 10000.
BUG=chrome-os-partner:32203
TEST=Run on Samus. Visually check lightbar.
BRANCH=None
Change-Id: I88b12bb66b5c586f2e14135069bd97d6b56832a1
Signed-off-by: Vic Yang <victoryang@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/219246
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
When a cable is connected, set USBC_POLARITY to the right polarity. This
is done in a different way than how we do this on other boards because
we only want to control polarity automatically on cable connection.
BUG=chrome-os-partner:32163
TEST=Flip the cable, check USBC_POLARITY changes.
BRANCH=None
Change-Id: I903123b8fd729e8c913014b83812d20328600f8e
Signed-off-by: Vic Yang <victoryang@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/219291
Reviewed-by: Alec Berg <alecaberg@chromium.org>
When 5v/12v/20v buttons are pressed, plankton first switchs to source
role, set the requested source cap, and then perform a soft reset.
However, if plankton was sink and just switched to source, the port
partner might not have switched to sink and this leaves the CC line in a
state where communication is not possible. The subsequent soft reset
then fails. If we are not already sourcing power, we actually don't need
a soft reset after changing source cap.
BUG=chrome-os-partner:32163
TEST=Switch from sink to source. Doesn't see "soft reset" in console.
TEST=Switch from 5V to 12V. See "soft reset".
BRANCH=None
Change-Id: Ia4b834c2e7dc1324b9143c46a72938845499e2fb
Signed-off-by: Vic Yang <victoryang@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/219004
Reviewed-by: Alec Berg <alecaberg@chromium.org>
On power-on reset, the USB hub might get stuck in a locked state due to
a race condition in hardware. Let's reset the hub after 0.5 seconds to
make sure this doesn't happen.
BUG=chrome-os-partner:32163
TEST=Power on the board. Measure the reset signal.
BRANCH=None
Change-Id: I0f89883c5db7c5376f3612da1615ba4f86b5efa6
Signed-off-by: Vic Yang <victoryang@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/219199
Reviewed-by: Alec Berg <alecaberg@chromium.org>
During the communication init, ectool will probe max request and
response packet size from ec and set packet size accordind to that.
However, with older kernel's ec driver, the buffer allocated by
kernel is not large enough and this will cause kernel bug.
BUG=chrome-os-partner:31989
TEST=ectool version runs fine on blaze
BRANCH=ToT
Change-Id: I499a5305c8fa8b0fd6f3be8554c9cf066b7e0828
Signed-off-by: Puthikorn Voravootivat <puthik@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/219114
Reviewed-by: Mohammed Habibulla <moch@chromium.org>
Enable low power idle for samus_pd. Low power idle is only
entered when no USB PD device is connected.
BUG=chrome-os-partner:31226
BRANCH=none
TEST=load onto samus_pd, use idlestats command to verify
that we are going into deep sleep (STOP mode). Run 30 min.
and verify no watchdog reboots or anything out of ordinary.
Also, verify that host commands from EC work when going into
deep sleep by sending host commands on the EC console with
pdcmd 0 0.
Change-Id: I3e2e04e6c4c0a84e291286dbed90945847e0dfdd
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/218957
Reviewed-by: Todd Broch <tbroch@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
This driver can be used to access multiple usarts using an abstract
stream interface. The stream interface can also be used in drivers
for the host interface and USB console interface, providing a
consistent API across all character stream style IO.
Signed-off-by: Anton Staaf <robotboy@chromium.org>
BRANCH=None
BUG=None
TEST=make buildall -j
Change-Id: Icf567f0b0fa4eb0e9ad4cdb0be8edc31c937a7de
Reviewed-on: https://chromium-review.googlesource.com/209671
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Tested-by: Anton Staaf <robotboy@chromium.org>
Commit-Queue: Anton Staaf <robotboy@chromium.org>
Enable fast charging with profile designed for ATL cells
that will be used in EVT.
BUG=chrome-os-partner:23776
BRANCH=none
TEST=Took detailed charging/discharging data and verified
that the actual profile matches the desired profile and that
the fast charging profile is actually faster than the
standard. See bug report for more info and data collected.
Change-Id: Ic11ab89e48afb73987b8013abf8b0564e1138156
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/212980
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
Add low power idle task to stm32f0. This can be enabled
by defining CONFIG_LOW_POWER_IDLE. This low power idle
uses STOP mode to conserve power.
BUG=chrome-os-partner:31226, chrome-os-partner:28335
BRANCH=none
TEST=add #define CONFIG_LOW_POWER_IDLE to samus and use
idlestats console command to verify using deep sleep.
also #define CONFIG_FORCE_CONSOLE_RESUME and make sure
serial console works without problems when going into
deep sleep.
Change-Id: I76b0ceb8587a139faa74353d3d8efb4f689fc669
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/218956
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Bug fix. Recently changed to use HSI 8MHz clock as clock source
for console UART, but the clock register was set incorrectly
for the case that the console UART is UART2.
BUG=chrome-os-partner:32170
BRANCH=none
TEST=Tested on fruitpie which is using UART2 for console.
Verified that console works.
Change-Id: Ied629eb3828e5fab911acb6a8e5f4087563ddb32
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/219312
Reviewed-by: Vic Yang <victoryang@chromium.org>
Older versions of flash VDM supported a 'rw_hash' command that has
since been deprecated in favor of 'info' command. This CL makes
flash_pd.py try either in order to determine whether the pd flash
erase was successful.
BRANCH=none
BUG=chrome-os-partner:28330
TEST=manual, succesfully run on zinger with only 'info' command support
util/flash_pd.py -m 1 zinger_ec.RW.flat
2014-09-18 14:35:39,305 - root - INFO - Current PD FW version is zinger_v1.1.2192-5cd
2014-09-18 14:35:39,305 - root - INFO - Flashing 11532 bytes
2014-09-18 14:35:45,779 - root - INFO - Successfully erased flash.
2014-09-18 14:35:45,890 - root - INFO - Chunk 0 of 481 done.
...
2014-09-18 14:36:39,133 - root - INFO - Chunk 480 of 481 done.
2014-09-18 14:36:46,072 - root - INFO - Flashing DONE.
2014-09-18 14:36:46,072 - root - INFO - SHA-1: f6b296ba d474edc4 2e917ad0 33cd16cb 0f51a3fc
2014-09-18 14:36:46,090 - root - INFO - New PD FW version is zinger_v1.1.2226-bea
Change-Id: I32f8b06fa546aa99c8290b6b73faa9b8df05e4fb
Signed-off-by: Todd Broch <tbroch@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/218878
Reviewed-by: Alec Berg <alecaberg@chromium.org>
When waking up from sleep, the real CPU_CLOCK is a lie for a moment(since we
cannot switch to the real clock during the first character) so the first
character will be corrupted.
The UART clock is now sourced from HSI(8MHz) which is available from the first
moment after the cpu wakes up from sleep.
BUG=None
TEST=Console should work.
When waking up(not implemented yet) it will also not lose a character
BRANCH=None
Change-Id: Ia12ed0634290f3edadfe3471b311759c3176260e
Signed-off-by: Alexandru M Stan <amstan@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/218728
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Tested-by: Alec Berg <alecaberg@chromium.org>
Commit-Queue: Alec Berg <alecaberg@chromium.org>
Implement RTC alarm, with resolution 50us, for stm32f0. This
is useful for using low power modes and waking up after set
period of time.
BUG=chrome-os-partner:31226, chrome-os-partner:28335
BRANCH=none
TEST=tested on samus_pd with CONFIG_CMD_RTC_ALARM defined and
used rtc_alarm console command to test various timeout periods.
Change-Id: Ibabd8662cfbea654c7de387669f7be83af4fd79d
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/218322
Reviewed-by: Todd Broch <tbroch@chromium.org>
Previously there was no way to remove multiple units at a time
from the queue, and the queue was wasting an entry to disambiguate
full from empty. There was also no way to get the free entry
count from the queue, only the ability to query if it was above
a required amount. The queue was also storing its constant
compile time configuration as well as its dynamic state in the
same structure. This wasted RAM on configuration information
that doesn't change.
This refactor fixes these issues, making the queue suitable for
use in the new USART stream driver.
Signed-off-by: Anton Staaf <robotboy@chromium.org>
BRANCH=None
BUG=None
TEST=make buildall -j
Change-Id: I284cee52d8189928dbc4c499f87ab34e14019e5a
Reviewed-on: https://chromium-review.googlesource.com/210533
Reviewed-by: Vic Yang <victoryang@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Commit-Queue: Anton Staaf <robotboy@chromium.org>
Tested-by: Anton Staaf <robotboy@chromium.org>
On boot, the EC should send host command to exchange status with
PD MCU. This allows EC to get the correct input current limit
when EC reboots and PD does not.
Also had to move some of the charger state machine initialization
to run with HOOK_INIT so that it runs before the tasks run.
BUG=none
BRANCH=none
TEST=tested on EVT samus. Without this change, if you reboot
EC, and run charger command, the charger input current limit
is 512mA. with this change, when the EC reboots, it sends host
command to PD MCU to get current limit and sets it appropriately.
Change-Id: I5426f0fc3a62b6cd7a73f55cb11b895902a54903
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/216879
Reviewed-by: Todd Broch <tbroch@chromium.org>
OSPEEDR cfg for PB15 was inadvertently set to '01' for PB15 (should be
'00'). Not sure it causes any harm but shouldn't be set according to
comment which is speeding up output pins on SPI interface PB12-14
only.
BRANCH=none
BUG=none
TEST=manual, compiles, boots, talks PD w/ samus_pd.
Change-Id: Ibc2ec1c427a2c3c92ffdf424b668752b1c0b0032
Signed-off-by: Todd Broch <tbroch@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/217963
Reviewed-by: Vic Yang <victoryang@chromium.org>
Add three retries for EC to PD host commands. With this change,
removed retry mechanism in host_command_pd.c which was a retry
only for the specific EC_CMD_PD_EXCHANGE_STATUS host command.
BUG=chrome-os-partner:32006
BRANCH=none
TEST=Loaded EC code onto samus. Added the following code
for testing failed host commands to samus_pd common/host_command.c
host_command_task():
if ((evt & TASK_EVENT_CMD_PENDING) && pending_args) {
if (i++ != 4)
pending_args->result =
host_command_process(pending_args);
else {
pending_args->result = -7;
i = 0;
}
host_send_response(pending_args);
}
This test code on samus_pd drops one in every five host commands.
With this code, from the EC, I send "pdcmd 0 0", and verified that
1 out of 5 times the EC prints a host command failed code, but then
retries successfully.
Change-Id: Ibf43feefbfc7d791c45c6689b82c66f5d71046ab
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/217461
Reviewed-by: Todd Broch <tbroch@chromium.org>
The PWRON signal is actually a pulse that's only supposed to happen at the S0->S5
transition. We can release it when we see POWER_ON.
BUG=None
TEST=Power on and power off normally. "halt" makes the system go to S5 instead
of rebooting.
BRANCH=None
Change-Id: I14f1cc83c8a4a89226574cf605823d247ce9508a
Signed-off-by: Chris Zhong <zyw@rock-chips.com>
Signed-off-by: Alexandru M Stan <amstan@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/217690
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Setting initial max speed works by setting RPM but fails when
setting with duty cycle
BUG=chrome-os-partner:31801
TEST=booted on auron and peppy and confirmed that initial fan speed is
set to maximum
BRANCH=none
Change-Id: I81172a414df13c2e0b2d0f4fe7ff1270fa5f60a3
Signed-off-by: Mohammed Habibulla <moch@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/217790
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Increase task stack size for PD host command task to 512. The nominal
stack size is 328 / 384, which is pretty close to the edge.
BUG=none
BRANCH=none
TEST=make -j buildall
Change-Id: Ifdf04923b817c832cbb77ba7f61c06a560aec97d
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/217452
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
