Some chips require special operations before flash can be accessed
(read, write, erase), without it the flash operations could be
corrupted. The chip that requires this should enable the
CONFIG_FLASH_SELECT_REQUIRED config, which exposes
EC_FLASH_INFO_SELECT_REQUIRED in flashinfo flags. Before any flash
operations is executed on the chip, EC_CMD_FLASH_SELECT should be issued
to notify the chip to prepare for the flash operations.
BRANCH=none
BUG=b:63685022
TEST=with depended CLs, touchpad interrupt should be disabled when
flashrom is in progress.
CQ-DEPEND=CL:*416548
Change-Id: I96455adbe739d5f924edf382a2752404a7c5ad04
Signed-off-by: Wei-Ning Huang <wnhuang@google.com>
Reviewed-on: https://chromium-review.googlesource.com/582374
Commit-Ready: Wei-Ning Huang <wnhuang@chromium.org>
Tested-by: Wei-Ning Huang <wnhuang@chromium.org>
Reviewed-by: Wei-Ning Huang <wnhuang@chromium.org>
This will officially kill the support for rev0 boards.
The major changes include:
1) Massive GPIO rename/reallocation
2) New power sequencing
3) Reconfigure peripherals (e.g. I2C, SPI, ADC)
4) Drop usb_charger_task
5) Remove lid switch
6) Display BL not driven by PWM
7) Move bmp280 from I2C to SPI
8) Remove SPI flash
9) Some placeholders for follow-up changes.
BUG=b:62640322, b:62269890
BRANCH=none
TEST=build scarlet
Change-Id: Idc0a854a0935089295b67da106ba1b35359f146d
Signed-off-by: Philip Chen <philipchen@google.com>
Reviewed-on: https://chromium-review.googlesource.com/572684
Commit-Ready: Philip Chen <philipchen@chromium.org>
Tested-by: Philip Chen <philipchen@chromium.org>
Reviewed-by: David Schneider <dnschneid@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
100us is hard to measure reliably on poppy side, let's increase to
500us, and widen the range.
BRANCH=none
BUG=b:63818321
TEST=Flash staff and soraka EC, check that pulses are detected
correctly.
Change-Id: I1c29a42c70da0efa0318a619bb83e451b9f168f4
Reviewed-on: https://chromium-review.googlesource.com/581572
Commit-Ready: Nicolas Boichat <drinkcat@chromium.org>
Tested-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
The EC cannot control warm vs cold reset of the chipset using the
SYS_RST_L pin; it's just a reset request. This commit changes the
behaviour of chipset_reset to assert SYS_RST_L regardless if a cold or a
warm reset is requested.
BUG=b:63508740
BRANCH=None
TEST=make -j buildall; Flash a modified image on npcx7_evb, verify that
no panics or asserts are hit.
Change-Id: Idfd6f556bf909c7df4e8bd50a79b60719478cde7
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/585573
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
If we have no ISR for an enabled GPIO interrupt (eg. for a UART GPIO
interrupt that wakes from low-power idle) then clear it, to avoid
interrupt storm.
BUG=b:63958831
BRANCH=eve
TEST=Verify we can repeatedly wake from low-power idle on eve by hitting
'enter' on the EC console.
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: I6a01cae33e3bf1a3b5b42c0389c4613dc1cb9b7d
Reviewed-on: https://chromium-review.googlesource.com/584011
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Duncan Laurie <dlaurie@google.com>
Reviewed-by: Mulin Chao <mlchao@nuvoton.com>
This commit adds the GPIOs for determining the GPIOs.
Additionally, this adds some alternate functions for the PWM and ADC
pins.
BUG=b:63508740
BRANCH=None
TEST=Flash modified version on EVB and verify that it boots without any
panics or assertions.
Change-Id: I34161ad075ad88f940a21c2ee94219ea6a878d63
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/584052
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
Currently sweetberry hits an integer truncation issue
at 2.4 ohm when uA per div goes below 1. We can use 100ths
of a uA as the current per div scale.
BRANCH=None
BUG=chromium:608039
TEST=log from sweetberry with 10 ohm config.
Signed-off-by: Nick Sanders <nsanders@chromium.org>
Change-Id: I9e9216230329483fd0bfcb44ce23cd15bae864b3
Reviewed-on: https://chromium-review.googlesource.com/577051
Commit-Ready: Nick Sanders <nsanders@chromium.org>
Tested-by: Nick Sanders <nsanders@chromium.org>
Reviewed-by: Nick Sanders <nsanders@chromium.org>
In the recent change to flash_ec, there was a problem with they way that
common_stm32_VARS was defined. This commit fixes the issue.
BUG=chromium:740026
BRANCH=potentially some FW branches.
TEST=Using servo_v2, flash elm.
Change-Id: I2e14f1f45525f494d9912b420d36d02d89b9dc5a
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/583540
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
EC currently uses a host command from kernel to enter s0ix.
This patch waits for the SLP_S0 interrupt to come after receiving
the host command before entering S0ix.
On the exit path, the SLP_S0 interrupt directly triggers the
exit rather than waiting for the host command.
BRANCH=none
BUG=b:37443151
TEST=check in EC logs for SLP_S0 entry and powerindebug output,
check suspend_stress_test on reef and soraka works fine,
make -j8 buildall runs fine
Change-Id: Ie5507b7a1e723532f07bc0671c2abd364f6224a2
Signed-off-by: Subramony Sesha <subramony.sesha@intel.com>
Signed-off-by: Archana Patni <archana.patni@intel.com>
Signed-off-by: Jenny TC <jenny.tc@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/513705
Commit-Ready: Jenny Tc <jenny.tc@intel.com>
Tested-by: Jenny Tc <jenny.tc@intel.com>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
1) Don't assert prochot by default, this signal has an inverter
and driving it high is asserting prochot until it gets deasserted
during S3->S0 transition.
2) Clear PMIC power source interrupts in pmic_init in case they
were inadvertently set by misbehaving PMIC. The BATTSHORT event
that matters for PROCHOT assertion is masked so it should never
be set anyway, but I found a system where it was set. This register
does not seem to get cleared by an LDO reset so PROCHOT was stuck on
until battery cutoff.
BUG=b:63913242
BRANCH=eve
TEST=manual testing on Eve unit
Change-Id: I5c7f7ca528160972f65bd714deea98357fa43a53
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://chromium-review.googlesource.com/579904
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
The original _CHIPNAME for npcx ec in the openocd configuration file
is npcx5m5g. As we introduce more npcx ec SKUs, it is not appropriate
to keep using this name. This CL modifies the _CHIPNAME to a generic
name(npcx_ec).
BRANCH=none
BUG=none
TEST=./util/flash_ec --board=npcx7_evb; check the openocd log and make
sure the _CHIPNAME is npcx_ec now.
Signed-off-by: CHLin <CHLIN56@nuvoton.com>
Change-Id: I49d298de1e43ac29f3e5535702595ee27225ac23
Signed-off-by: CHLin <CHLIN56@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/576604
Commit-Ready: Jun Lin <riverq@gmail.com>
Tested-by: Jun Lin <riverq@gmail.com>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Support a level shifter for both 1.8v and 3.3v
uarts on SBU.
BRANCH=None
BUG=b:35849284
TEST=ran on tigertail, both 1.8v and 3.3v detected.
Change-Id: I76d545b582c6ed15086941513d5de4cd6783ac16
Signed-off-by: Nick Sanders <nsanders@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/575595
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
hwtimer ticks at 8 * 32768 Hz rather than 250 KHz, so adjust our timing
appropriately. Also ensure that udelay() will delay for at least the
requested time, taking into account our timer precision.
BUG=b:63858553
TEST=Generate square wave with 1000us udelay between GPIO edge toggle,
verify period is 1000us + code overhead. Also verify timer behavior on
overflow with 'forcetime' command. Also verify accuracy of system clock
to 0.2% with `timerinfo` and a stopwatch.
BRANCH=None
Change-Id: I5da41bd7250db87de5143cc54ebd0bb750fb7003
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/578551
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Tigertail Rev. C has a button, we'll use it to toggle
between A, B and off.
BRANCH=None
BUG=b:35849284
TEST=ran on tigertail w/rework, mux muxed.
Signed-off-by: Nick Sanders <nsanders@chromium.org>
Change-Id: I2a2a9ce0ba713c47e6f1196fac62a3804a78bf94
Reviewed-on: https://chromium-review.googlesource.com/575893
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Pass in recovery button press/release information to AP using MKBP
button driver.
BUG=b:63893483
BRANCH=None
TEST=Behavior verified by Shelley.
Change-Id: I7a6e50ec8595d99327b5fc8e822bf762e0ce13e0
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/580539
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Board rev0 will lose VBAT on power cycle and therefore
cannot successfully save the reset flag state.
Implement workaround that will allow these boards to continue to
work for FAFT testing by indicating to the skylake chipset power code
that it should skip the PMIC reset when doing 'reboot ap-off'.
BUG=b:63889675
BRANCH=None
TEST=None
Change-Id: Ie79053e2e52a3a9efd9cd864808af7214989602e
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/579666
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Using zero to represent success make it cleaner when processing return
values of this function. Also, let's report different failures using
different error values.
Note that nobody checks this function's return value yet.
BRANCH=cr50
BUG=b:63686091
TEST=none
Change-Id: If25d30e637701f6c37f3ce75e5a5d5315e0e86e9
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/579583
Reviewed-by: Marius Schilder <mschilder@chromium.org>
Reviewed-by: Nick Sanders <nsanders@chromium.org>
Unique device ID register (96 bits) is at a different place on STM32F4
compared to other STM32.
BUG=none
BRANCH=none
TEST=Using board_read_serial() from hammer/board.c in
sweetberry/board.c, confirmed that we can extract and assign a unique
USB serial number.
Change-Id: Idb257f0f20422482c729a2b97b4b16ee231ca4d9
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/579575
Commit-Ready: Gwendal Grignou <gwendal@google.com>
Tested-by: Gwendal Grignou <gwendal@google.com>
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
This adds the CCD configuration module, and the console commands to
control it. It is not wired up to any of the CCD capabilities; that's
coming in the next CL.
Briefly:
* CCD configuration is persistently stored in nvmem_vars. Use ccdinfo to
print it.
* CCD can be Locked, Unlocked (some capabilities), or Opened
(all capabilities), using the ccdlock / ccdunlock / ccdopen commands.
* CCD config can be restricted by setting a password via ccdpass.
* Individual config capabilities can be set via ccdset. Some of those will
be used to gate access to things like write protect and UARTs. Others
affect the requirements for ccdunlock / ccdopen (for example, is physical
presenc required).
* The entire config can be reset via ccdreset. If only unlocked, config
that is restricted to Opened is not reset.
* If CR50_DEV=1, ccdoops will force-reset and open the config.
See go/cr50-ccd-wp for more information.
BUG=b:62537474
BRANCH=none
TEST=manual with CR50_DEV=1 build
gpioget # make sure GPIO_BATT_PRES_L=0
ccdlock # lock, because CR50_DEV=1 builds start unlocked
ccdinfo # locked, flags=0, all capabilities default
ccdpass # access denied (we're locked)
ccdreset # access denied
ccdset flashap always # access denied
ccdunlock
ccdinfo # unlocked
ccdpass foo
ccdinfo # flags=2 (password set when unlocked)
ccdset flashap always # access denied
ccdset uartectx unlesslocked
ccdinfo # yes, uartectx permission changed
ccdlock
ccdunlock # fails without password
ccdunlock bar # wrong password
ccdunlock foo # busy
(wait 3 sec)
ccdunlock foo
ccdreset
ccdinfo # no password, flags 0, capabilities all default
ccdopen # requires physical presence; tap power or use 'pp'
ccdset uartectx unlesslocked
ccdset batterybypasspp ifopened
ccdpass baz
ccdinfo # password set, flag 0, ccdset changes worked
ccdunlock
ccdreset
ccdinfo # uartectx back to ifopened, password still set
ccdopen baz # still requires physical presence
ccdset opennolongpp always
ccdlock
ccdopen baz # no pp required
ccdset unlocknoshortpp unlesslocked
ccdlock
ccdopen baz # short pp sequence required (3 taps)
ccdlock
ccdunlock baz # short pp sequence required
ccdopen baz # pp not required
ccdset unlocknoshortpp always
ccdlock
testlab open # access denied
testlab enable # access denied
ccdunlock baz
testlab open # access denied
testlab enable # access denied
ccdopen baz
testlab enable # requires short pp
ccdinfo # flags 1
ccdreset
ccdinfo # no password, flags=1, caps all default
ccdlock
testlab open
ccdinfo # opened
testlab disable # requires short pp; let it time out
ccdinfo # still opened, flags=1
ccdlock
ccdoops # backdoor in CR50_DEV images to force-reset CCD
ccdinfo # opened, flags=0, all defaults (yes, oops wipes out testlab)
ccdreset rma
ccdinfo # flags = 0x400000, everything but Cr50FullConsole always
ccdreset # back to flags=0, all default
Change-Id: I24e8d8f361874671e6e94f27492ae00db919bea9
Reviewed-on: https://chromium-review.googlesource.com/569439
Commit-Ready: Randall Spangler <rspangler@chromium.org>
Tested-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Disable reporting of EC events to the linux kernel that are not used
by kevin's kernel.
BRANCH=none
BUG=chromium:637061
TEST=make buildall passes, lid close puts AP into suspend, lid open
turns on display
Change-Id: I7841294aec0853f4820a262ec14e8ad6037e1060
Signed-off-by: Nick Vaccaro <nvaccaro@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/503536
Reviewed-by: Shawn N <shawnn@chromium.org>
When compiling target tests for a board that defines
CONFIG_CHIPSET_CANNONLAKE, the build would fail due to the chipset code
being built without a chipset task. This commit removes the Cannonlake
chipset code when building a test that does not have a chipset task (and
use Cannonlake).
BUG=None
BRANCH=None
TEST=make -j BOARD=zoombini tests; verify that build succeeds.
Change-Id: I15a5729db64314a8d6566be879f7c356ffa95725
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/578316
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
This will be used as part of case closed debugging configuration.
Currently, this only adds the state machine, and a test command which
is available when CR50_DEV=1. It also adds a new sleep mask flag for
physical presence detect, instead of oveloading FORCE_NO_DSLEEP.
The physical presence state machine supports both short (tap 5 times
in 15 seconds) and long (short, followed by 4 more taps 1-5 minutes
apart) sequences. It will call a callback function at the end of the
sequence, so that multiple things can each request physical presence
in turn. This will be used by ccdopen / ccdunlock / testlab commands
for CCD V1.
Eventually, CCD config will replace the unlock sequence handling in
wp.c. But for now, we don't touch that.
See go/cr50-ccd-wp for more information.
BUG=b:62537474
BRANCH=none
TEST=manual
Short sequence:
pp short
pp
pp
pp # See "Physical presence good"
Timeout
pp short
pp # 15 sec later, get timeout error
Long sequence:
pp long
pp
pp
pp
(wait 2 sec)
pp
(wait 2 sec)
pp # See "PP good"
Long sequence, presses too fast:
pp long
pp
pp
pp
pp # See "PP L too soon"
(wait 2 sec)
pp
(wait 2 sec)
pp # See "Physical presence good"
Abort:
pp short
pp abort # See "Physical presence aborted"
Change-Id: I09da81ad11d328e7d7740c3fe838a5f67d7b8708
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/568796
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
This commit adds support for the virtual wire signals over eSPI.
Additionally, the SLP_S0_L signal is added for the board and some minor
changes are made to some GPIOs.
BUG=None
BRANCH=None
TEST=flash zoombini image on npcx7 EVB with some modifications. Verify
no panics or asserts are hit.
Change-Id: I6ada270b3e3fc7e24b28a8da6ee9dcde707414fc
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/577054
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
Instead of having to pass in both the board and the arch used there
(which might be complicated in the light of different ECs with different
arches), allow passing in the board and a set of cross compilers.
The core/*/build.mk then pick the compiler that is responsible for them.
The current method works just the same: If you've already set
CROSS_COMPILE, no override happens. If you set neither CROSS_COMPILE nor
CROSS_COMPILE_$arch, the same default as before this CL is set.
BUG=none
BRANCH=none
TEST=emerge-{samus,kevin} chromeos-ec behave reasonably with adapted
ebuild
Change-Id: Icf1866f296412dd92ecfe134394224c49f7c3df5
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://chromium-review.googlesource.com/549344
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Stefan Reinauer <reinauer@google.com>
RCIN# signal is known to not work properly for performing a warm reset
when the CPU is in a bad state. This results in the common key combo
(Alt-Volup-r) not working to reset the host. Thus, use SYS_RESET
signal instead to trigger both cold and warm chipset reset.
BUG=chromium:721853
BRANCH=None
TEST=make -j buildall
Change-Id: I38663db96767d0aa03cd1aea0fe2a0cc5b771cd2
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/575947
Reviewed-by: Duncan Laurie <dlaurie@google.com>
In deep S3, SLP_SUS# goes low which results in power to base being
cut. For such cases, PMIC needs to be configured so that it keeps the
power to base up. Use VREN register to keep PP5000_A rail enabled in
deep S3.
BUG=b:63251418
BRANCH=None
TEST=make -j buildall. Verified that wake from base works in deep S3.
Change-Id: Ice3ba56f1a7e52275c3afa332c29b5b252dded4d
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/574619
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
We need to add __keep to the USB descriptors, otherwise they
get thrown away.
Also, for some reason the optimized RWSIG task uses a little bit
more stack space, so account for that:
1 RWSIG 00000000 0.264350 1096/2048
BRANCH=none
BUG=b:63610290
TEST=make BOARD=hammer -j
make newsizes
build/hammer/RO/ec.RO.flat shrank by 2052 bytes: (37336 to 35284)
build/hammer/RW/ec.RW.flat shrank by 3172 bytes: (50508 to 47336)
Flash hammer, touchpad, keyboard, update all still work fine.
Change-Id: I39ffd320dae883596ce481efc4adec6e3c23000b
Reviewed-on: https://chromium-review.googlesource.com/567909
Commit-Ready: Nicolas Boichat <drinkcat@chromium.org>
Tested-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
With the bd99954 charger we do not need to discharge when full,
so remove this config option and the setting of 94% for "full"
battery.
Note that this only affects the battery reporting state, the
EVT systems (board <= 4) will still discharge when full (in order
to prevent the charger noise) but they will now indicate that they
are discharging in this state instead of appearing full.
Newer boards (version > 4) will behave as expected.
This is a compile time option so it isn't something I can easily
support old boards with, but I think it is more important to do
the right thing for new boards.
BUG=b:35585628
BRANCH=eve
TEST=test charge behavior when full on board version 6
Change-Id: I3dd46ae305107b17b3bf8e3ce71578d3400b0f79
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://chromium-review.googlesource.com/573091
Reviewed-by: Shawn N <shawnn@chromium.org>
Eve does not use PECI so disable it and remove from the resulting binary.
BUG=b:35581264
BRANCH=eve
TEST=build EC for Eve and ensure peci module is not included
Change-Id: Ie87d789226b2b5f2162ea96cb001a5cb62359213
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://chromium-review.googlesource.com/573083
Reviewed-by: Shawn N <shawnn@chromium.org>
This CL adds CHIP_VARIANT_NPCX7M6G to support another npcx7 ec SKU.
Please note that the default setting in npcx7_evb is npcx7m6f.
For the EVB using the 128-pins EC package, please change CHIP_VARIANT
from npcx7m6f to npcx7m6g in build.mk.
BRANCH=none
BUG=none
TEST=No build errors for make buildall; Set CHIP_VARIANT=npcx7m6g in
board/npcx7_evb/build.mk; Build the image and test on EVB.
Change-Id: I2f857e4f6524eab45930bac3cc209409d4a53ee8
Signed-off-by: CHLin <CHLIN56@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/569320
Commit-Ready: Jun Lin <riverq@gmail.com>
Tested-by: Jun Lin <riverq@gmail.com>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Mulin Chao <mlchao@nuvoton.com>
Current LED color changes are abrupt. This CL adds a new function
which steps from one color (some RGB combo) to another gradually. When
the new or old color is white, then precomputed steps computed from
HSI space are used. Other transisions involving either just red/green
use linear steps computed dynamially based on the total change.
This CL also creates a new task for the LED code so that the color
transitions won't hold off other hook tasks for too long a period of
time. Changed the LED tick time to be 500 msec as it's no longer tied
to the hook tick.
BUG=b:35584895
BRANCH=eve
TEST=Using EC console command 'battfake', changed reported battery
charge level and verified that the LED patterns still work as
expected. In addition, had debug code which printed to the console
what the R, G, B duty cycle levels were for each transition and
verified the expected values were achieved. Visually compared version
with transitions to the previous version which changed abruptly.
Change-Id: I4e7c19556db9ed6037f2afa05cf348d19aeb18bb
Signed-off-by: Scott Collyer <scollyer@google.com>
Reviewed-on: https://chromium-review.googlesource.com/562543
Commit-Ready: Scott Collyer <scollyer@chromium.org>
Tested-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
In particular, highlight more clearly cr50/common code differences,
describe update over USB state machine, and common code commands.
Also, replace all cr50/CR50 instances with Cr50.
BRANCH=none
BUG=b:36375666
TEST=~/chromium/src/tools/md_browser/md_browser.py -d docs
Change-Id: I45e26a87c3455e1c67be186b403b1d4c4acade91
Reviewed-on: https://chromium-review.googlesource.com/558537
Commit-Ready: Nicolas Boichat <drinkcat@chromium.org>
Tested-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
