Record commands used previously and use up/down arrow key to navigate in
the command history.
Also removed the command '.' of repeating last command as we can use up
arrow key now.
Also changed the behaviour of uart_write_char() to be blocking on
transmit FIFO full, so that we do not lose echoed character and do not
need to flush.
BUG=chrome-os-partner:7815
TEST=Type 'help' and enter. Then type 'aaaa' and up arrow key, should
show 'help', and pressing enter prints help.
Type 'hellp' and enter. Then type 'aaaaaa' and up arrow key, should show
'hellp'. Should be able to use left/right arrow key and backspace to
correct it to 'help', and pressing enter prints help.
Type 'help' and enter. Then type 'aaa', up arrow key, and down arrow
key. Should show 'aaa'.
Change-Id: I65c615d61bf63acb31bea329aa91a3202d4db0ad
- Add #ifdef CONFIG_TEMP_SENSOR before #include'ing temp_sensor.h
which actually requires temp_sensor_id to be defined.
Revert the forward declare used earlier since it is not the
correct solution in this case.
- Add #ifdef CONFIG_CHARGER before calling charger_init()
Signed-off-by: David Hendricks <dhendrix@chromium.org>
BUG=None
TEST=compiled on both BDS and Discovery
Change-Id: I60b7e4ba91eb958b3ad724cc9ffa9a12fe9c3a71
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=chrome-os-partner:7906
TEST=from ec console, 'x86power s0' should power the system on reliably.
Change-Id: Idebfc8b4e86587b540934d245649f912ccb4aa95
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=chrome-os-partner:7488
TEST=type things into the x86 console UART; should appear on the u-boot prompt
Change-Id: I75fd225842c03d11d79280fb7453ad37695279e3
Current makefile takes CONFIG_* flags from $(CHIP)/config.h . This
CL adds $(BOARD)/board.h and a sample charger config flag.
Signed-off-by: Rong Chang <rongchang@google.com>
BUG=chrome-os-partner:7917
TEST=build bds,link board and check warning and error messages.
Change-Id: I1f13d24da6b18c014f40f941ef7245487e5ccc81
This is a trivial patch to fix compilation for boards that are not
based on LM4 (e.g. Discovery).
Signed-off-by: David Hendricks <dhendrix@chromium.org>
TEST=Compiled for Discovery
BUG=None
Change-Id: Ia1f29c61ff4a1f65fe65c43a8e58def7d1217ab2
When run with BOOT0=1 and BOOT1=0, the STM32L enters a system monitor
which allows flashing over the serial port (USART1 pins PA9 and PA10).
Implement commands to flash and run a program from a linux Host.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BUG=None
TEST=on a serial port connected to Discovery board pins PA9 and PA10,
run manually the various tools commands.
Change-Id: I42f95ed50a56d82d728989149b3e47210af9dc96
F1-F7: swap scancode of set 1 and set 2
F8-F10: change from (F9, F10, F11)
arrow keys: swap scancode of set 1 and set 2
Search key: change from CapsLock key
BUG=none
TEST=tested on bds.
Change-Id: Ifb8e715a2cd5f8ea174f7c38647c5ce550382615
Refactor board/chip-specific code into corresponding directories.
Add support of the four I2C temp sensor in Link.
Use table lookup to handle different types of temperature sensors.
BUG=chrome-os-partner:7527
TEST=Correctly read EC internal temperature on bds.
Compile for link succeeded.
Change-Id: I694cfa54e1545798d877fafdf18c5585ab5f03e2
Original code tests SND bit, but it is not reliable to indicate the
SERIRQ frame has been sent out because the EC always clears it
immediately. Unfortunately the SIRQRIS is always asserted in
continuous mode so that we cannot rely on it.
So, the udelay(4us) method is the best way we can use now.
Note: the quiet mode? Forget it. My EC never sends out further frames
after the first has been sent.
BUG=none
TEST=on bds board.
Change-Id: Ica79b463f3dbe7435fe75f3db4cef00ad7ad5ec0
The GPIO console commands are common to all platform, let's push them in
the common code.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BUG=None
TEST=make BOARD=link && make BOARD=bds && make BOARD=discovery
on BDS console, try gpioget command.
Change-Id: I26e6d26b8d661e78b80d5d5f665e81f4daef0c11
No interrupt support yet.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BUG=None
TEST=on Discovery EC console, using "gpioget" and "gpioset" commands
check we can switch the LED and read the button state.
Change-Id: I01294643d3df070a535dab5a6be02c296487fca5
Allow to display the verbose command lines even when building the test
programs.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BUG=None
TEST="make tests" with and without V=1
Change-Id: Ib1195c7e069d7823c2eb7b2311bd5f3c6cd6c835
There is no host command yet and the "hello" test is not using it.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BUG=None
TEST=make tests BOARD=discovery && make tests BOARD=link
Change-Id: Ib7f49f8e38270a8c537e352396b1966abc801511
Add a final wait to ensure the clock is ready before returning.
Setup the Flash according to the manual recommendations.
The low-speed oscillator and RTC are now done in the system module with
other RTC inits.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BUG=None
TEST=run the EC firmware on the Discovery and manually exercise various
path through the console.
Change-Id: I4e6149b6fd55c8fc72dbdf6bfc4a10665e0246bd
When the flash base address is not zero (e.g. STM32L chip), the current
image index is wrongly computed.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BUG=None
TEST=check it compiles for all boards, run on Discovery board and see
proper value.
Change-Id: I06f5508cdffce6d754bd93e870d64087d299c9c7
Allow to get proper reset reason.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BUG=None
TEST=On the discovery board, try the reset button, the "reboot" command
and a blocking wait, and see the proper reset reason displayed.
Initialize the scratchpad register with "setscratchpad" command and
check we can read it back after reboot.
Change-Id: I1fe1eec4987f7c9816454de4fd3b4addda4ad05a
Use the Independant WatchDog.
The Window WatchDog would provide a nice early warning interrupt before
actually rebooting but the max period (128 ms) is probably too short for
our purpose.
The full GPIO support and the reboot cause detection will be implemented
in later steps.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BUG=None
TEST=on Discovery board, do blocking waits of 500ms and 1500ms, and
check the latter reboots the platform and the former does not.
Change-Id: I26e4d8b26b733269b7811cc3b3a09daf98ea364a
The problem comes from the different assumption of interrupt mode in EC and
the PCH. The PCH assumes IRQ1 is edge-triggered and triggered at a rising edge.
However, the auto-IRQ functino of EC is level-triggered and uses low-active to
assert an IRQ. This makes the deadlock so that the kernel never gets an
interrupt until a byte is manually pulled from host.
So, the solution is manually firing an IRQ_1 to host after EC puts a byte to
port 0x60. Note that the auto IRQ needs to be disabled in order to avoid
the interference with manual IRQ generation.
This CL also moves chip specific code to lm4/lpc.c and handle some minor
keyboard commands.
BUG=none
TEST=on hacked baord.
Change-Id: Ib57f5a4d749cb019e4c3c00da110054c4f335c7b
The ADC input pin was always configured as BDS. Modified it to configure
the correct pin.
BUG=none
TEST=On Link, "rw 0x4002451C" show 0xff instead of 0xf7.
Change-Id: I1efd5cd59ad65f55cd673529afa6153add63ecac
Refactor ADC code and move board/chip-specific part to corresponding
directories.
Implement function and console command to read Link charger current.
BUG=chrome-os-partner:7527
TEST=Read EC temperature and POT input on BDS.
Change-Id: I7fafd310ea49d9b2781f10c3453f5488da29a08a
As the STM32L doesn't have any 32-bit timer, we use 2 chained 16-bit
counters to emulate a 32-bit one :
* TIM2 is the MSB half-word (Slave timer)
* TIM3 is the LSB half-word (Master time)
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BUG=None
TEST=run timer_calib and timer_dos on the Discovery board, and check
waitms and gettime console functions against wall clock.
Change-Id: I8917207384d967fd87321797856e3d58b237f837
Force starting the transmission immediatly when ordered by the UART
buffering layer.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BUG=None
TEST=run EC console on Discovery and measure the timestamp of each
characters on the serial port.
Change-Id: I036a3fa0a60baa27de4ba0ceb386841a429535ac
The TX empty interrupt needs an actual write to DR to be cleared.
So, we de-activate it before filling the TX buffer to ensure the
interrupt won't fire after the last write.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BUG=None
TEST=run EC console along with a lower priority task on Discovery board,
and check the task is scheduled as expected.
Change-Id: I56c33c6dd7ccfd238fd9d5910780d12945467010
Handle left and right arrow key to move cursor around.
Other escape sequences are still ignored.
BUG=chrome-os-partner:7865
TEST=type some text and use left and right arrow key. Cursor should
move.
type 'hellp', left key, and backspace. Should show 'help' and hitting
enter prints help.
type 'hexp', left key, backspace, 'l'. Should show 'help and hitting
enter prints help.
Change-Id: If9ac4504c56f023f824175de2daf565ce72d4560
simple UART driver to get the serial console on the USART3.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BUG=None
TEST=run on Discovery board and check we get the first message on the
UART and the console is echoing the characters.
Change-Id: Id85999a5ddbd75804e9317a1b8c2fd4afb89eb38
Expand the macros before building the priority variable name in order to
ensure we have a valid name.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BUG=None
TEST=check manually preprocessor expansion for several combinations.
Change-Id: I926821d42c966ac674e7d24254c9f22779f93ca2
Run from internal clock at 16Mhz, but enable PLL to get a better
precision.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BUG=None
TEST=run on discovery board and check software is still alive after
clock initialization.
Change-Id: I8425482825015adf96c30e67a9320d0df2f4f2b7
Define IRQs and register addresses for basic peripherals to do STM32L
bringup.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BUG=None
TEST=mostly untested, there should be typos over there...
Change-Id: Ib6d90436e25be74f724112619cdae7acccfaf085
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=chrome-os-partner:7718
TEST=manual
// enable fan
gpioset enable_vs 1
// set fan speed to 7000
fanset 7000
faninfo
// should report duty cycle about 65%, fan speed about 7000 rpm, status = 2
fanset 4000
faninfo
// should report duty cycle about 25%, fan speed about 4000 rpm, status = 2
fanset -1
// should report duty cycle 100%, fan speed about 8800 rpm, status = 3
Change-Id: Ib7d7df14ad240811e6e79bc1fc4ecf0e6841c334
I keep hitting the darn arrow keys. Until we can do something more
elegant like a real command history, this will at least keep me from
corrupting the display and input buffer.
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=none
TEST=type 'help' and some arrow keys, then enter. Should print help, not an error.
Change-Id: Idb552e9c22876fc2dc1f349f0038e94048f00aa7
To assist in x86 chipset bringup, there are 4 GPIOs we weren't
printing state transitions for.
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=none
TEST=reboot; should see state transitions in the high nibble (mask 0xF000), for example:
[x86 power state 1 = S5, in 0x2001]
[x86 power state 1 = S5, in 0x3001]
[x86 power state 1 = S5, in 0x7001]
Change-Id: I0527e4698425d845e8b08589e89592f95d8bee41
Keyboard scanning was not properly configuring GPIOs on link. Among
the problems, it was setting GPIO level then direction, when it needs
to set direction first. Also fixed this in gpio pre-init.
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=chrome-os-partner:7761
TEST=1) press keys on keyboard; see keyboard state change on console
2) 'gpioget PCH_PWRBTNn' should report 1 after boot, not 0
Change-Id: I54010aa6eef1de4822574f964de369b459ee6d0f
