We need to change PLL settings if host apply eSPI operating
frequency higher than 50MHz, because FND clock is required
to be higher than half of operating frequency.
BRANCH=none
BUG=b:70537592
TEST=Change PLL succeed with chip select is low.
Change-Id: Ieba62f33ed024aed7a8e7f4cc48b1398ed781170
Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
Reviewed-on: https://chromium-review.googlesource.com/817717
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Waiting out HOOK_TICK_INTERVAL for a non-interrupt power signal can
cause boot delays of up to 500ms, which can lead to dropped host
commands and other bad side effects. Poll IN_PGOOD_S0 when sequencing up
to reduce the minimum delay to 5ms.
BUG=b:70390178
BRANCH=None
TEST=Run "reboot" on EC console, check timestamp of S0 transition print:
[0.332974 power state 3 = S0, in 0x000f]
Compare to pre-patch:
[0.692799 power state 3 = S0, in 0x000f]
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: I4b8891f75d896b1ae47d8f12ed07581f20b6ae7c
Reviewed-on: https://chromium-review.googlesource.com/822594
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Philip Chen <philipchen@chromium.org>
Add the flags for board_deep_sleep_allowed and
board_detect_ap_with_tpm_rst.
BUG=b:35647982
BRANCH=cr50
TEST=run firmware_DeepCr50SleepStress on electro. Make sure Bob can
still detect the AP state and doesn't enter deep sleep
Change-Id: I39e45f6eacc1cbdcb3ab1caaecd0836f8a2c073a
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/699294
Reviewed-by: Randall Spangler <rspangler@chromium.org>
In order to make a single hammer image support both base with and
without keyboard backlight. We need a way to dynamically determine if
backlight is present, and send the correct HID descriptors. This is done
through declaring two HID descriptors and return the correct one
depending on whether or not the backlight is present.
BRANCH=none
BUG=b:67722756
TEST=On reworked board with pull-down on backlight pin,
USB descriptor has backlight HID report descriptor, and is
functional.
TEST=On old board with both pull-up and pull-down (equivalent to
having pull-up only, i.e. no backlight)
USB descriptor does not have backlight HID report descriptor
Change-Id: Ie3eac9b3d4cd749308ccfb96a7db469701f9793b
Signed-off-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/770600
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
In some cases, we want to be able to dynamically modify a few bytes
in the USB descriptor (in our case, length of referenced items),
but it could also be other things like flags.
These 2 new functions allow to keep all the USB descriptor in flash, and
modify these few bytes before writing them in the USB buffer.
BRANCH=none
BUG=b:37447752
TEST=Flash hammer, USB descriptors are valid.
Change-Id: I8624255fa43f52a0aaa21d20e963f3974f236912
Signed-off-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/771057
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Pull-down means backlight is present, pull-up means backlight
is absent.
After detection, we still apply internal pull-down on the GPIO,
to make sure old boards with both pull-up and pull-down stuffed
do not always keep backlight on.
BRANCH=none
BUG=b:67722756
TEST=On reworked board with pull-down on backlight pin,
backlight works, and "Backlight present" shown in console.
TEST=On old board with both pull-up and pull-down, backlight is
off by default, and "Backlight not present" shown in console.
Change-Id: I6988c6ef8f4d155a08967db34f72d7ea4c835306
Signed-off-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/538458
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
This commit enables the interrupt handlers for the SN5S330 for both
meowth and zoombini. Additionally, on meowth the interrupt line is
shared between the TCPC and the PPC, therefore we have to check both
parts when an interrupt occurs. The TCPC will be serviced first,
however when reporting the alert status, we need to actually read the
alert registers since we cannot simply use the level of the interrupt
line as the PPC may be asserting an interrupt as well.
The PPC is currently setup to interrupt on PP1 overcurrent situations.
The EC will then notify the AP of the overcurrent status by simply
setting the overcurrent GPIOs.
BUG=b:69139844
BRANCH=None
TEST=Flash meowth; Verify EC boots up okay.
TEST=Flash zoombini; Verify EC boots up okay. Verify can still perform
PD negotiation.
CQ-DEPEND=CL:797936
Change-Id: I43445799088711de9d5ed488abc945e6f1084918
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/797937
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
Right now, the only events that are unmasked by default are overcurrent
conditions on PP1. This commit adds a simple interrupt handler and
introduces a board specific callback when the overcurrent status changes
on a port. This way, a board can take whatever action it desires with
the notification.
BUG=b:69139844
BRANCH=None
TEST=Flash zoombini with SN5S330 stuffed. Verify that board boots okay.
TEST=With some extra code to setup the interrupt handler, attempt to
exceed the current limit set, verify that interrupt handler is called.
Reduce the current pulled to under the current limit, verify that the
condition is no longer present.
CQ-DEPEND=CL:797937
Change-Id: Id3321c5703f9608da895be0ed5841f2fb76e734e
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/797936
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
Add delay of 1ms with stable power before asserting PWR_GOOD.
CDX03 seems to work ok with and without the delay, but since it
is a requirement in the electrical data sheet, better add it.
Also removed an unnecessary header while I was here.
BUG=b:70350333
BRANCH=none
TEST=power CDX03 on and off
Change-Id: I9f2f94bfb907ac9e88f350e72286061a97ebfe3d
Signed-off-by: Edward Hill <ecgh@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/816063
Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Also updated the basic parameters (design_cap, ichg_term, and v_empty)
based on the characterization result.
BUG=b:69634899
CQ-DEPEND=CL:813038
BRANCH=none
TEST=manually test on Scarlet rev2, 'battery' command shows reasonable
reading no matter is_ez_config is set as 0 or not.
Change-Id: I55889efe39cc43e38c0285d298bcf39f0a4e49a1
Signed-off-by: Philip Chen <philipchen@google.com>
Reviewed-on: https://chromium-review.googlesource.com/812481
Commit-Ready: Philip Chen <philipchen@chromium.org>
Tested-by: Philip Chen <philipchen@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
We've been using the basic configuration (EZ config) to
initialize max17055.
It doesn't require battery profile, but the accuracy of fuel gauge
is not the best.
With a full battery profile in place, we should extend our driver
to import the battery profile for advanced config.
It should boost the accuracy.
BUG=b:69634899
CQ-DEPEND=CL:812481
BRANCH=none
TEST=manually test on Scarlet rev2, 'battery' command shows reasonable
reading no matter is_ez_config is set as 0 or not.
Change-Id: Iaea2d3e20f5de4207a86d4fff5f1561aaba4d362
Signed-off-by: Philip Chen <philipchen@google.com>
Reviewed-on: https://chromium-review.googlesource.com/813038
Commit-Ready: Philip Chen <philipchen@chromium.org>
Tested-by: Philip Chen <philipchen@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
It is beneficial to have the 'major' version number component advanced
with every major Cr50 code release: this will allow to use the 'minor'
version number component when it is necessary to release a bug fix or
a small addition to the current release.
BRANCH=cr50
BUG=none
TEST=verified proper version number reported by 'version' command
Change-Id: Ie87a2b676b59b46be243fa6367571a1d0877f13d
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/820270
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
For debug, in common code let's log the watchdog PC
and task id as our SW panic params.
BUG=chromium:790006
BRANCH=none
TEST=manually test scarlet rev2 from a1-a3, b1-b2:
(a1) Add 'while(1);' in button ISR
(a2) Boot and press the button
(a3) When watchdog is triggeried, check with 'panicinfo'
that saved R5 is the PC for button ISR.
(b1) 'crash watchdog' in EC console
(b2) Check with 'panicinfo' that CONSOLE task id is saved in
EXCEPTION and PC is saved in R5.
Change-Id: I64d2fcf594dd24b0951e002ab8e80ebcac2d1def
Signed-off-by: Philip Chen <philipchen@google.com>
Reviewed-on: https://chromium-review.googlesource.com/803618
Commit-Ready: Philip Chen <philipchen@chromium.org>
Tested-by: Philip Chen <philipchen@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
The blinking LED indicates that debug mode is active.
BUG=b:69981636
TEST=Press VolUp + VolDown for 10s to enter debug mode
=> charging LED blinks
=> stops blinking after user action or timeout
test different cases:
- fully charged battery, connected to power
- fully charged battery, not connected to power
- partially discharged battery, connected to power
- partially discharged battery, not connected to power
BRANCH=none
Change-Id: If7ca06aaf5d1fb4c3df4dfb9e63ca6425002b880
Signed-off-by: Matthias Kaehlcke <mka@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/818496
Reviewed-by: Shawn N <shawnn@chromium.org>
Setting password should be allowed only after the owner logged in for
the first time and before they log out or someone else logs in.
Once any other user but the owner logs in, it should become impossible
to set password until the device is reset.
As proposed here, this would apply to both attempts to set password
through crosh and Cr50 console.
Password handling on Cr50 passes the following states:
- password setting is not allowed after Cr50 reset until an upstart
(as opposed to resume) TPM startup happens, as signalled by the TPM
callback. After the proper TPM reset the state changes to
'POST_RESET_STATE' which means that the device was just
reset/rebooted (not resumed) and no user logged in yet.
- if the owner logs in in this state, the state changes to
'PASSWORD_ALLOWED_STATE'. The owner can open crosh session and set
the password.
- when the owner logs out or any user but the owner logs in, the state
changes to PASSWORD_NOT_ALLOWED_STATE and does not change until TPM
is reset. This makes sure that password can be set only by the owner
and only before anybody else logged in.
Separate changes to the TPM library code make sure that TPM reset is
reported through the platform layer, so that POST_RESET_STATE is
entered.
BRANCH=cr50
BUG=b:67007578
TEST=with the rest of the infrastructure in place verified that
password can be set only when the owner logged in for the first
time before anybody else logs in or the owner logs out.
Change-Id: Ieaa3dc8ff9d2e43ae11151eb31173220f5c75b58
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/804141
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Andrey Pronin <apronin@chromium.org>
us_to_rtcss() could return an invalid value when us approached 1 sec
due to precision loss in the divisor. Change the calculation order to
divide last to eliminate precision loss.
BUG=b:68185182
BRANCH=None
TEST=On scarlet, Verify hw clock closely matches reality w/ low-power idle.
Verify EC doesn't watchdog for 5 hours in S5 / G3 w/ low-power idle. Verify
suspend-stress-test still succeeds to wake device on alarm.
Change-Id: Id40797dd4291e94a54a09bbbdbc1a7f7a00a01b4
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/818332
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Brian Norris <briannorris@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Philip Chen <philipchen@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
This gets the pins set up. Not yet sure if we may need additional
support for the LM3630A or if it will use the generic PWM support.
BUG=b:69379749
TEST=make -j buildall
BRANCH=None
Change-Id: I80a1a10818483666461bf47500e3956880dcc1fc
Signed-off-by: Benjamin Gordon <bmgordon@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/812064
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Let's not allow the user to clear or change CCD password without
specifying the old password.
To keep things simple, two changes are being made:
- do not allow setting password if password is already set
- when clearing the password require user to enter
'clear:<password>' instead of just 'clear'
BRANCH=cr50
BUG=b:70029808
TEST=verified that setting password is possible only if there is no
password set currently, and that invoking 'ccd password
clear:<old password>' indeed clears the password.
Change-Id: I3753c2701e224ef89b25ad68c1b47b54eef9cdb1
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/813098
Reviewed-by: Randall Spangler <rspangler@chromium.org>
stm32f0 / f3 can take up to 40ms to erase a single sector of flash. Also
add a note about instruction fetch being blocked on flash operation
completion.
TEST=`make buildall -j`
BUG=b:70193071
BRANCH=None
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: Icb6c199a975b31f4fa7c73ceb6ad8ec06150abb1
Reviewed-on: https://chromium-review.googlesource.com/815276
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Using FWMP for CCD management requires that FWMP contents could be
read even when the AP is not operational, i.e. before TPM2_Startup
command is issued.
A fix is added to the TPM2 library to allow access to FWMP contents
even if TPM is not used by the AP. With that in mind there is no need
to delay reading FWMP until TPM2_Startup command is issued. With the
console task stack increase FWMP contents can be read directly on the
console task context.
BRANCH=Cr50
BUG=b:62537474
TEST=with TPM patch applied verified that CCD can be opened when AP is
down (i.e. TPM2_Startup command was not issued).
Change-Id: Ibf4325917a512a855fc658edb9e51e4837328f43
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/817896
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
The current console stack size prevents using it for even simpler TPM
library invocations. With this increase it is possible to invoke TPM
NV access API from console commands.
BRANCH=Cr50
BUG=b:62537474
TEST=with the rest of the patches verified that FWMP contents can be
read from a console command.
shmem console command output shows 6616 bytes of free SRAM space
when in prod mode and 6624 bytes when in dev mode.
Change-Id: I177af1abde422dab0a9fdb0f4619eaf0ffefa9f6
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/817895
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
With the recent addition of the presubmit check progress display it
became obvious that hook2 from ./PRESUBMIT.cfg takes quite a bit of
time on each check.
A closer examination has shown that this script scans the entire
codebase on each patch to see if there have been some inconsistencies
wrt EC host command definitions.
Let's limit running this check only to patches which actually touch EC
host commands in any way.
BRANCH=none
BUG=none
TEST=verified that the check runs only when the 'EC_.*CMD' string is
present in the diffs output of the patch
Change-Id: I128dba48332142b8835cf36747ab290190e6bcef
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/815951
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Sam Hurst <shurst@google.com>
This patch sets the PD operating power to 50W, which is the same as what
the AP requires to boot. Since Fizz doesn't have a battery to charge,
we're not interested in lower power.
BUG=none
BRANCH=none
TEST=Boot Fizz on Type-c adapter (87W, 60W). Verify it fails to boot on
on 45W charger.
Change-Id: Ia9191ecf71329c693bee7d5893e53bd2fec70eeb
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/811524
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
This CL adds microsecond to sweetberry timestamp, for more
accuracy in timing sweetberry runs.
This CL is part of the effort to start sweetberry measurements
while running power autotests.
BRANCH=None
BUG=b:68956240
TEST=./powerlog.py -b xxx.board -c xxx.scenario \
--save_stats_json [directory to store it]
Change-Id: I68c40d5be6d684205b49428c4e5cb6e69af6dfdf
Signed-off-by: Mengqi Guo <mqg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/812502
Reviewed-by: Puthikorn Voravootivat <puthik@chromium.org>
The -MP preprocessor option changes generated dependency files such
that removal of .h files does not cause make to fail dependency check.
BRANCH=none
BUG=none
TEST=verified that removal of .h file from the code and from the tree
does not cause failing builds any more.
Change-Id: If6adb6f53938878c914ca6ee6947012548bc0019
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/814876
Reviewed-by: Randall Spangler <rspangler@chromium.org>
This sets power on defaults for UART3 to be routed to
the glados style uart-on-jtag pinout. This is pretty
standardized going forward.
BUG=None
BRANCH=servo-9040.b
TEST=miniterm.py /dev/google/Servo_Micro-2-1.2/serial/Servo_UART3
Change-Id: I397df8fc09da681eba28cae489e2f6eaef8a87d0
Signed-off-by: Nick Sanders <nsanders@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/813180
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
There might be more than one place that will use very similar codes in
CL:542716 (usb_i2c.c). To avoid unnecessary duplication of code, we fold
the logic into i2c_xfer(). With config enabled (illustrated in this CL),
i2c_xfer() will support large reading. An early prototype of potential
usage is demostrated in CL:781300.
BRANCH=none
TEST=For CONFIG_I2C_XFER_LARGE_READ:
With proprietary software on slave: ./touchpad_updater -d
TEST=For usb_i2c regression:
./touchpad_updater still works (where the reading is less than 255)
TEST=For generic EC regression test:
On poppy EC (With CONFIG_I2C_XFER_LARGE_READ defined)
(1) Prevent override of update
/usr/share/vboot/bin/set_gbb_flags.sh 0xa39
(2) flashrom -p ec -w ec_binary_contains_this_CL.bin
(3) ectool reboot_ec cold
(4) "ectool version" verified that both RO/RW/Build info is local.
(5) Test with a type-C DP dongle on DELL 2408WFP.
(6) Plug-in type-C charger and external display still works.
(7) Confirmed that battery is charging.
(7) "ectool battery" reads same data (for fixed field) as before.
(8) "ectool usbpdpower", confirmed charger info displayed as before.
(9) "ectool usbpd 0", confirmed content exactly as before.
(10) For Gyro. Verify under Arc++
Using App: com.gamma.bubblelevel, works the same as before.
(11) For Accelerometers. Verify under Arc++
Using App: com.innoventions.sensorkinetics,
small movement's charts looks as expected.
TEST=For generic EC regression test:
On Caroline EC (Without CONFIG_I2C_XFER_LARGE_READ defined).
Details in CL:810332
BUG=b:63993891
Change-Id: I654868945fa535e784800177d54eb2d9803f5249
Signed-off-by: Chun-Ta Lin <itspeter@google.com>
Reviewed-on: https://chromium-review.googlesource.com/788479
Commit-Ready: Chun-ta Lin <itspeter@chromium.org>
Tested-by: Chun-ta Lin <itspeter@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
The PNPCFG (EC2I control module) is used to set I/O port base
address and IRQ number.
On it8320, PNPCFG will be reset while system event PLTRST_L
is asserted. This means we can't decode I/O cycles correctly
until we re-initialize PNPCFG.
We disable this reset source, then we don't need to re-initialize
PNPCFG for each PLTRST_L asserted.
BRANCH=none
BUG=none
TEST=MECC board with it8320 + Intel SKL-Y RVP3 and boot to shell.
Change-Id: I7efe8f726939245424237c1d153df4f83b39ae6b
Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
Reviewed-on: https://chromium-review.googlesource.com/810428
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Update genvif so that it can create Rev 1.22 Vendor Info Files. Also
format the VIF so that it matches VIFs generated with the USB VIF
generator.
BUG=b:69972352
BRANCH=None
TEST=`make -j buildall`
Used generated VIF for nasher on GRL Test Equipment
Signed-off-by: Sam Hurst <shurst@chromium.org>
Change-Id: I35bc940c0c65c89be9a40ff9228e51123f136e7b
Reviewed-on: https://chromium-review.googlesource.com/801874
Commit-Ready: Sam Hurst <shurst@google.com>
Tested-by: Sam Hurst <shurst@google.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
Create a lockfile at
/run/lock/power_override/battery_tool.lock rather than
/run/lock/battery_tool_powerd.lock so that powerd doesn't
need to special-case the file's path.
BUG=chromium:784651
BRANCH=None
TEST=None
Change-Id: I151cf26d635dc969d113e9d80c93177985a7ab2f
Signed-off-by: Daniel Erat <derat@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/809921
Commit-Ready: Dan Erat <derat@chromium.org>
Tested-by: Dan Erat <derat@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
Even if we set the rtc alarm timeout for more than 86400 secs,
we should not crash the system.
BUG=chromium:768042
BRANCH=none
TEST=on AP console, do 'ectool rtcsetalarm 99999' and
then see 'EC result 3 (INVALID_PARAM)' without crash.
Change-Id: Ic0fa92ff101bce1f4791221c4e1eadaf7a005355
Signed-off-by: Philip Chen <philipchen@google.com>
Reviewed-on: https://chromium-review.googlesource.com/807624
Commit-Ready: Philip Chen <philipchen@chromium.org>
Tested-by: Philip Chen <philipchen@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
This commit just adds the GPIO for controlling the display backlight for
meowth and zoombini. The backlight should be enabled from the EC side
on transitions to S0 and turned off when suspending. Additionally, if
the lid is opened or closed the display backlight will be enabled or
disabled respectively.
BUG=b:69972660
BRANCH=None
TEST=`make -j buildall`
TEST=Flash meowth; Boot to S0, verify that the ENABLE_BACKLIGHT GPIO is
set high; Shut down; Verify that ENABLE_BACKLIGHT is 0.
TEST=Repeat above test on zoombini. Also, boot to S0, use a magnet to
simulate the lid closing, verify that ENABLE_BACKLIGHT is 0 when lid is
"closed". Verify it is 1 when lid is "open".
Change-Id: Iffc5db89a0378d354b1fe9e9e5347d57e7caf69b
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/811752
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
The SN5S330 has support for detecting when Vbus is present on a port.
This commit simply adds an API to query the PPC.
BUG=None
BRANCH=None
TEST=`make -j buildall`.
TEST=Flash a board with the SN5S330, with some extra code, verify that
Vbus can be detected with this API.
Change-Id: I45bf7ff24bcdc447efe12932f51f8094108e29d5
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/791502
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Edward Hill <ecgh@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
The default sourcing current limit can be set by the following config
option:
CONFIG_USB_PD_MAX_SINGLE_SOURCE_CURRENT
However, the way that this macro was being used was incorrect for the
SN5S330 driver. Since, enum values are not known at compile time, the
check needs to happen during runtime. This commit makes this change.
BUG=None
BRANCH=None
TEST=Enable CONFIG_USB_PD_MAX_SINGLE_SOURCE_CURRENT on a board that uses
the SN5S330, verify that there are no build errors.
Change-Id: I04a1fa1e2e42c2f4ba49f1769857a8796b2f0a6f
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/791501
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
This adds a check for the current and new versions,
and will not update if they are matched.
BUG=b:69016431
BRANCH=None
TEST=sudo ./servo_updater.py -b servo_micro
Change-Id: I3462099a086278dc1589609d76facf11a64bd3bc
Signed-off-by: Nick Sanders <nsanders@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/804716
Reviewed-by: Wai-Hong Tam <waihong@google.com>
This patch adds switch-slot option to reboot_ec command. When the
option is specified, it'll make EC switch the active RW slot
before reboot.
BUG=b:69921268
BRANCH=none
TEST=Run ectool reboot_ec cold switch-slot and verify the active
slot is switched.
Change-Id: Iec568be36e6010ed9a51aa768a7f35e4a63f0fc0
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/809944
Reviewed-by: Randall Spangler <rspangler@chromium.org>
