Let sensor be powered on in S3. It is useful for Android and if we want to
disable keyboard wakeup based on lid angle.
Allow EC to disable touchpad and not send keyboard events when lid angle
is greater than 180.
BUG=chrome-os-partner:57510,chromium:620633
BRANCH=gru
TEST=In S3, check the sensors are readable.
Check that when in S3 and lid angle is < 180 EC sends keyboard events.
Check that when in S3 and lid angle is > 180 EC does not send keyboard
events.
Change-Id: I4e7959ed37bc5dfdf9c105ecae94c314b253d77f
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/406739
Commit-Ready: Gwendal Grignou <gwendal@google.com>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Prior x86 boards have had GPIO for toggling RCIN directly on the PCH,
although many likely had HW-assisted methods as well.
With eve we need to generate an eSPI Virtual Wire for RCIN, but in reality
software control over RCIN Virtual Wire is not available with the npcx EC,
so the legacy LPC interface for pulsing KBRST must be used instead as this
is the only way to generate RCIN.
This method will likely vary on different EC chips, but for skylake it
can just be abstracted into the LPC module.
BUG=chrome-os-partner:58666
BRANCH=none
TEST=successful 'apreset warm' on eve EC console
Change-Id: I7f9e7544a72877f75d05593b5e41f2f09a50e1c9
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/400037
Reviewed-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
This board function allows workarounds to be applied to a board after all
power rails are up but before the AP is out of reset.
Most workarounds for power sequencing can go in board init hooks, but for
devices where the power sequencing is driven by external PMIC the EC may
not get interrupts in time to handle workarounds.
For x86 platforms and boards which support RSMRST# passthrough this board
callback will allow workarounds to be applied despite the PMIC sequencing
by ensuring that the function is executed before RSMRST# deassertion.
BUG=chrome-os-partner:58666
BRANCH=none
TEST=test IMVP8 workaround on multiple eve boards
Change-Id: I0569494084000a4b1738ee18aafce5c96900dc4b
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/402591
Reviewed-by: Shawn N <shawnn@chromium.org>
Add the default undefined state for CONFIG_ESPI and rename
CONFIG_VW_SIGNALS to CONFIG_ESPI_VW_SIGNALS.
BUG=chrome-os-partner:58666
BRANCH=none
TEST=pass presubmit checks
Change-Id: I45242d545915c16bb46f751532a01ab937cee5f0
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/400032
Reviewed-by: Shawn N <shawnn@chromium.org>
The power state driver would print out the current power state along
with its signals everytime a power signal interrupt was fired. On some
systems, a signal may briefly go low and then come back before our
chipset module has a chance to notice. This causes what appears to be
duplicate prints.
This commit tries to only print out the current power state when
something has actually changed. If the input power signals or state
differs from the last time it checked, then the information will be
printed.
BUG=None
BRANCH=gru
TEST=Find a kevin where PGOOD goes away quite frequently. Build and
flash; Verify that significantly less "power state S0" console spam is
emitted.
TEST=Verify that all state transitions are still printed.
Change-Id: I9d66c04e2ed79ab203c54f0a8dad82f32856bbf0
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/388761
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
In order to help correlate EC logs with those from the kernel, it was
suggested that the EC could periodically print the RTC time. This
commit prints out the RTC time when changing power states.
BUG=chrome-os-partner:57731
BRANCH=gru
TEST=Build and flash kevin. Boot system up and suspend. Verify that
RTC times are logged to the EC console.
Change-Id: Ia1ee1ec88c6733f863a703fb3f841ab74b80fcb9
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/388802
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
In order to help correlate EC logs with those from the kernel, it was
suggested that the EC could periodically print the RTC time. This
commit prints out the RTC time when a chipset reset is requested.
BUG=chrome-os-partner:57731
BRANCH=gru
TEST=Build and flash kevin. Trigger watchdog from kernel and verify
that RTC time is printed when the chipset is reset.
Change-Id: Idc9a815c3337f720d41d16e0d844b4c1ea6728d8
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/388857
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
Holding SYS_RST low will keep the TPM in reset, and prevent a
reset-too-soon-after-power-on case that put the TPM into a bad state.
BUG=chrome-os-partner:56414
BRANCH=None
TEST=Manual on kevin rev5, verify board still seqences from G3->S0 and
back, S0->S5 and back, S0->S3 and back.
Change-Id: I07671079deedb757314679608d848b1620aa67d6
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/374899
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Catherine Xu <caxu@google.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Since pretty much always, we've declared console commands to take
a "longhelp" argument with detailed explanations of what the
command does. But since almost as long, we've never actually used
that argument for anything - we just silently throw it away in
the macro. There's only one command (usbchargemode) that even
thinks it defines that argument.
We're never going to use this, let's just get rid of it.
BUG=none
BRANCH=none
CQ-DEPEND=CL:*279060
CQ-DEPEND=CL:*279158
CQ-DEPEND=CL:*279037
TEST=make buildall; tested on Cr50 hardware
Everything builds. Since we never used this arg anyway, there had
better not be any difference in the result.
Change-Id: Id3f71a53d02e3dc625cfcc12aa71ecb50e35eb9f
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/374163
Reviewed-by: Myles Watson <mylesgw@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Do not power-on the AP unless battery can provide sufficient power
or the charger is negotiated to sufficient power.
BUG=chrome-os-partner:56494
BRANCH=none
TEST=Manually tested on Reef. Device can boot to OS without the
battery & cut-off battery.
Change-Id: Ib22bad81a29ccbb2fecc8e835148b627dd722988
Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/374023
Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
rk3399 doesn't use AP-controlled wireless power state and
CONFIG_WIRELESS isn't defined, so wireless_set_set() is in fact an empty
useless function.
BUG=None
BRANCH=None
TEST=Verify basic EC functionality on Kevin.
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: I6e3631012ca1f356555a847793050ebdef8eee52
Reviewed-on: https://chromium-review.googlesource.com/373643
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Add virtual wire power signals support for skylake. By adding
CONFIG_VW_SIGNALS definition in board level driver, we can save three
GPIOs (SLP_S3/SLP_S4/CLK_RUN) on skylake platform.
Modified sources:
1. common.c: Add support for VW power signals.
2. skylake.c: Add upper func to get system sleep state through GPIOs or VWs.
BRANCH=none
BUG=none
TEST=make buildall; test boot up and shut down on eSPI POC of wheatley.
Change-Id: I0eae363dad8cec011eb32929a40701f19fde7e1a
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/366711
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Allow the host to self-report its sleep state through
EC_CMD_HOST_SLEEP_EVENT, which will typically be sent with SUSPEND
param when the host begins its sleep process. While the host has
self-reported that it is in SUSPEND, don't assert the interrupt
line, except for designated wake events.
BUG=chrome-os-partner:56156
BRANCH=None
TEST=On kevin, run 'ectool hostsleepstate suspend', verify that
interrupt assertion is skipped for battery host event. Run 'ectool
hostsleepstate resume' and verify interrupt is again asserted by the
battery host event.
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: I74288465587ccf7185cec717f7c1810602361b8c
Reviewed-on: https://chromium-review.googlesource.com/368391
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Cr50 has sys_rst_l as a wake source, but it can't tell which pin woke it
on resume. To know the source it has to check the value of the pin on
resume. This change makes the delay long enough for Cr50 to resume and
check that sys_rst_is asserted.
BUG=chrome-os-partner:55674
BUG=b:30308276
BRANCH=none
TEST=enable sleep on cr50 and verify apreset still reset it
Change-Id: I8e088c5f13a4222142161d8b79550dfc6eb529d6
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/364170
Reviewed-by: Shawn N <shawnn@chromium.org>
On a power press that will bring the system to S0, start our 8 sec
timeout in case the power button is never released.
BUG=chrome-os-partner:55666
BRANCH=None
TEST=Press and hold power button on kevin to bring device to S0, verify
device boots in normal mode and powers down ~8 seconds after initial
press.
Change-Id: I1cbb52974bcc09d23a130df13815cee07968467a
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/363592
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Before, as soon as the EC started booting, it would unconditionally boot
the AP (unless explicitly told not to. ie: "reboot ap-off"). However,
we weren't waiting for our power to settle which was causing some
brownouts. This would happen when trying to boot without the battery.
This commit causes the EC to inhibit powering on the AP until we have
sufficient power.
BUG=chrome-os-partner:55289
BRANCH=None
TEST=Flash EVT2; verify can boot normally.
TEST=Remove battery and insert charger. Verify that DUT can boot up.
TEST=Insert drained battery. Verify power on is inhbited. Plug in
charger and verify that DUT can power on.
Change-Id: Ifb40766fcc1d330674ec39de6d81174f92b6d658
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/361005
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
The firmware needs to talk to the EC while the power button is pressed.
If the EC did not even leave the S5->S3 state this is not possible.
Seems like the piece of code is not even necessary, check_for_power_off_event
will catch the long press asynchronously later on anyway.
BRANCH=none
BUG=chrome-os-partner:54781
TEST=power up by power button and hold it, there should be
no error logs during EC sync, and screen turns on for a short time
then off
Change-Id: Ic0cccb6cfc5ddd389c1111a77ec06530a9e429ef
Signed-off-by: Koro Chen <koro.chen@mediatek.com>
Reviewed-on: https://chromium-review.googlesource.com/359152
Reviewed-by: Rong Chang <rongchang@chromium.org>
- Power up the AP automatically on initial EC power-on.
- In S0, wait for 8s power button hold before powering down.
- In S3 and lower, power down immediately on power press.
- In G3 / S5, power up on lid open.
BUG=chrome-os-partner:54582,chrome-os-partner:54511
BRANCH=None
TEST=Manual on gru. Verify the following:
- AP powers up when battery initially attached.
- `reboot` powers up AP after EC reset.
- `reboot ap-off` doesn't power up AP.
- `apshutdown` + `lidclose` + `lidopen` causes AP power-up.
- Holding power for 4s in S0 does not change power state.
- Holding power for 8s in S0 causes AP power down.
Change-Id: I588056549a972212c28b9aa6a83fe2e0b179baa9
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/355650
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
PP1800_PMU impacts the initial centerlogic voltage due to DVS circuitry.
Since there's no other sequencing dependency, turn it on earlier.
This fixes centerlogic from initially starting too high (1.5V).
BUG=none
BRANCH=none
TEST=Watch PPVAR_CENTERLOGIC and confirm that it starts at the target voltage
Change-Id: Icac076a7e8aef978401452a98d9f6bc8b373d94f
Signed-off-by: David Schneider <dnschneid@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/352247
Reviewed-by: Shawn N <shawnn@chromium.org>
Leave USB-A charging enabled in S3, and move gru-specific code into
board hooks, out of the power state driver.
BUG=chrome-os-partner:54159
BRANCH=None
TEST=Manual on gru. Verify USB-A enable GPIOs are asserted in S0 and
deasserted in G3.
Change-Id: Icadeb771226dd0fda4ae96fdde9b3984d87fdd15
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/351670
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Power-down sequence in reverse order of power-up, with delays extended
to 10ms, to allow rails extra time to decay.
BUG=chrome-os-partner:54159
BRANCH=None
TEST=Manual on gru. Verify repeated `powerbtn` commands on console
boot + power-down the SOC.
Change-Id: I2e8fb39f8f900e56deef6b386bae1c336aa1f963
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/351520
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Move power rail and pmic enable control to be handled at
board level due to specific board design.
Modify rsmrst where assertion is pass-through at all time
and de-assertion is only pass-through at power up.
BUG=chrome-os-partner:53666
BRANCH=none
TEST=amenia is able to handle apreset warm/cold, pmic shutdown,
soc reset/shutdown.
Change-Id: I7ff819d88d0e194073bee8f02b1e3fa70ca44ba7
Signed-off-by: Kevin K Wong <kevin.k.wong@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/347370
Commit-Ready: David Hendricks <dhendrix@chromium.org>
Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Tested-by: David Hendricks <dhendrix@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Divya Jyothi <divya.jyothi@intel.com>
This adds the basic framework for Reef including full GPIO listing,
board config file, and rudimentary functionality. It has not been
fully tested and still has several TODOs/FIXMEs. For now we just need
something that will build and can be incrementally improved.
BUG=chrome-os-partner:53035
BRANCH=none
TEST=EC and AP both boot, seems reasonably stable for now
Change-Id: I4934ad00917e251dd1d7eb759207a92c45a36136
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/339292
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Use input signals to verify power state and determine power state after
sysjump.
BUG=chrome-os-partner:52878
BRANCH=None
TEST=Manual on kevin.
- Verify AP powers up on 'powerbtn'.
- AP shuts down on 'apshutdown'.
- AP re-powers / resets on 'powerbtn' + 'apreset'.
- AP doesn't shutdown on 'sysjump rw' while in S0.
Change-Id: Id24feb0f8490aa7cb73c46178085ff2e46f8d0a6
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/341704
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: David Schneider <dnschneid@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
add optional chipset specific function to check if PLTRST# is valid
BUG=chrome-os-partner:52656
BRANCH=none
TEST=make buildall, able to boot to OS on amenia
Change-Id: I7a2747c4f77f50393c3250c2ab0e1625e64e5a41
Signed-off-by: Kevin K Wong <kevin.k.wong@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/341732
Reviewed-by: Shawn N <shawnn@chromium.org>
Previously calls to hook_call_deferred were passed the function to call,
which was then looked up in the .rodata.deferred section with a linear
search. This linear search can be replaced with a subtract by passing
the pointer to the deferred_data object created when DECLARE_DEFERRED
was invoked.
Signed-off-by: Anton Staaf <robotboy@chromium.org>
BRANCH=None
BUG=None
CQ-DEPEND=CL:*255812
TEST=make buildall -j
Change-Id: I951dd1541302875b102dd086154cf05591694440
Reviewed-on: https://chromium-review.googlesource.com/334315
Commit-Ready: Bill Richardson <wfrichar@chromium.org>
Tested-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
PMIC already has a built-in 100ms delay for V1P05S when ALL_SYS_PWRGD
asserts, hence EC can assert SOC_PWROK immediately. On shutdown RSMRST_N
should assert and SOC_PWR_OK should de-assert immediately when PMIC asserts
PMIC_RSMRST_N and de-assert All_SYS_PWRGD respectively. Hence removed
the unnecessary timing delay for SOC_PWROK and RSMRST_N.
BUG=none
BRANCH=none
TEST=Issued a shutdown command and manually tested on amenia.
RSMRST_N asserts immediately when PMIC asserts PMIC_RSMRST_N
SOC_PWR_OK de-asserts immediately when PMIC de-asserts All_SYS_PWRGD.
Change-Id: I8bb79277a3dcf8545764ba58736f422ac377776e
Signed-off-by: Kevin K Wong <kevin.k.wong@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/339001
Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
Implement warm reset and force shutdown routines, which are called from
other modules.
BUG=chrome-os-partner:51926, chrome-os-partner:51923
BRANCH=None
TEST=Verify 'apshutdown' on EC console goes to G3. Verify 'apreset'
causes AP reset while staying in S0.
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: Ifb479287f87f31ac49e007c337cc0c24a79898e6
Reviewed-on: https://chromium-review.googlesource.com/338923
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
Elm is an oak variant that uses ANX7688 PD port controller. This CL sets
PD port count to 1 and modifies TCPC I2C address to 0x50.
Other elm changes are included in this change:
- add 2 KX022 motion sensors, remove BMI160
- remove ALS
- LED configuration changed to 2 bi-color LEDs
- remove pi3usb30532
- add ANX7688 mux driver
- change PD interrupt polarity
BRANCH=none
BUG=none
TEST=manual
make BOARD=elm -j
load and test on elm proto
Signed-off-by: Rong Chang <rongchang@chromium.org>
Change-Id: I8ad02da9acade985bc0e7e2f85d9e58db7e6b38d
Reviewed-on: https://chromium-review.googlesource.com/331453
Reviewed-by: Shawn N <shawnn@chromium.org>
Various voltage rails will be enabled / disabled by the PMIC when
GPIO_PMIC_SLP_SUS_L changes. We need to delay the disable of V0.85A
by approximately 25ms in order to allow V1.00A to sufficiently discharge
first.
BUG=chrome-os-partner:52047
TEST=Probe V1.00A and V0.85A during power-down, verify V1.00A discharges
faster than V0.85A.
BRANCH=glados
Change-Id: Ibbf4f989e1814e131dc373d2b5da9b6fa1ac9cce
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/337325
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The debounce timer might be too slow to actually update the state of
debounced_power_pressed by the time we do power_button_is_pressed in
the S3->S5 state transition.
Call power_button_wait_for_release() instead of wait_for_power_button_release()
to make sure there are no deferred actions.
BRANCH=none
BUG=chrome-os-partner:50362, chrome-os-partner:51109
TEST=During dev mode screen, press power button, note the device stays off
TEST=sudo test_that -b oak <DUT_IP> firmware_FwScreenPressPower
Change-Id: Ic60c1847ba461ef874dea5bf7d03675622f24beb
Signed-off-by: YH Huang <yh.huang@mediatek.com>
Reviewed-on: https://chromium-review.googlesource.com/332310
Reviewed-by: Rong Chang <rongchang@chromium.org>
CONFIG_PMIC_FW_LONG_PRESS_TIMER was ported long time ago from
Tegra, but the codes are actually not used and erroneous.
It might wrongly trigger set_pmic_pwron(0), and turn off
PMIC power accidentally. This causes POWER_GOOD lost and
power state will go back to S5 during boot up.
Clean up the codes by referencing check_for_power_off_event()
of Rockchip.
BRANCH=none
BUG=none
TEST=bootup and press power button quickly right after we are in S0.
Bootup should still complete normally.
Change-Id: Ie034efa3575dbebae4debb1afc206fddd9116350
Signed-off-by: Koro Chen <koro.chen@mediatek.com>
Reviewed-on: https://chromium-review.googlesource.com/332724
Reviewed-by: Rong Chang <rongchang@chromium.org>
After power good is lost, PMIC requires some time to turn off
all its internal power before we can turn off VBAT by
set_system_power(0). This ensures the power measurement is within
PMIC spec when system is shut down.
BRANCH=none
BUG=none
TEST=measure the power rails of PMIC after system is shut down
Change-Id: I55d4d99ed0ef69b103a4e52e9f9eec1c9e6265b5
Signed-off-by: Koro Chen <koro.chen@mediatek.com>
Reviewed-on: https://chromium-review.googlesource.com/332409
Reviewed-by: Rong Chang <rongchang@chromium.org>
this is to move the existing code from chipset level to board level
since PseudoG3 is a board feature that required specific hardware.
BUG=none
BRANCH=glados
TEST=use hibernate command to enter PseudoG3
Change-Id: I309ef89e0ff7057ce46c634baa9791731a771984
Signed-off-by: Kevin K Wong <kevin.k.wong@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/327677
Reviewed-by: Shawn N <shawnn@chromium.org>
