Touch the watchdog during init to prevent it from firing
prematurely during HOOK_INIT processing before the tasks are
started and watchdog_reload() will be called with HOOK_TICK.
BUG=b:77336348
BRANCH=eve,poppy,fizz,reef,kevin
TEST=run stress test for several days:
while true ; do ectool reboot_ec RO ; ectool reboot_ec RW ; done
Change-Id: I79e744a4678ab1808870d0e7647d2ce273ddeb8f
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1001532
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
During watchdog initialization, the driver doesn't disable ITIM16
module which used for detecting watchdog timeout before updating
new preload value. Although the ITEN bit on reset is zero, it caused
preload value is not updated to module successfully since ITEN won't
be reset (ITIM16 is still enabled) in sysjump case.
Despite WDCNT will be reloaded by touching watchdog in HOOK_TICK
hook function later, it's better to disable any ITIM16 module before
updating ITCNT register.
BRANCH=none
BUG=b:77336821
TEST=No build errors for npcx5 series.
Change-Id: I19baa47bca347b9dca2fc1dcaacca81519facf21
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/999458
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Before this change uart_ec_interrupt and software watchdog
interrupt handler both had priority 0. Since UART IRQ number is
33, and software watchdog is 44, the UART interrupt handler
would have higher prority.
Fix this by increasing all interrupt handler priorities, leaving
the software watchdog handler alone on priority 0.
BRANCH=eve,poppy,fizz
BUG=b:76391320
TEST=Cherry-pick CL:979736 (causes a watchdog in UART interrupt
handler), check that panicinfo contains a sensible PC in r5
after reset.
Change-Id: I97f99af5192a4a9571854a4d3f7c48a4674d605e
Signed-off-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/979738
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
If an ITIM32 timeout event occurred during lpc_sib_wait_host_read_done()
and lpc_sib_wait_host_write_done() routines, in rare case, ec might have
a chance to gets stuck since ec's interrupts are disabled when CSWR/CSRD
bits are high forever. (Normally, CSWR/CSRD bits won't be always high.
These bits are high forever also means something wrong on LPC/eSPI
bus.)
In order to prevent this situation, the CL checks TO_STS bit of ITCTS
in these routines. If this bit is set, restoring ITIM32 preload counter
value to maximum value and processing overflow will be done by
force_time().
BRANCH=eve,fizz,poppy
BUG=b:76182199
TEST=No build errors for npcx series. Passed test command of CL 979389
on npcx_evb. No symptom occurred during warm reset stress test on
soraka.
Change-Id: Ic645f7c5a2a1e49a3c1f3d7e089dd66b4bb75ac6
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/979874
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
No one is using this method and it implies that all chipset should
support the RCIN# Virtual Wire if using eSPI. Only large core chips
use RCIN#; small core chips don't.
This method was introduced for skylake and has since been replaced
since CL:575947 was merged.
BRANCH=none
BUG=none
TEST=build all
Change-Id: Ic541e3d61d1e0ecc64a0bb12385bdada40f0acf2
Signed-off-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/975904
We have a growing list of boards in chip/npcx/system.c that are
unable to distinguish a reset from a power-on or a reset-pin type.
Instead of being a temporary issue this is now solidified in the
design on some kabylake boards.
Instead of defining board-specific checks in the chip code this
change adds a config option that the relevant boards can define.
BUG=b:76232539
BRANCH=none
TEST=make -j buildall passes
Change-Id: I76e0f011d70ce6f778b1fb6a56c2779c39c3cbd6
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://chromium-review.googlesource.com/979575
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
These print-outs are usually very deep in the call stack (rare
error cases that do not happen often), and therefore are the
longest branches on most tasks. Replacing cprints by
cputs/cprintf helps with that.
BRANCH=none
BUG=b:75234824
TEST=make BOARD=soraka SECTION=RW analyzestack | grep Task shrinks
significantly (more than 100 bytes on some tasks)
Change-Id: I7c5bb750f4aa624cd06736e0bb6b24d307fc0196
Signed-off-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/966041
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
A few commands had help text of "[0 | 1]" but parse_bool()
doesn't recognize 0 and 1. Change help text to "[on | off]",
matching other commands.
BUG=b:75302458
BRANCH=none
TEST=none
Change-Id: I9b1e4a70e024d17ec8bccc015069e31d7fff08ca
Signed-off-by: Edward Hill <ecgh@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/967248
Reviewed-by: Randall Spangler <rspangler@chromium.org>
If the I2C port is completely broken then there is no point in trying to
continue with the transaction. This can happen if the pull-ups on the bus
are not working because they are in a power domain which is not currently
enabled.
Check the return value from i2c_unwedge() and return if it doesn't work.
Tidy up a few comments at the same time.
BUG=b:72129419
BRANCH=none
TEST=manually remove the check AP being off in sb_tsi_get_val() and see
that it quickly fails now, rather than hanging the EC for a while trying
the transaction.
Change-Id: I66ab52943459726537dfc74355f8aeaa5817dba5
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/956017
Reviewed-by: Edward Hill <ecgh@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@google.com>
Some boards have forgotten to undef CONFIG_PECI but it is benign. This
should be an opt-in feature instead of an opt-out feature. No one is
using it, so no one will opt-in.
BRANCH=none
BUG=none
TEST=Verified that grunt, kahlee, meowth, and zoombini are not using the
PECI bus for Soc temperature via schematics (GPIO81). Other boards are a
no-op. See cl:951407 for steps taken to ensure all npcx boards were
accounted for.
Change-Id: I6ca4b9d22b7cb23c9842729658810ebe165ff6cc
Signed-off-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/951408
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
This patch splits struct fan_t into two parts: base configuration
and RPM configuration. RPMs are expected to be different from
model to model while a base configuration is most likely shared.
BUG=b:73720175
BRANCH=none
TEST=make buildall
Change-Id: Iff17573f110e07e88d097dd848cf91ee98b83176
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/949382
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
The CONFIG_UART_HOST is supposed to be defined to the index of the UART we
want to use. It is not supposed to be defined as a boolean. Updated npcx
and all incorrect uses.
BRANCH=none
BUG=none
TEST=Added the following diff to ensure that everything still built:
diff --git a/chip/npcx/lpc.c b/chip/npcx/lpc.c
index 446baa842..826233744 100644
--- a/chip/npcx/lpc.c
+++ b/chip/npcx/lpc.c
@@ -897,6 +897,9 @@ static void lpc_init(void)
/* Initialize Hardware for UART Host */
#ifdef CONFIG_UART_HOST
+#if !CONFIG_UART_HOST
+#error "Fix me"
+#endif
/* Init COMx LPC UART */
/* FMCLK have to using 50MHz */
NPCX_DEVALT(0xB) = 0xFF;
Change-Id: Ia46c7cb86c6040a5c75dddf23d5ccd8e33210581
Signed-off-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/949308
Reviewed-by: Randall Spangler <rspangler@chromium.org>
1. Enable fan feature and update fan setting.
2. Enable SW and chipset throttle feature.
3. Fix the issue that cannot set fan duty by "fanduty" in EC console.
BUG=b:72974136
BRANCH=none
TEST=Check fan command(fanduty/fanset/fanauto) in EC console can work and
check below condition.
1.AP throttling soft
--> Increased temperature to over trigger point, then to check
EC notify event in EC console.
2.AP throttling hard
--> Increased temperature to over trigger point, then to check
EC notify event and CPU_PROCHOT pin status in EC console.
3.Fan controlled in s3/s5 as expected (by EC)
--> Check Fan turn off in s3/s5.
4.Fan controlled in S0 as expected (by DPTF)
--> Check Fan keep 100% duty and no see DPTF to set fan duty.
But fan duty can be control by "fanduty" in EC console.
Change-Id: If9fd7f64c123ff54742052b6310023f0d4b0113a
Signed-off-by: raymondchou <raymond_chou@compal.corp-partner.google.com>
Reviewed-on: https://chromium-review.googlesource.com/906086
Commit-Ready: Raymond Chou <raymond_chou@compal.corp-partner.google.com>
Tested-by: Raymond Chou <raymond_chou@compal.corp-partner.google.com>
Reviewed-by: Raymond Chou <raymond_chou@compal.corp-partner.google.com>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
NPCX7 requires that the HW_WIRE bits 2-0 of VWEVSM2 register are set
so that the hardwire signals for SCI, SMI and RCIN are connected to VW
input of eSPI_SIF module. NPCX5 did this by default, however NPCX7 has
made it configurable.
NPCX7 however sets the HW_WIRE bits 2-0 to 1 at reset. So, this change
ensures that they are preserved while initializing VWEVSM2 registers
BUG=b:74111394
BRANCH=None
TEST=Verified that SCI works on glkrvp and meowth with NPCX7.
Change-Id: I9da6f45b4aa0b72b68db6192cb7567f09b072f0c
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://chromium-review.googlesource.com/943801
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Divya S Sasidharan <divya.s.sasidharan@intel.com>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: ML Chao <mlchao@nuvoton.corp-partner.google.com>
Reviewed-by: Jett Rink <jettrink@chromium.org>
Currently, if there is a fan which isn't in RPM mode, the rest of the
fans are not controlled even if they're in RPM mode. This patch gives
a chance to all the fans.
BUG=b:35543471
BRANCH=none
TEST=none
Change-Id: I6f930bad313bc2a31497f46647ab2b08e328dfff
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/940813
Reviewed-by: Randall Spangler <rspangler@chromium.org>
This CL adds the driver support for the WoV module which inludes the
following files:
- wov.c
- wov_chip.h
- apm.c
- apm_chip.h
It also supports the console commad "wov" which can test different
configuration and audio quality by entering different parameters.
The detail description of WoV console command is listed below:
------------------------------------------------------------------------
[Note]: Before changing any of settings, please make sure the operation
mode is on the "OFF" state. (ie. run the command wov cfgmod off
first) .
> wov init
Initialize WoV interface, including pin mux and interrupt
registration etc.
> wov mute <enable / disable >
mute enable / disable.
> wov cfgsrc <mono | stereo | left | right>
set audio source, ex: wov cfgsrc left, means audio source from left
MIC.
> wov cfgbis <16|18|20|24>
set audio resolution, ex: wov cfgbit 16 means audio resolution are
16bits.
> wov cfgsfs <8000|12000|16000|24000|32000|48000>
set audio sampling frequency rate, ex: wov cfgsfs 48000 means audio
sampling rate are 48Khz.
> wov cfgbck <32fs|48fs|64fs|128fs|256fs>
set I2S bit clock rate, ex: wov cfgsfs 48000 and wov cfgbck 32fs
means audio sampling rate are 1536Khz (32*48000).
> wov cfgfmt <i2s|right|left|pcma|pcmb|tdm>
set I2S but format, ex: wov cfgfmt right means audio I2S format are
Right-Justify.
> wov cfgmod <off|vad|ram|i2s|rami2s>
set audio operation mode ,ex: wov cfgmod i2s means audio output via
I2S bus.
> wov cfgtdm <0~496 0~496 0~3>
set TDM time slot, the first values is left channel delay counter,
the second is right channel, and the 3rd is startup counting condition.
(chosen LRCK raising or falling edge) .
[Note: this command is just working on cfgmod equal to tdm]
> wov cfgget
retrieve above settings.
> wov vadsens
(currently not support, reserve for next version)
> wov gain (0~31)
set audio data gain value, ex: wov gain 10 means setting audio digital
gain are 10dB.
> wov cfgdck <1.0 | 2.4 | 3.0 >
set digital MIC PDM clock rate. ex: wov cfgdck 2.4 means PDM clock
are 2.4Mhz.
-----------------------------------------------------------------------
This CL also adds the chip ID (0x24) for npcx7m7w. So the console
command "version" can show the chip is npcx7m7w.
BRANCH=none
BUG=none
TEST=No build errors for make buildall.
TEST="BOARD=npcx7_evb make"; Flash the image on EVB; Test WoV function
with console commands described above.
Change-Id: Ief2b3e89edbd3e6d2a9d82d317a93c9f0b7a20cd
Signed-off-by: Dror Goldstein <dror.goldstein@nuvoton.com>
Signed-off-by: Simon Liang <CMLiang@nuvoton.com>
Signed-off-by: CHLin <CHLIN56@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/897314
Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com>
Tested-by: CH Lin <chlin56@nuvoton.com>
Reviewed-by: Scott Collyer <scollyer@chromium.org>
Fan enable state is controlled in common/fan.c. This patch prevents
npcx fan driver from enabling it.
BUG=b:73127788
BRANCH=none
TEST=Verify no 'Fan 0 stalled' is printed in S3 and S5. Verify the
fan spins in S0.
Change-Id: I549253a64c91d8a23bb793c3506b5daf1f7642be
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/937941
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
According to NPCX data sheets (NPCX5 and NPCX7), ESPI_MAXFREQ should
be decided based on the value of FMCLK. Since we are setting FMCLK to
30MHz on NPCX5, eSPI_MAXFREQ needs to be set to 33MHz.
This change sets ESPI_MAXFREQ_MAX depending upon the value of FMCLK.
BUG=b:73504527
BRANCH=fizz?
TEST=Verified that on soraka ESPI_MAXFREQ is set to 33MHz. Also, ran
some reboot tests to ensure that there is no regression in boot time.
Change-Id: Iaee89078741cf44c7ac232e2ee14d75384f68a35
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://chromium-review.googlesource.com/925843
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-by: caveh jalali <caveh@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
According to Nuvoton datasheet, when SHM windows are in IO mode, only the
bottom 16-bits of registers @ offset xF4 and xF8 are used.
"This register is ignored when WRAM1_IO bit in WIN_CFG register is set to
1 (LPC / eSPI Peripheral Channel I/O access with 16-bit address). This
register is set to its default value by Host Domain reset."
BRANCH=none
BUG=none
TEST=boot grunt and verify host communication still works.
Change-Id: I3e48ea1b09355eaf6967b9f7522bc3d35459b76b
Signed-off-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/919006
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Mulin Chao <mlchao@nuvoton.com>
the npcx7 can only run eSPI at (up to) 50MHz while the npcx5 can go up
to 66MHz. so, set the max speed to whatever the hardware can actually
do. the bit pattern for 66MHz is "reserved" on the npcx7, so let's
not even define it in the npcx7 case.
BUG=b:72838699, b:71859563
BRANCH=none
TEST="make buildall" passes; boots on meowth
Change-Id: I428caf72a41fe58008df4624c475dafadca4a0bc
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/910321
Commit-Ready: caveh jalali <caveh@chromium.org>
Tested-by: caveh jalali <caveh@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Since there is no KEYPROTO task on chromebox such as fizz and sion, lpc
driver doesn't declare KBC IBF/OBE ISRs for these events. If host put
data in ec's KBC input buffer unexpectedly, exception_panic() will be
executed in default_handler. Then we will see ec print
"=== PROCESS EXCEPTION: 29 ====== xPSR: 01000000 ===" message without
any hard fault and reset.
This CL fixed this symptom by turning off KBC if there is no KEYPROTO task.
We also run suspend stress test on fizz and no watchdog reset symptom
occurred.
BRANCH=none
BUG=b:72353876
TEST=No build errors. Run suspend stress test on fizz and no watchdog
reset occurred.
Change-Id: I4744fac0d6fb2628849c728d4860509434fa2cbb
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/899706
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Duncan Laurie <dlaurie@google.com>
In this CL, we add the following changes to support the CHIP_VARIANT
npcx7m6xb and npcx7m7w:
1. Define the code RAM, data RAM, BBRAM base address/size.
2. Initialize the wov.c file for WoV driver development. (It will be
compiled only when CHIP_VARIANT=npcx7m7w in the build.mk and
CONFIG_WAKE_ON_VOICE is defined in board.h)
3. Fix the the incorrect offset of PWDWN_CTRL7 register.
BRANCH=none
BUG=none
TEST=No build errors for make buildall.
TEST=Change CHIP_VARIANT to npcx7m7w/npcx7m6xb in
board/npcx7_evb/build.mk; "BOARD=npcx7_evb make"; Check ec image can be
built. Flash the image on EVB; make sure EVB bootup.
Change-Id: I87bccb9097f8f0a6c67f96a8d90adf201ae9e773
Signed-off-by: CHLin <CHLIN56@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/858637
Commit-Ready: CH Lin <chlin56@nuvoton.com>
Tested-by: CH Lin <chlin56@nuvoton.com>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Boards needs to define GPIO_EC_COMM_PU, which needs to be driven
high during EC-EC transaction. This makes sure that the line does
not go low, even when the base goes away during the transaction.
BRANCH=none
BUG=b:68954760
TEST=EC-EC communication works with this change.
TEST=With signal analyzer, check that UART line is always kept
high while transaction is in progress.
Change-Id: Iad7b26a9a93b674aa4fff0bc3a72a13e6782515d
Signed-off-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/845544
Reviewed-by: Randall Spangler <rspangler@chromium.org>
The original ec_npcxspiflash lfw is used by the openocd to program SPI
flash via Servo JTAG. In order to support UUT mode to program SPI flash,
this CL modified the lfw with the following changes:
1. Rename the lfw ec_npcxflash to npcx_monitor to unify the naming.
2. The npcx_monitor will read the first 4 bytes from the area of monitor
header. If the monitor identifies the first 4 bytes is a UUT tag, it
will read parameters(SPI_OFFSET/IMAGE_SIZE) from the relative offset of
monitor header. Otherwise, it will read parameter from the general
register r0/r1 which will be restored by openocd script in advance.
3. Add monitor_hdr.c to generate the monitor header binary files
(monitor_hdr_ro.bin/monitor_hdr_rw.bin)) automatically after compiled.
The memory layout to restore the reuqired binaries are listed below:
ec firmware(RO/RW) - the start address of Code RAM area.
monitor header - 0x200C3000
npcx_monitor - 0x200C3020
BRANCH=none
BUG=none
TEST=No build errors for "make buildall".
TEST=Follow instructions in CL:826763; make sure the ec firmware is
updated and ec can boot up.
CQ-DEPEND=CL:828341
Change-Id: I5de997a4dee5449d578972e2f929c6e08c5dff67
Signed-off-by: CHLin <CHLIN56@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/826909
Commit-Ready: CH Lin <chlin56@nuvoton.com>
Tested-by: CH Lin <chlin56@nuvoton.com>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
For debug, in common code let's log the watchdog PC
and task id as our SW panic params.
BUG=chromium:790006
BRANCH=none
TEST=manually test scarlet rev2 from a1-a3, b1-b2:
(a1) Add 'while(1);' in button ISR
(a2) Boot and press the button
(a3) When watchdog is triggeried, check with 'panicinfo'
that saved R5 is the PC for button ISR.
(b1) 'crash watchdog' in EC console
(b2) Check with 'panicinfo' that CONSOLE task id is saved in
EXCEPTION and PC is saved in R5.
Change-Id: I64d2fcf594dd24b0951e002ab8e80ebcac2d1def
Signed-off-by: Philip Chen <philipchen@google.com>
Reviewed-on: https://chromium-review.googlesource.com/803618
Commit-Ready: Philip Chen <philipchen@chromium.org>
Tested-by: Philip Chen <philipchen@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
After firmware update, cr50 toggles the EC's reset line, expecting
the system will boot. This isn't the case for Chromebox because it
sets AP_OFF flag on a clean shutdown (to restore the previous power
state after power loss & restore).
This patch adds EC_REBOOT_HIBERNATE_CLEAR_AP_OFF to EC reboot
command. It makes EC first clear AP_OFF then hibernate.
BUG=b:69721737
BRANCH=none
TEST=Verify Fizz reboot after cr50 update.
Change-Id: If3207d7284f244ca1adf0d516ef744dbc739a9c1
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/802632
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This CL fixed the issue that ec cannot enter low power mode, which
increases more power consumption in s5, by not setting ESPIRSTWE bit.
For more detail, please see the npcx5's errata rev1_7, No.2.21.
BRANCH=none
BUG=b:69351155
TEST=No build errors for "make buildall".
TEST=build and flash soraka, run commands to read the power consumption:
dut-control pp3300_dsw_ec_cfg_reg:0x7327k
dut-control pp3300_dsw_ec_mw -t 20 | grep "@@"
the average power consumption measured reduces from 42.x to 10.x mw.
TEST=do cold reboot stress test for 4 hours and no symptom occurred.
Change-Id: Ic6fd7fe14ae8acaefd4e1a99ca1625254f67d708
Signed-off-by: CHLin <CHLIN56@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/778709
Commit-Ready: CH Lin <chlin56@nuvoton.com>
Tested-by: CH Lin <chlin56@nuvoton.com>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
With the upcoming change to add a new command to get/set/clear host
events and masks, it seems to be the right time to bump up the host
events and masks to 64-bit. We are already out of available host
events. This change opens up at least 32 bits for new host events.
Old EC commands to operate on host events/masks will still deal with
lower 32-bits of the events/mask. On the other hand, the new command
being added will take care of the entire 64-bit events/masks. This
ensures that old BIOS and kernel versions can still work with the
newer EC versions.
BUG=b:69329196
BRANCH=None
TEST=make -j buildall. Verified:
1. hostevent set 0x4000 ==> Sets correct bit in host events
2. hostevent clear 0x4000 ==> Clears correct bit in host events
3. Kernel is able to query and read correct host event bits from
EC. Verified using evtest.
4. Coreboot is able to read correct wake reason from EC. Verified
using mosys eventlog list.
Change-Id: Idcb24ea364ac6c491efc2f8dd9e29a9df6149e07
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/770925
Reviewed-by: Randall Spangler <rspangler@chromium.org>
EC_IN_RW signal is used to determine if the switch to dev mode can be
safely made. However, EC_IN_RW needs the EC_RST_L line driven low in
order to be reset. In faft tests that utilize crosEcSoftrecPower
method, EC_RST_L is not being driven by servo to fix other test
failures related to keeping EC and AC reboots in sync.
This CL adds a new argument 'wait-ext' to the EC reboot command.
When this option is used, instead of the EC generating a reset via
it's system watchdog, it will wait 10 seconds for EC_RST_L to be
driven.
BUG=b:64603944
BRANCH=coral
CQ-DEPEND=I086687c3dd7591460099267880d56ab8265d2e4b
TEST=Ran "/usr/bin/test_that --board=coral <ip addr> firmware_DevMode"
mutliple times and verified that it passes. Previoulsy, this test
always fails when the EC is in RW before it starts. Also tested
platform_ServoPowerStateController_USBPluggedin and verified it passed.
Change-Id: I614f9156066d5719601ee43e29c7a064f9bba6e2
Signed-off-by: Scott Collyer <scollyer@google.com>
Reviewed-on: https://chromium-review.googlesource.com/737524
Commit-Ready: Scott Collyer <scollyer@chromium.org>
Tested-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
The original assembly code of deep sleep bypass will cause build error
if both CONFIG_LOW_POWER_IDLE and CONFIG_LTO are defined when buildiing
board glkrvp/zoombini. This CL fixed it by change the bypass assembly code
from:
asm ("push {r0-r5}\n"
"ldr r0, =0x100A8000\n"
"wfi\n"
"ldm r0, {r0-r5}\n"
"pop {r0-r5}\n"
"isb\n"
);
to:
asm ("push {r0-r5}\n"
"wfi\n"
"ldm %0, {r0-r5}\n"
"pop {r0-r5}\n"
"isb\n" :: "r" (0x100A8000)
);
BRANCH=none
BUG=none
TEST=No build errors for "make buildall".
TEST=build zoombini/glkrvp with CONFIG_LOW_POWER_IDLE and CONFIG_LTO,
no build errors.
TEST=build npcx7_evb/npcx_evb and do stress test for deep idle->wakeup
on EVB, no symptom observed.
Change-Id: I90b13b4baf418e3f4b3234d4811e3978b6436aac
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
Signed-off-by: CHLin <CHLIN56@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/756535
Commit-Ready: CH Lin <chlin56@nuvoton.com>
Tested-by: CH Lin <chlin56@nuvoton.com>
Add a common hook handler on CHIPSET_RESUME to log port80 resume
message instead of duplicating the same code in all chip lpc_resume.
BUG=b:68669668
BRANCH=None
TEST=Verified that port80 resume is logged on S0ix and S3 resume.
Change-Id: I313692f5499717d0d8f62be2ba3b8566c46e4dde
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/745362
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Add a new LPC helper routine lpc_resume_clear_masks that can be used
to clear SCI, SMI and wake masks upon resume from S3. This is done to
mask the events until host explicitly unmasks them.
It also ensures that these masks do not get reset on resume from S0ix
where the host does not re-configure these masks.
BUG=b:68669668
BRANCH=None
TEST=Verified following:
1. make -j buildall
2. On resume from S0ix, SCI mask is not reset.
3. On resume from S3, SCI mask is reset and then set again by host request.
Change-Id: I17a86bd60ef066b3716fb79ecce62f311eb45509
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/745533
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
According npcx ec wake-up mechanism by espi VW events, the driver
needs to make sure the IE/WE bits in VWEVMSn and the VWUPD bit in
ESPIWE registers are both set. Or ec won't wakeup by VW signals until
the other wake-up events occured. (WE bit of VWEVMSn is introduced on
npcx7.)
In this CL, we turn on IE/WE bit in VWEVMSn registers during espi driver
initialization and toggle the bits of ESPIWE register for VW and general
events such as ESPI_RST and so on when ec turn on/off host interface's
interrupts to make sure ec can wake-up from deep idle by espi events in
time.
BRANCH=none
BUG=none
TEST=No build errors for npcx5/7 series. Using "suspend_stress_test -c
1000" to do stress test and no symptom occurred on poppy. Both warmboot
and coldboot stress test for 5 hours and no symptom occurred on poppy.
Change-Id: I853532508bf9da5f3abc39e20ab848e659ca5e26
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/725559
Reviewed-by: Amit Maoz <amit.maoz@nuvoton.corp-partner.google.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
Also, fix uart_rx_available to only call
clock_refresh_console_in_use when the default pad is selected.
BRANCH=none
BUG=b:65526215
TEST=On Lux, EC console works, so does pad-switching EC-EC comm,
and idlestats shows that the EC goes to deep sleep.
TEST=In uart_alt_pad_write_read, increase usleep time in loop from
100 to 10000 (the shorter 100us time prevents EC from going
into deep sleep during the transaction), no transaction
error in EC-EC communication when system goes into deep sleep.
Change-Id: I3855b07f37def0ac9cfd700318ba64c432d3c42b
Signed-off-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/735103
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Define NPCX_UART_* macros instead of having so many ifdef
NPCX_UART_MODULE2 in the code.
Also, do not set NPCX_WKEDG bit in npcx_uart2gpio: instead
set it in uart_config just just like NPCX7 does it.
BRANCH=none
BUG=b:65526215
TEST=On Lux, EC console works, so does pad-switching EC-EC comm.
TEST=Flash soraka, using "idlestats", check that EC goes into
deep sleep, and that it can be woken up typing in EC console.
Signed-off-by: Nicolas Boichat <drinkcat@chromium.org>
Change-Id: I84b4f980fa79ed43640df4afc23cdc24cca21d99
Reviewed-on: https://chromium-review.googlesource.com/730029
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
NPCX5* only has one UART controller, which can be switched
between 2 pads. We keep the default pad for EC console,
however, we allow switching to the alternate pad for short,
infrequent, transactions. Both pads are assumed to use the
same baudrate and other line settings.
When switching pad, we first configure the new pad, then switch
off the old one, to avoid having no pad selected at a given time,
see b/65526215#c26.
Because of the added complexity of npcx_gpio2uart (and the fact
that it uses the global variable "pad" define in uart.c), we
move the implementation to uart.c (npcx_uart2gpio is also moved
for consistency).
When the pad is switched to alternate pad, characters input
and output on the EC console (default pad) would be lost. To
compensate for this, we:
- Switch back to main pad in case of EC panic, so that output
is shown on EC console.
- Immediately abort current alternate pad transaction if a
character is received on the default pad. Note, however,
that the first character will be lost (this can be worked
around by telling user to press enter, and have servod/FAFT
always send 2 blank lines (instead of just one) before
sending a command).
- Inhibit pad switching for 500ms after receiving a character
on default pad. Assuming a reasonable typing speed, this
should allow developers to type console commands relatively
comfortably, while not starving the alternate pad communication
for too long.
The logic above could be simplified significantly by implementing
software flow control (XON/XOFF, see b/67026316).
BRANCH=none
BUG=b:65526215
TEST=While follow-up CL that writes long 1k buffers, the following
works fine:
- type 'uart' in EC console
- Read battery power consumption from servod, which "types" in
the EC console:
while true; do dut-control ppvar_vbat_mw; sleep 1; done
no failure is seen.
TEST=Add this test code in uart_alt_pad_read_write, after the pad
has been switched, and check that panic information is
consistently printed correctly:
{
static int t;
if (t++ > 20)
t = t / ret;
}
Change-Id: I18feed2f8ca4eb85f40389f77dac3a46315310e7
Signed-off-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/659458
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Instead of duplicating the handling of host events and host event
masks in chip lpc drivers, add routines in common code to provide
basic functions like setting/getting of masks, setting/getting of
events and handling of masks transitions across sysjump.
BUG=None
BRANCH=None
TEST=make -j buildall. Verified following:
1. Event masks are correctly retained across sysjumps.
2. Wake from S3 works fine.
3. Wake from S0ix works fine.
4. SCI generated correctly.
Change-Id: Ie409f91b12788e4b902b2627e31ba5ce40ff1d27
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/707771
Reviewed-by: Shawn N <shawnn@chromium.org>
In npcx5, the flash interface pinmux should be turned on in order to
access the external flash. However, in npcx7, the internal flash is
used. It is meaningless to turn the pinmux on. And it also causes the
alternative function of these pins not work normally(such as
GPIOA0/GPIOA2) if the pinmux is enabled. This CL uses the preprocessor
flag NPCX_INT_FLASH_SUPPORT to conditionally prohibit the execution of
flash pinmux code.
BRANCH=none
BUG=none
TEST=No build errors for "make buildall". Build npcx_evb and npcx7_evb
boards, make sure the pinmux are correctly configured seperately.
Change-Id: Iba2300159f204b65d15852ec1755714df0c64816
Signed-off-by: CHLin <CHLIN56@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/704316
Commit-Ready: CH Lin <chlin56@nuvoton.com>
Tested-by: CH Lin <chlin56@nuvoton.com>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
When the host sets rtc alarm wake time = 0, it wants
to reset and disable the alarm.
Also, align the implementation in npcx with that in stm32
to check both delay_s and delay_us.
BUG=b:66971951, b:63908519
BRANCH=none
TEST='ectool rtcsetalarm 3'. After alarm goes off, run
'ectool rtcgetalarm' and then see 'Alarm not set'.
Change-Id: I693f1c72cba492e837891c716f79e2aa4da59b2a
Signed-off-by: Philip Chen <philipchen@google.com>
Reviewed-on: https://chromium-review.googlesource.com/691256
Commit-Ready: Philip Chen <philipchen@chromium.org>
Tested-by: Philip Chen <philipchen@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Brian Norris <briannorris@chromium.org>
In npcx7, we introduced a new bit, VWUPDW, in ESPISTS register to
indicate a Master-to-Slave VW signal was updated and the relevant WE
bit is 1. But there's no relevant IE bit in ESPIIE for VWUPDW, old
mechanism for clearing pending bits of ESPISTS will ignore this bit.
And ec cannot enter deep sleep anymore since this bit is set. This CL
fixed this bug by setting bit 17 of mask variable if ec is npcx7 series.
BRANCH=none
BUG=none
TEST=No build errors for npcx5/7 series.
Change-Id: I80c57d3c230e9d06ba134538ccdcd29f290bb7bf
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/672183
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Amit Maoz <Amit.Maoz@nuvoton.com>
In this CL, we introduced new bit fields of eSPI registers on npcx5/7
for the incoming patches. We also remove useless registers such as
VWGPMS, VWGPSM and PING in order to let the driver look more clearly.
This CL also includes:
1. Fixed typo from ESPIIWE to ESPIWE.
2. Introduce ESPIWE bits fields on npcx5/7.
3. Introduce new bit fields in ESPISTS of npcx7.
4. Remove useless VW1-4, VW1IE1-4 bits in ESPISTS and ESPIIE registes.
5. Introduce new bit field, WE, in VWEVMSn register of npcx7.
BRANCH=none
BUG=none
TEST=No build errors for npcx5/7 series. Using "suspend_stress_test -c
1000" to do stress test and no symptom occurred on poppy. Both warmboot
and coldboot stress test for 3 hours and no symptom occurred on poppy.
Change-Id: Ie8aa3dbd148588b0d9a756572d66604a6836a760
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/672026
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Amit Maoz <Amit.Maoz@nuvoton.com>
In order to prevent keeping the CSAE bit at 1 forever impacts the eSPI
performance, the npcx driver enables host access wakeup functionality
before ec enters deep sleep or wfi. But this bypass also should be added
in __idle() of core/cortex-m/task.c if CONFIG_LOW_POWER_IDLE is
disabled.
This CL also narrows the bypass only when host interface is eSPI.
BRANCH=eve
BUG=b:64730183
TEST=No build errors for make buildall. Disable CONFIG_LOW_POWER_IDLE
functionality on poppy and use following script "count=0; while :;
do echo "--- iteration --- $count"; time flashrom -p ec -r ec.bin; sleep
1; count=$((${count}+1)); done" to test eSPI performances over 300
times. No errors occur and all tests' efficiency are the same as
removing CSAE bypass.
Change-Id: I8b6b69e37318208c185747151c06b3e6bdfd2f4e
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/644967
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
