The corresponding bits in PCH_ADPA reflect the current state of the
connection and not a change in the state. This was interpreted wrong
since some PRMs state that these bits can be cleared. It seems they
can't be, though. Linux' i915 also doesn't try to clear them and only
interprets their state as presence of a display.
Change-Id: I8e8bfd30937f393e5c411b7d48668a4f5f7b0129
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/18167
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: Nico Huber <nico.h@gmx.de>
This is useful when we only want to probe for connected displays while
another entity currently controls the outputs.
Also introduce an `All_Ports` list, that can be used when it's unknown
which ports are actually implemented (the default now, when no port
list is provided to `Scan_Ports()`).
Change-Id: I5d8e289a907fe99c673084afbce54da65ba98e9c
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/18123
Tested-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
For cold plugging, we don't wait for a hot-plug event. But, even if we
are not supposed to wait for a hot-plug event, we have to clear any
pending event. Also, a failed DP training can result in another hot-plug
event.
A stale event would be spuriously interpreted as a disconnect, resul-
ting in an infinite loop of cycling the pipe on and off.
Change-Id: I4c7bbe0ac792553c94e928ba0a5eeb822a857f9c
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/18122
Tested-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
To support arbitrary configuration changes, we have to disable all
changed pipes first before we enable any new outputs.
Currently if an output moved from one pipe to another we might have
enabled it twice on different pipes.
Change-Id: Ibf601b8b5044aff4dd9e0a9c15cec20db6907aa5
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/18120
Tested-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Checking for hotplug events should be done before any other work to
reduce load and (spurious) debug output. Therefor, use the simpler
`Port_Type` in the interface of `Hotplug_Detect()` so we don't have to
fill the whole `Port_Cfg` before checking for events.
Also, now that it's possible, factor the disabling of a single output
out of `Update_Outputs()`.
Change-Id: I2a0ba5530c8d511fa95f9cac12297ad428a40d77
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/18119
Tested-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
The only time these settings are referenced is when we are about to
tear down a pipe. But we don't need the current state to do this. On
retraining due to a hotplug event, we start the whole configuration
again for simplicity. So we won't need it on that path either.
Change-Id: I01662e4a4a6150a0b05c57a016171fa3f0e7b93a
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/18117
Tested-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Shuffle things around to let the caller decide when to output the
settings. This removes spurious "DP" outputs for FDI configuration
which reuses the DP_Info infrastructure.
Change-Id: I9e6d6946002ef758b6c31f7de797dc6d329cae74
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/18116
Tested-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Split the transcoder setup out of `Pipe_Setup` into a new package
`Transcoder`. This comes closer to how Intel's manuals describe the
hardware.
Also rework the related constant definitions to make things more
human readable.
Change-Id: Ife0f0d635d87b874d4b713a00ca7a1bec688c672
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/17764
Tested-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Intel's manuals became much more clear with the years about what be-
longs to the transcoder and what to the pipe setup.
Although the transcoder is generally tied to a specific pipe, we
keep the naming of transcoder A, B, C which are mapped to the Primary,
Secondary, and Tertiary pipe respectively (with the exception of the
Haswell+ EDP transcoder which can be attached to any pipe).
Change-Id: I722786d318268c51ae2eaba9c108312f139165d8
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/17763
Tested-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
We chose the FDI-link settings too early, before we even set the
mode's BPC in case the default for an output should be selected.
This resulted in a too small lane count for the FDI in corner cases.
Change-Id: I12c6465c296bda4b7af116bd5a4c3d2ce593a3ac
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/18115
Tested-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
In Initialize(), the state of the graphics hardware is reset to a
known state (i.e. everything is turned off first). That's unnecessary
in the coreboot case where we just came out of reset. Thus, make the
state cleaning optional with a `Clean_State` parameter that defaults
to `False`.
Change-Id: Ifee6ec9e9876fca8a715684718014917a3e35879
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/17758
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Similar to
770fe4a gma: Use framebuffer size as pipe source size
we have to use the unscaled framebuffer size for the plane fetched
from memory.
Change-Id: I76cabdda5656982af2e8ff7cb67d2ad4a14a40a2
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/17748
Tested-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Adrian-Ken Rueegsegger <ken@codelabs.ch>
The panel power sequencer sometimes waits very long without an expli-
cable cause. We can however skip waiting for the panel power sequence
if we're already done with the configuration.
This fixes a sporadic, useless delay of about 130ms on the T420.
Change-Id: I27bf9b8bbae8a7447cde7ea4b88231b1707698b3
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/17760
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Before probing the internal panels EDID, we have to wait for the panel
power up delay. To use this time, we enable the panel power before pro-
bing any port and can probe external ports during the delay. On a T420
this saves about 5ms without an external display connected and 15ms
with.
Change-Id: Idce2ebbdb60182c9161e0a92ee4d42ff50c95688
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/17759
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
The GMA package has grown way too big. Move derivation of the internal
configuration into new package `Config_Helpers`, EDID probing into new
package `Display_Probing`.
Change-Id: Ib49ac7b00367be4295d18dba3afd1a0692e0497f
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/17757
Reviewed-by: Adrian-Ken Rueegsegger <ken@codelabs.ch>
Mostly renaming and some type tightening. Move the call to
Configure_FDI_Link() into Fill_Port_Config() as it's part of the
Port_Config.
Also start to document some procedures. The whole high-level con-
figuration is driven by non-obvious software-design choices, and
thus isn't self-explanatory even if you know the hardware.
Change-Id: Ib6a0893333e9359776140ed9de110f54cf36f6e5
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/17756
Reviewed-by: Adrian-Ken Rueegsegger <ken@codelabs.ch>
If an HDMI/DP display is detected, probe the sibling port that shares
physical pins too and bail out if something is detected. This is a
precaution for adapters that expose the pins of a port for both HDMI/
DVI and DP (like some ThinkPad docks). A user might have attached both
by accident and there are rumors of displays that got fried by apply-
ing the wrong signal.
Change-Id: I276ad55a353d60389bc36724d8af37b158ae4599
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/17755
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
DP and HDMI ports share physical pins. We can skip the probing of a
port if the other is already configured.
Change-Id: Iff2dcab969b607be900f8569affee5e1d288caba
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/17754
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Factor the probing of a single port's EDID out. Not only to save some
indentation levels but also to make it more flexible for later en-
hancements.
Change-Id: I063787ac42174a02e83e3d5ed93c033f16d3df7a
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/17753
Reviewed-by: Reto Buerki <reet@codelabs.ch>
We usually don't have the full Port_Config available when we want to
read the EDID. Also move this procedure one level up into GMA.
Change-Id: Ibdce83c6024d796c645dae6786c67206b5343402
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/17752
Reviewed-by: Reto Buerki <reet@codelabs.ch>
This procedure was never used to its full extent, afaict. It does too
much and that's barely tested. New code should be based on Scan_Ports().
Change-Id: I2367488f4b906a03a226313a41bf3d5f8dc4e6ef
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/17751
Reviewed-by: Reto Buerki <reet@codelabs.ch>
Before we had DP support, Digital just meant HDMI or DVI, but now it's
pretty confusing. Rename them to HDMI as it supersedes DVI.
Change-Id: Ie8b4c60ac60040aa5c725ffc9cd06aa164391756
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/17750
Reviewed-by: Reto Buerki <reet@codelabs.ch>
This was long overdue. Originally, we only had one type of `confi-
guration` but those times are over. Thus, rename `Config_Type` to
`Pipe_Config` along with `Configs_Type` to `Pipe_Configs` and
`Config_Index` to `Pipe_Index` to give them more meaningful names.
Change-Id: Ic02c738f51b01a883e05eff1c94f9c2d6058fdc4
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/17749
Reviewed-by: Reto Buerki <reet@codelabs.ch>
Some devices fail to transmit the EDID header pattern correctly. To
compensate, we patch EDID header patterns when at least six out of
the eight bytes match. We then verify the checksum over all bytes
including the patched header.
Linux does it similar and gets more displays up that way, sigh.
Change-Id: Ic63880a05e64f40dfda165bd54e708cd981f08fb
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/17493
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
In some configurations (e.g. textmode) we know that we'll only enable
a limited number of pipes. So let's skip additional port probing in
Scan_Ports() that would only waste time otherwise.
Change-Id: I496e84cfe8bb170a6b500f64461db4c837c439fd
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/17278
Tested-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Given that current Intel chips only support 4K@30Hz over HDMI, it's
actually no surprise that older chips had even lower limits. For a
24bpp mode, it's 225MHz for Nehalem, Sandy and Ivy Bridge and 300MHz
for everything newer.
To keep the code most simple we keep the display's native resolution
and just limit the clock if we encouter an unsupported mode.
TEST=Booted T420 with a DELL U3415W attached over DP-to-HDMI and
DVI-to-HDMI adapters. The display came up with 3440x1440@42Hz
(instead of a garbled picture at 1720x1440@60Hz).
Change-Id: I5386386c648db267a49ed1f62750d2a5fdb2d934
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/17499
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Add special VGA_PLANE_FRAMEBUFFER_OFFSET that, if set on the primary
pipe, toggles the use of the legacy VGA plane instead of the `hires`
plane.
The caller is responsible for the configuration of the VGA plane and
has to specify the framebuffer width and height accordingly.
Change-Id: I9f678fe033d835c9183fbb2d2b05b6585eb545ca
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/17276
Tested-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
If the framebuffer size is smaller than the display mode's resolution,
enable the panel fitter or pipe scaler (on Skylake+).
Change-Id: I0a648a7e7bf495a80636a589a74b698ecba7e7d5
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/17263
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: Nico Huber <nico.h@gmx.de>
Now that we are going to use scaling and have framebuffer sizes dif-
ferent from the display mode's resolution, it's crucial to put the
right size (i.e. the unscaled framebuffer size) into PIPESRC.
Change-Id: Ieb4b5c3960490e286d44c982c28f7ff729ecd84b
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/17264
Tested-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
When deciding if a pipe has been configured, we only checked if reading
the EDID succeeded not if it contained usable data.
TEST=Booted kontron/ktqm77 with a DVI-I to VGA cable and the display
came up (it didn't before because of a gap in the pipe config, i.e.
the second pipe was disabled so coreboot didn't bother to look at
the third).
Change-Id: I10075db8916efcee68be95971145c3f6f1530e5a
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/17087
Tested-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Boards with a DVI-I connector share the I2C pins for both analog and
digital displays. In that case, the EDID for a VGA display has to be
read over the I2C interface of the coupled digital port.
TEST=Booted kontron/ktqm77 with DVI-I to VGA cable. Display is detected
and enabled (but doesn't show anything, yet?).
Change-Id: I5c4f77d5ad1927f075877a3719361ed2193f4c39
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/17086
Tested-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This setting exists for any platform before Skylake. Some have sane
defaults after reset, some don't. So we always set the correct divisor.
This makes external DP output work with coreboot on Ivy Bridge.
Change-Id: I91d8030a985cc35c7cf826c0276753137b5d6b77
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/17072
Tested-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
This seems to be a scratchpad register to tell later drivers which
frequency the platform uses. Linux reads this but never writes the
register.
Change-Id: I55af7c7b675da580c7f52d9997262b232019132c
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/17071
Tested-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
