charge_manager may request a charge current limit less than the
capability of the supply in certain cases (eg. during PD voltage
transition, to make an effort to comply with reduced load spec).
Depending on the battery / system state, setting a reduced charge
current limit may result in brownout.
Pass the uncapped / max negotiated current to board_set_charge_limit()
so that boards may use it instead of the requested limit in such
circumstances.
BUG=chrome-os-partner:56139
BRANCH=gru
TEST=Manual on kevin with subsequent commit, boot system with zinger +
low-charge battery, verify devices powers up to OS without brownout.
Change-Id: I2b8e0d44edcf57ffe4ee0fdec1a1ed35c6becbbd
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/383732
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
AL3010 is Dyna-Image ambient light sensor.
Here is add basic driver and functions.
BUG=chrome-os-partner:52915
BRANCH=elm
TEST=Flash on base board "glados" with ASUS
al3010_init is return success.
al3010_read_lux is return the lux success.
Change-Id: Ie3b97d0889b150c43d19bc84d84f04c13e415c31
Signed-off-by: Rocky Hsiao <rocky.hsiao@dyna-image.com>
Reviewed-on: https://chromium-review.googlesource.com/356874
Reviewed-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-by: Thomas Lin <thomas.lin@dyna-image.com>
If the host sends a back to back I2CS write followed by a read of the
access register, then the read IRQ can be missed by FW because it was
clearing this bit at the end of the ISR. This would result in a
following write to have the incorrect number of bytes since the
address register byte from the read that wasn't processed gets left in
the HW write fifo.
BRANCH=none
BUG=chrome-os-partner:40397
TEST=manual
The issue was happening at the beginning of depthcharge. Without this
fix, I would see the Cr50 console message:
'data size mismatch for reg 0x0 rx 2, need 1'
After moving the IRQ clear could not reproduce this message. In
addition, the debug I2CS log showed that there was a read transaction
immediately following the write.
Change-Id: I9854dde6880a789e0acb2b1f6a06b43c73a5a2df
Signed-off-by: Scott <scollyer@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/382687
Commit-Ready: Scott Collyer <scollyer@chromium.org>
Tested-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
In the initial design multi-byte registers were being converted to
network byte order and so there was reason to treat 1 byte and 4 byte
register reads differently. However, since the conversion to network
byte order is not being done, there is no reason to treat these cases
differently outside of the number of bytes to read.
BRANCH=none
BUG=chrome-os-partner:40397
TEST=manual
Reboot Reef and verify that TPM is working in coreboot
coreboot-coreboot-unknown.9999.fbbcb2d Thu Sep 8 19:41:15 UTC 2016
LPSS I2C bus 2 at 0xfe022000 (400 KHz)
tpm_vendor_probe: ValidSts bit set(1) in TPM_ACCESS register after 5 ms
I2C TPM 2:50 (chip type cr50 device-id 0x28)
setup_tpm():404: TPM: SetupTPM() succeeded
src/lib/tpm2_tlcl.c:179 index 0x1007 return code 0
Change-Id: If74c432136c02d334e0d58d16dc817d7773b0584
Signed-off-by: Scott <scollyer@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/382688
Commit-Ready: Scott Collyer <scollyer@chromium.org>
Tested-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
By this time hopefully all old hardware has been junked. Take out the
old code to check for old hardware to save a little bit of space, since
space is tight.
BRANCH=gru
BUG=chrome-os-partner:55561
TEST=Build and boot
Change-Id: I9b147a8c1955e1c2c3fee3dd6ab7fc6e520be4bf
Reviewed-on: https://chromium-review.googlesource.com/384452
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Simon Glass <sjg@google.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
This reverts commit 1966433427.
The CL seems to break USB ethernet dongles (and maybe other USB
functionality). Reverting for now so development isn't impacted.
BUG=chrome-os-partner:57310
BRANCH=gru
TEST=check that usb ethernet works after booting on kevin
Change-Id: I91d05da65d56afcd8a21ac2074a31f759c4aaec8
Reviewed-on: https://chromium-review.googlesource.com/383862
Commit-Ready: Douglas Anderson <dianders@chromium.org>
Tested-by: Douglas Anderson <dianders@chromium.org>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
LID_OPEN gpio is interrupt trigger on both the edge. If the system is
hibernated when LID is open and then LID is closed, system wakes from
hibernation. Hence setting the LID_OPEN GPIO as interrupt raising before
hibernation so that system won't wake up upon LID close in hibernation.
BUG=chrome-os-partner:57221
BRANCH=none
TEST=Issued hibernate when LID is open, closed the LID after hibernation
observed system won't boot back till LID is open again.
Change-Id: Idc89c3d85b7d246c3e18d0ced48e7d47bebeafec
Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/383753
Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
There is leakage on SYS_RST_ODL from the internal pullup cr50 has on
DIOM0. This change removes the internal pullup on reef.
On Kevin there is a bug preventing the EC from being able to pull
sys_rst_l up high enoug for cr50 to detect that it is pulled high. This
change adds an internal pullup back when cr50 detects that it is on a
kevin or gru.
BUG=chrome-os-partner:56945
BUG=chrome-os-partner:53544
BRANCH=none
TEST=On gru and kevin remove servo verify when apreset is run on the EC
it resets cr50 and the AP. Run pinmux and check that there is a pullup
on diom0 on kevin but not on gru.
Change-Id: Ica4f557745967b93e0bd9c8462916b1f735756ac
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/381322
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
This changes how tpm_register_put() debug messages are displayed
to show only the bytes that are sent instead of some
uninitialized bytes as well.
BUG=none
BRANCH=none
TEST=make buildall; run on Cr50 hardware
On the console, run
chan -1
to enable displaying the debug output.
Before this CL, you'd see messages like this:
tpm_register_put(0x024, 21 180)
tpm_register_put(0x024, 1 17f)
tpm_register_put(0x018, 1 120)
tpm_register_put(0x018, 1 140)
Afterwards, you'd see accurate messages:
tpm_register_put(0x024, 21, 80 01 00 00 ...)
tpm_register_put(0x024, 1, 01)
tpm_register_put(0x018, 1, 20)
tpm_register_put(0x018, 1, 40)
Change-Id: Iad798804a4b6060e9bfafad50c90138eb1144c8f
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/382664
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
All PIN() assignments in board/$BOARD/gpio.inc must be unique,
since otherwise you're just creating duplicate names and table
entries for the same core interrupt and may not be initializing
things the way you think.
BUG=none
BRANCH=none
TEST=make buildall; test on Cr50 hardware
Also verified that the image size is exactly the same before an
after this CL.
Change-Id: Ifb1805a010905f67fc5c0d246b6252af73715409
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/383773
Reviewed-by: Randall Spangler <rspangler@chromium.org>
On different systems SYS_RST may be edge triggered, so it is not
guaranteed holding it low will hold the AP in reset. With this change,
enable_ap_spi now holds the EC in reset, so it is guaranteed the AP is
in reset.
BUG=chrome-os-partner:54982
BRANCH=none
TEST=run 'sudo flashrom -p raiden_debug_spi:target=[EC|AP] --flash-name'
on gru, kevin and reef
Change-Id: I3176462b932eba5bf8d69dbab70500bca8c7ff46
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/380484
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
For kevin, we are not using the PROCHOT# signal for the charger so we
can enable a power save mode. This commit will leave BGATE on but
without monitoring the PROCHOT# signal. When VBUS or VCC is removed
from the charger, the charger will enter this power save mode. It will
return to normal functionality when VBUS or VCC is applied.
BUG=chrome-os-partner:55631
BRANCH=kevin
TEST=Flash kevin; Verify we can still charge; Verify that power
consumption is less with this patch applied than without.
CQ-DEPEND=CL:382877
Change-Id: I05274a770b35c981e0541d8f79f66b81ffb4d153
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/383391
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
The BD99956 charger has a power save mode that it can enter once VBUS or
VCC is removed. This commit adds an optional config option that can be
used to select the power save mode:
CONFIG_BD99955_POWER_SAVE_MODE
By default, no power save mode will be enabled. However, a board can
device what level of power savings they wish to use.
The levels are the following:
BD99955_PWR_SAVE_LOW /* BGATE ON w/ PROCHOT# monitored only system
* voltage. */
BD99955_PWR_SAVE_MED /* BGATE ON w/ PROCHOT# monitored only system
* voltage every 1ms. */
BD99955_PWR_SAVE_HIGH /* BGATE ON w/o PROCHOT# monitoring. */
BD99955_PWR_SAVE_MAX /* BGATE OFF */
BUG=chrome-os-partner:55631
BRANCH=kevin
TEST=make -j buildall
Change-Id: Ibab7ad30d5f1ae9917b46b40d6f2800ef19e52dd
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/382877
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
Enable interrupt from BMI160 for FIFO control.
It can be use for significant motion detection.
BRANCH=kevin
BUG=b:28552512
TEST=Pass CTS tests SensorBatchingTests, SingleSensorTests
To trigger FIFO interrupt during the batch tests, EC lid angle
calculation is disabled from the EC with "acclerate 0 0"
Change-Id: I3ed4afcdee7075c5e5e20974d70a9e6bd64ecd52
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/382677
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Allow the detection of tablet mode for sensors and powerd.
BUG=chromium:606718,b:28552512
BRANCH=kevin
TEST=Check with evtest that events are send.
Check sensor data is in lid referal in tablet mode.
Change-Id: I0822e7419ccba01d70bf9327593164c15493fb10
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/380377
Reviewed-by: Randall Spangler <rspangler@chromium.org>
When tablet mode is detected, send an event to the AP.
BUG=chromium:606718
BRANCH=none
TEST=Check with evtest that events are sent when the tablet goes in tablet
mode and back to device mode.
Change-Id: I49f2404b5ecf87e71fa5aef4c8ce9c9beda26a15
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/380414
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
User of sensor data can use tablet mode to rotate the sensor datums
along the X axis.
This is useful on Kevin where we gather base data.
When the base is behind the lid, the datums needs to be rotated by 180
to be in the lid referential.
BUG=b:27849483
BRANCH=none
TEST=check the sensors changes when kevin is in tablet mode.
Change-Id: I60147600f534df0770a44b5158ef8afe87d9dd9d
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/380413
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Using the lid angle, detect if we are in tablet mode or not.
We are in tablet mode when the lid angle is large enough:
tablet_mode:
1 | +-----<----+----------
| \/ /\
| | |
0 |------------------------>----+
+------------------+----------+----------+ lid angle
0 240 300 360
BRANCH=kevin
BUG=chrome-os-partner:55702,b:27849483
TEST=Check on Kevin event are sent on tablet mode transition.
Change-Id: Id9935ce4dd717e2c20fa6c9520defb504a1760d9
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/383073
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
When lid is closed, the lid angle can move to 358, 360, 0, 359 ...
Prevent transition 0 from/to 360 by keeping the last calculated value.
BRANCH=kevin
BUG=chrome-os-partner:55702
TEST=Check transition does not happen anymore.
Change-Id: Ifa8415470f425c893e2c3662c84c8fd0156e0524
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/373040
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
There is no point in waiting for a reset to clear the fallback
counter, it can be cleared as soon as USB update is finished.
BRANCH=none
BUG=chrome-os-partner:56864
TEST=on a kevin-tpm2 device: set the reset counter to 7 by running
> rw 0x40000128 1
> rw 0x4000012c 7
on the cr50 console. Then try uploading a new RW image over Suzy-Q
and verify that it is running after reset.
Then verify that cr50 can still be updated
Change-Id: I098a87c48b2fe864143715b1e90d4bb2409b9eae
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/383077
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
This makes minor changes to GPIOs for the next build:
- USB_C0_PD_RST_L is actually push-pull in next build, so remove the
comments about USB_C0_PD_RST_ODL.
- Added TABLET_MODE
- Make the net name for volume up/down buttons match the name in the
schematic.
BUG=none
BRANCH=none
TEST=built and booted on Reef EVT
Change-Id: I0799de059d71809174e246b6bbd7f3a2fe25686a
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/381791
Reviewed-by: Shawn N <shawnn@chromium.org>
This adds support for the GD25LQ40 NOR flash chip which is identical
to W25Q40 for the purposes of write-protection support for the ranges
that we care about.
BUG=chrome-os-partner:57015
BRANCH=none
TEST=needs testing
Change-Id: I09ad02e04fab4c539b9558180d73bf6c31da6aed
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/382641
Reviewed-by: Shawn N <shawnn@chromium.org>
Sanity tested by powering up cr50 and checking for correct RBOX
register values.
This patch is mainly to address RBOX debounce issues and key blocking
while EC_RST is asserted. A debounce value less than 4, sometimes
causes initial pin values to be incorrectly detected. The latter is
related to https://chromium-review.googlesource.com/#/c/357590/.
As RBOX controls cannot be selectively bypassed (they have to be
bypassed as a group), all registers are set up in this patch
BUG=chrome-os-partner:54602
BRANCH=None
CQ-DEPEND=CL:377621
TEST=manual on Kevin
Do three-finger salute, enter recovery mode.
Change-Id: Ieb82c94fa33888ead359a77bf77981567998b3fc
Signed-off-by: Timothy Chen <timothytim@google.com>
Reviewed-on: https://chromium-review.googlesource.com/372001
Commit-Ready: Bill Richardson <wfrichar@chromium.org>
Tested-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
Data from the sensor (in Pa) does not fit in 16 bits.
Add set_range/get_range to allow the AP to set the precision.
For pressure around ~1000 hPa, we need to right shift by 2 bits.
BUG=chrome-os-partner:57117
BRANCH=reef
TEST=Check data is not truncated anymore:
> accelrange 4
Range for sensor 4: 262144 (Pa ~= 2621 hPa)
> accelread 4
Current data 4: 24030 0 0
Last calib. data 4: 24030 0 0 (x4 = 961.2 hPa)
Change-Id: I3f7280336e5120d903116612c9c830f4150d2ed7
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/382323
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
TTC must be written twice, otherwise the value will be lost on EC reset,
even if VBAT stays stable.
BUG=chrome-os-partner:57010
BRANCH=None
TEST=On kevin, run 'rtc set 55555' then trigger cold reset through
servo. Run 'rtc' on subsequent boot and verify timing ticks did not
reset to zero.
Change-Id: If05b698e75eece5f8879a109b98886b547eb71a4
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/382654
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
The CTR was set to 1 less than the max PWM value, so when the DCR
is set to max PWM value, duty goes to zero. The bug is fixed by
setting CTR to PWM max vlaue.
BUG=chrome-os-partner:57052
BRANCH=None
TEST=Manual on terminal.
> pwmduty 1 raw 0
Setting channel 1 to raw 0
1: disabled
> pwmduty 1 raw 65535
Setting channel 1 to raw 65535
verified that screen didn't blank
Change-Id: I10885d382f1bd252a5e7355da99dc00bd876e29f
Reviewed-on: https://chromium-review.googlesource.com/381632
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
We often find it handy to build test images that are unlocked or
have special powers. To avoid confusing these with production
images, this adds a "DEV/" to the version string:
"make BOARD=cr50" looks like this:
> version
Chip: g cr50 B2
Board: 0
RO_A: * 0.0.9/0088a3eb
RO_B: 0.0.8/710d4375
RW_A: * 0.0.6/cr50_v1.1.5261-4848d7e
RW_B: 0.0.6/cr50_v1.1.5261-4848d7e
[...]
"CR50_DEV=1 make BOARD=cr50" looks like this:
> version
Chip: g cr50 B2
Board: 0
RO_A: * 0.0.9/0088a3eb
RO_B: 0.0.8/710d4375
RW_A: 0.0.6/cr50_v1.1.5261-4848d7e
RW_B: * 0.0.6/DEV/cr50_v1.1.5261-4848d7e
[...]
BUG=chrome-os-partner:55557
BRANCH=none
TEST=make buildall; also..
Build both with and without the CR50_DEV=1 environment variable.
Observe that the version string differs even if nothing else
does.
Change-Id: Ifee9fbf922c2bbb40a1a9d0a716d2d11aa0d3ec2
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/382851
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
In order to improve the performance of sysjump, the CL increases the clock
freq of ec to 50M HZ (The maximum freq rate for SPI flash.). Once ec jumps
into the other region successfully, the clock freq is restored to the
default value (15MHz) in main routine.
Modified sources:
1. clock.c: Add clock_turbo for speed up clock's freq to max.
2. clock_chip.h: The declarartion for clock_turbo.
3. system.c: Speed up clock rate before downloading FW.
BRANCH=none
BUG=chrome-os-partner:34346
TEST=make BOARD=npcx_evb; test nuvoton IC specific drivers
Change-Id: I996e35fff336e6292599497feb1ee6c2f95becba
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/381799
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Input to the EC UART console is restricted by default so that
casual passers-by can't type random commands to it through the
case-closed debug connection. However, there's no need to
restrict the AP UART console, since it's entirely under the AP's
control.
This CL leaves the AP console enabled by default whenever the CCD
cable is connected. It will be disabled when the AP is powered
down or while servo is attached, but enabled otherwise.
BUG=chrome-os-partner:55322
BRANCH=none
TEST=make buildall, test on Cr50 hardware
Use the "ccd" command to see and modify the UART console
settings, and the "devices" command to observe how things change
when servo is connected and things are powered up and down.
Change-Id: I5cc453bc60473269e22112cf49f61495733abb10
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/382152
Commit-Ready: Bill Richardson <wfrichar@google.com>
Tested-by: Bill Richardson <wfrichar@google.com>
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
Add a hook to act when the a device is going in tablet mode and back.
BUG=chromium:606718
BRANCH=kevin
TEST=Test with evtest that an event is sent to the AP.
Change-Id: Ic9c3b158f1178504af41abff18b28de8e07fc7a7
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/380412
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
We don't really have the ability to build the latest signer yet, but
this should not stop us from being able to build a properly signed
image using the ec makefiles.
As a stopgap measure the suggestion is to keep the latest signer
binary in ~/bin/codesigner in chroot, then with this patch applied
invoking make with CR50_DEV=1 will cause the proper sighner used and
proper signing procedure followed.
The signed targets need to be built in series to avoid concurrent use
of the signer fob, an addition dependency is being added to enforce
that.
BRANCH=none
BUG=chrome-os-partner:55557
TEST=ran make as follows:
CR50_DEV=1 make BOARD=cr50
touched the fob when requested, uploaded the generated
build/cr50/ec.bin on a kevin-tpm2 using usb_updater, and observed
it boot properly with the new version.
Change-Id: Ia9494bdc60b4bd3b8e5e09cbcbd8b27409c739d2
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/376885
Tested-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
Enabled the trickle charging mode by setting the VPRECHG_TH_SET
register[0x18H] to board specific battery voltage minimum value.
When the battery voltage drops below the battery voltage minimum
value, trickle charging is enabled.
BUG=chrome-os-partner:56684
BRANCH=none
TEST=Manually verified on Reef. Drained the battery below battery
voltage minimum value. On plugging in the charger, State
Machine Status register CHGSTM_STATUS [0x00h] is 0x01 which
indicates, current state of the charger state-machine is in
Trickle-Charge condition.
Change-Id: Ic4b985c71ff68ea4f5ab22e18feab03d776ec134
Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/376939
Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
To be able to parse binary panicinfo from feedback reports, we need
a host tool:
- Move panicinfo generic parsing functions to a separate C file
- Create a new host utility to parse panicinfo
BRANCH=none
BUG=chromium:643062
TEST=base64 -d | ec_parse_panicinfo
Change-Id: Idd8560a2894f270d0ab3a9f654c333135759e57f
Reviewed-on: https://chromium-review.googlesource.com/379639
Commit-Ready: Nicolas Boichat <drinkcat@chromium.org>
Tested-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
