RDD is working reliably and defaulting to CCD makes it difficult to
display port functionality.
BUG=chrome-os-partner:52281
BRANCH=none
TEST=manual
run 'reboot ap-off' on the EC. Plug in a unreworked suzyq and
verify 'lsusb | grep 5014' doesn't show any devices
run 'powerbtn' on the EC and verify 'lsusb | grep 5014' now
shows a device.
Check that this works on gru, kevin, and reef.
Change-Id: If4a9fc2f8f874e602c28f8e397c9bf8ea6184b59
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/360914
Reviewed-by: Bill Richardson <wfrichar@google.com>
Having DIO A4, A8, and A14 connected to the spi master output pads
prevents reef from booting. We need to tristate those pins when spi ccd
is not in use.
This change disconnects those pins from the spi peripheral when spi is
disabled and reconnects them when spi is enabled.
BUG=chrome-os-partner:53582
BRANCH=none
TEST=manual
use 'pinmux' to verify DIOA4, DIOA8, and DIOA14 are set have
GPIO 7, 8, and 9 as their output sources when not using the usb
spi interface.
Check the usb spi interface still works.
Enable usb spi then disable ccd and check that the pins are
connected back to the non-peripheral gpios.
Verify the AP on kevin and reef can be flashed using servo.
Verify the AP boots successfully on both.
Change-Id: I85d70422a30da445076432d2bfc81960aeba8578
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/357883
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
When the debug cable is disconnected the a USB suspend interrupt is
triggered and puts the chip to sleep before rdd can detect a change on
the cc lines and disconnect from CCD. This prevents the DEBUG_STATE_MAP
from being reset to detect the debug connect and is left detecting the
disconnect. Since the debug accessory is already disconnected the RDD
interrupt will wake up the chip right after it goes to sleep.
The UTMI and PIN wake source still cause the chip to wake up before the
RDD interrupt, so disable those to test this change.
BUG=chrome-os-partner:54796
BRANCH=none
TEST=Disable wake pin and utmi wake sources. Put cr50 to sleep. Attach a
reworked suzy q and make sure cr50 wakes up. Detach it and check that it
goes back to sleep. Do that a couple of times. Check CCD is still
enabled when the debug accessory is detected and disabled on
disconnect.
Change-Id: I58a012895bc874dcdd512aa84de9a917469f3139
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/360234
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
When the uart rx signal is not externally pulled high by the EC or AP,
the low rx signal triggers thousands of uart interrupts. At
initialization Cr50 does not know the state of those devices. If the
uart is initialized when the device is off these interrupts may prevent
Cr50 from booting on certain boards. This change does not enable the
uart until the device state is know. When the device state monitoring
detects that the AP or EC is powered on it will enable uart 1
or 2 and when it detects that it is powered off then the uart will be
disabled.
BUG=none
BRANCH=none
TEST=UART_CTRL registers are set to 0 for uart 1 and 2, and are changed
to 3 when the device state is on.
Change-Id: I43e847c6abb8507a86de92a5c226a79f3add7f97
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/360026
Reviewed-by: Scott Collyer <scollyer@chromium.org>
The bit IRQ11B of register HIIRQC is meaningful only when PM Channel 1
is in PC87570-Compatible. In previous commit, we deprecate use of
PC87570 mode but set the bit unintentionally. This will not cause any
bug but may make confused when reading the code.
Modified sources:
1. lpc.c: CLear IRQ11B in register HIIRQC.
BUG=chrome-os-partner:34346
TEST=make buildall -j; verify on Wheatley
BRANCH=none
Signed-off-by: CHLin <CHLIN56@nuvoton.com>
Change-Id: I594222c29557add847a1f689859fdf558d64fdd3
Reviewed-on: https://chromium-review.googlesource.com/358536
Commit-Ready: CH Lin <chlin56@nuvoton.com>
Tested-by: CH Lin <chlin56@nuvoton.com>
Reviewed-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-by: Amit Maoz <Amit.Maoz@nuvoton.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
If the UART0 RX pad is not pulled up, cr50 will get held up on all of
the interrupts triggered by the low signal. This causes cr50 to reboot
continuously. UART0 RX was moved to DIOA13, which does not have an
internal pull up. This means we have to rely on an external pull up.
Because not having an external pull up on DIOA13 could prevent the
system from booting and UART0 RX is only used as an alternate debugging
mechanism from suzyq, we decided it is best for UART0 RX to be disabled
by default.
BUG=none
BRANCH=none
TEST=Connect UART1_RX to DIOA1 and test that it still accepts input.
Disconnect it from any pads. Verify the system boots normally and
console input from DIOA1 no longer works but the suzyq shell still does.
Change-Id: I68988c59cfce610cc6c360bf8dd9685e98ab12ff
Reviewed-on: https://chromium-review.googlesource.com/357881
Commit-Ready: Mary Ruthven <mruthven@chromium.org>
Tested-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-by: Scott Collyer <scollyer@chromium.org>
Board initialization function configures certain RBOX registers, but
RBOX initialization runs at the same priority as board initialization,
and as such is not guaranteed to run in time.
Reducing RBOX initialization priority guarantees that RBOX is
initialized by the time board init function needs to access it.
BRANCH=none
BUG=chrome-os-partner:49959
TEST=the AP_WP_L signal now reports the expected value:
> gpioget AP_WP_L
1 AP_WP_L
>
Change-Id: I9c29451a08fc47d3409031bda1a936de243c0c70
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/358169
Tested-by: Brian Norris <briannorris@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
This patch replaces a long standing stub. When the EC asserts this
signal, the CR50 must reset.
But this signal could be driven by CR50 itself as well, and in that
case the signal's assertion should not be causing the CR50 reset.
Ideally it should be possible to tell if the pin is configured as
output and ignore its assertion in that case. But there is no API for
checking the pin configuration settings at this time. An API function
is added to check if the AP Flash is being programmed, the GPIO
configuration access API is left for future enhancements.
BRANCH=none
BUG=chrome-os-partner:52366, chrome-os-partner:54982
TEST=issue 'reboot' command from the bash command line.
- verify on the cr50 console that it reboots along with the rest of
the device
- observe that reading of the NVRam spaces is still fully
functional, and Kevin can boot all the way up to the login
screen.
- try flashing AP firmware through CR50, verify that it succeed.
Change-Id: Ie4506238dc8b158b32121719a2db7fd232fd7d6c
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/357967
Reviewed-by: Shawn N <shawnn@chromium.org>
In NPCX5m5g/NPCX5m6g, PM channel 1 can support both
PC87570-Compatible and enhcnced mode. In next generation of chip,
only enhanced mode will be supported. Set the enhanced mode as
default in the firmware to support all gereration of chips.
BUG=chrome-os-partner:34346
TEST=make buildall -j; verify on Wheatley
BRANCH=none
Change-Id: Ide9e17a1fe8a0d2bfdc33efe2336a10702660679
Signed-off-by: CHLin <CHLIN56@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/357752
Commit-Ready: CH Lin <chlin56@nuvoton.com>
Tested-by: CH Lin <chlin56@nuvoton.com>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Mulin Chao <mlchao@nuvoton.com>
The modexp implementation occasionally produces
a result larger than the modulus, in which case a
single final reduce is required. The software
based implementation already has this check.
BRANCH=none
BUG=chrome-os-partner:43025,chrome-os-partner:47524
TEST=tpmtest.py passes
Change-Id: I0a830781e2a109963394d0702cbc2ca6457c410c
Signed-off-by: nagendra modadugu <ngm@google.com>
Reviewed-on: https://chromium-review.googlesource.com/357010
Commit-Ready: Nagendra Modadugu <ngm@google.com>
Tested-by: Nagendra Modadugu <ngm@google.com>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
SHI_OBUF_VALID_OFFSET may wrap on buffer full, leaving us with an
incorrect tally of bytes transmitted. Always assume the worst case, that
SHI_OBUF_VALID_OFFSET is at maximum, when deciding to apply 256B bypass.
BUG=chrome-os-partner:54566
BRANCH=None
TEST=Manual on gru. Verify 'flashrom -p ec -r read.bin' does not produce
CRC errors.
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: I7c0ccc1b555838854584a3be8ced50057eaea961
Reviewed-on: https://chromium-review.googlesource.com/356771
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shelley Chen <shchen@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Mulin Chao <mlchao@nuvoton.com>
If SHI finds itself in an unexpected state, we may try to print an error
message for each IBF / IBHF interrupt, which is excessively spammy and
may even lead to EC watchdog. Avoid console spam by not duplicating IBF
/ IBHF / IBEOR error prints, if our state doesn't change.
BUG=chrome-os-partner:54502
BRANCH=None
TEST=Manual on gru. Verify only one print is seen when SHI fails due to
missed initialization.
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: I331c64c24fa3a68d7c17e052240691076d3532cc
Reviewed-on: https://chromium-review.googlesource.com/356239
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
The highsec jittery clock was breaking the USB peripheral, because it
would use bank values that mapped to frequencies less than 15MHz. This
change modifies stepx16 to keep the bankvalues mapped to frequencies
above 18MHz to ensure the USB peripheral can work with the high
security jittery clock.
BUG=chrome-os-partner:53952
BRANCH=none
TEST=sudo flashrom -p raiden_debug_spi:target=AP -r test_img.bin
Change-Id: If8b45583f2cd9272b6d1e79a06556724c25d6495
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/356192
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
When the Cr50 doesn't have anything else to do and it's been a
while since anyone has communicated with it (10 seconds via UART,
1 second via SPI, and the USB bus has stopped sending SOF
packets), it enters one of three idle states:
wfi = fully powered, just waiting for an interrupt.
sleep = low power mode, but RAM is preserved. It resumes quickly.
deep sleep = hibernate. RAM is lost, resume is a warm boot
You can get/set the idle state with the "idle" console command.
BUG=chrome-os-partner:49955,chrome-os-partner:54331
BRANCH=none
TEST=make buildall
To test it:
* I've only tested on the debug board, because I need a serial
console (not serial-over-USB) to see if it's asleep or not.
* I haven't been able to knowingly force USB Suspend on my
workstation, so to fake it I just unplug the USB cables.
* Wait 10-12 seconds after typing anything on the serial console,
then press a key. If the Cr50 was asleep, the first character
will be lost. If it wasn't, you'll see the character echoed
immediately.
Change-Id: Icc213e50b0c38f8c2b16bcd9960e2e5550b43180
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/356123
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
We need to write 0 to RBOX_WAKEUP_CLEAR after writing 1 to clear the
rbox wakeup registers.
BUG=none
BRANCH=none
TEST=after init verify 'rw .h 0x40550098' returns 0
Change-Id: Id7eda45f443300e77f293556eece72d52ca28f17
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/355283
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-by: Hsiao-heng Lee <kelinlee@google.com>
Adding ability to get # seconds before rtc alarm
goes off.
BUG=chrome-os-partner:52218
BRANCH=None
TEST=ectool rtcgetalarm w/o setting returns
Alarm not set.
ectool rtcsetalarm 30; ectool rtcgetalarm
to make sure counting down to 0. After alarm
goes off, rtcgetalarm should return alarm not
set again.
rtcsetalarm 30; rtcgetalarm to check alarm is set.
rtcsetalarm 0; should disable alarm. Use
rtcgetalarm to ensure that alarm is disabled.
Change-Id: I176b12fe2dda08eedd23ea33dc64785f09f1d9ae
Signed-off-by: Shelley Chen <shchen@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/353331
Reviewed-by: Shawn N <shawnn@chromium.org>
We have no guarantee about the alignment of our input buffer so don't
use 32-bit access.
BUG=chrome-os-partner:54561
BRANCH=None
TEST=Manual on gru. Enable CHROMEOS_VBNV_EC, verify exception isn't
encountered on host command 0x17. Also verify call to
system_set_vbnvcontext followed by system_get_vbnvcontext results in
same data being read back.
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: I4df636b70c71a43a2dd6f584ee965135e90b4351
Reviewed-on: https://chromium-review.googlesource.com/354132
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
FUSE_CTRL_OVERRIDE overrides all rbox fuse values with the values in
RBOX_DEBUG not just the ones that are explicitly set. This change
removes the override from rbox.
BUG=chrome-os-partner:54238
BRANCH=none
TEST=on gru and kevin check that pressing 'c' registers on the EC.
Change-Id: I655e9ca96e52359a7d36e0d691f838c335df8cb8
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/353033
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-by: David Schneider <dnschneid@chromium.org>
loader/key_ladder.c depends on debug_printf(). Refactor
the printf function so that key_ladder.c need not depend
on main.c.
This change being made in preparation for a future
change which introduces a dependency between RW and
key_ladder.o
BRANCH=none
BUG=chrome-os-partner:43025,chrome-os-partner:47524
TEST=build succeeds
Change-Id: I5c9bf7bd6dd9f76ab6410e6e797973bdb072ec16
Signed-off-by: nagendra modadugu <ngm@google.com>
Reviewed-on: https://chromium-review.googlesource.com/351760
Commit-Ready: Nagendra Modadugu <ngm@google.com>
Tested-by: Nagendra Modadugu <ngm@google.com>
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
Default setting is at 48MHz.
For PLL frequency at 24MHz:
1. USB module can't work, it requires 48MHz to work.
2. SSPI clock frequency is divide by two.
Signed-off-by: Dino Li <dino.li@ite.com.tw>
BRANCH=none
BUG=none
TEST=1. uart, i2c, timer, and pd modules are function normally
at different PLL frequency settings.
2. use 'flashrom' utility to flash EC binary with different
PLL settings.
Change-Id: Iabce4726baff493a6136136af18732b58df45d7f
Reviewed-on: https://chromium-review.googlesource.com/347551
Commit-Ready: Dino Li <Dino.Li@ite.com.tw>
Tested-by: Dino Li <Dino.Li@ite.com.tw>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Since the pending bit of host access interrupt is set frequently if
PCH accesses KBC/PM_Channel/Shared Memory through LPC after entering
S0. It's better to add checking enable bit of MIWU of it in case huge
latency between gpio interrupt and serving its own ISR in INT11's ISR.
Modified sources:
1. gpio.c: Add checking enable bit of MIWU of host access in INT11 ISR.
BRANCH=none
BUG=chrome-os-partner:34346
TEST=make buildall -j; test nuvoton IC specific drivers
Change-Id: I1ae57173eb208fa78218bc01cfbc91f9a29c5c81
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/352362
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Add a certificate verifier, so that endorsement
certificates may be verified upon installation.
Doing so allows for catching certificate errors early.
BRANCH=none
BUG=chrome-os-partner:43025,chrome-os-partner:47524
TEST=all tests in test/tpm_test/tpmtest.py pass
Change-Id: I9339a6bc36e4d82ae875ce774e31848ae983fa1f
Signed-off-by: nagendra modadugu <ngm@google.com>
Reviewed-on: https://chromium-review.googlesource.com/351031
Commit-Ready: Nagendra Modadugu <ngm@google.com>
Tested-by: Nagendra Modadugu <ngm@google.com>
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
State that needs to survive re-flashing
of RO+RW is stored in the INFO bank. An
example of such state is manufacture secrets,
which need to survive reflashing from the
personalize firmware to the initial TPM2
firmware.
This change adds support for writing to
the writeable flash info bank.
BRANCH=none
BUG=chrome-os-partner:43025
TEST=manually verified info1 reads and writes
Signed-off-by: nagendra modadugu <ngm@google.com>
Change-Id: I9226e2161e036d1dacccbe55b67724b449983008
Reviewed-on: https://chromium-review.googlesource.com/351274
Commit-Ready: Nagendra Modadugu <ngm@google.com>
Tested-by: Nagendra Modadugu <ngm@google.com>
Reviewed-by: Marius Schilder <mschilder@chromium.org>
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
This commit includes changes required for
supporting a hardware based montgomery
modexp (r = a ^ e mod N).
The function bn_is_bit_set() was previously
static, and now added to internal.h, as this
function is used by the hardware implementation.
Add function declarations for new functions
related to the hardware implementation to
chip/g/dcrypto/internal.h
BRANCH=none
CQ-DEPEND=CL:*260618,CL:*260895
BUG=chrome-os-partner:43025,chrome-os-partner:47524
TEST=all tests in test/tpm_test/tpmtest.py pass
Change-Id: I5fe4a6692678b64f27659f42a08d200b6fe6f0cc
Signed-off-by: nagendra modadugu <ngm@google.com>
Reviewed-on: https://chromium-review.googlesource.com/347462
Commit-Ready: Nagendra Modadugu <ngm@google.com>
Tested-by: Nagendra Modadugu <ngm@google.com>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
The `i2cdetect` tool will scan certain slave addresses with a zero byte
read / write. Reply to such requests with the ACK status of the slave
device.
BUG=chrome-os-partner:53324
BRANCH=None
TEST=Verify `i2cdetect -y -a 9` on kevin yields the ACK status of each
slave address.
Change-Id: If080cc9f1b7dfefb0025fef448c5b177a2a50137
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/350102
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Mulin Chao <mlchao@nuvoton.com>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Mulin Chao <mlchao@nuvoton.com>
Instead of enabling the SOF calibration at usb_init(), enable it
only when the first SOF packet is seen following the usb_init(),
as suggested in the recommendations document linked from the bug
report.
Also fix the code to do the right thing. The original reference
code had errors.
BUG=chrome-os-partner:50800
BRANCH=none
TEST=make buildall; test on Cr50
After adding some instrumentation code, I see the SOF being
detected and the calibration started. It only happens once after
each usb_init() and only when the USB traffic begins.
Change-Id: Id2b9a41d90ce9cc9e467fb759463d69a57bb5540
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/350371
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
While in CCD, cr50 can be used to flash the AP and EC through USB. This
change adds an endpoint that can be used to read, erase, and write to
the AP and EC spi rom.
Currently CCD is not enabled on cr50, so usb_spi access has to be
enabled manually through the cr50 console.
BUG=chrome-os-partner:50701
BRANCH=none
TEST=manual
On EC console run 'flash_tristate true'
On cr50 console run 'usb_spi enable'
Use 'flashrom -p raiden_debug_spi:target=EC' and
'flashrom -p raiden_debug_spi:target=AP' to interact with
the AP and EC flash
CQ-DEPEND=CL:342144
Change-Id: I9c31dab252a8bfbc498eaf64ac5c2f53ec9dde30
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/342511
I2C is not necessarily _that_ slow, especially when using 1Mhz clock
speed, and, looking at traces from userspace, there are large gaps
(150us) between bytes (while the bytes themselves only take ~10us).
At 400kHz and higher bus speed, busy-loop for the duration of 2 bytes,
before sleeping (and yielding to other tasks) for 100us between each
attempt.
BRANCH=None
BUG=chrome-os-partner:50381
TEST=i2cget, look at Logic 16 traces: no gaps between address and bytes
Change-Id: If47f0f8e55be37002361800d35f71c945863d42d
Signed-off-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/346670
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Port SHA and P256 code to depend on third_party/cryptoc.
Remove config options CONFIG_SHA1, and CONFIG_SHA256 as
these are provided by third_party/cryptoc.
Also remove unused config options CONFIG_SHA384, CONFIG_SHA512.
Crypto functions prefixed by dcrypto_ (declared in internal.h ),
DCRYPTO_ (declared in dcrypto.h) are implemented under
chip/g/dcrypto, and otherwise are implemented under third_party/cryptoc.
BRANCH=none
BUG=chrome-os-partner:43025,chrome-os-partner:47524,chrome-os-partner:53782
TEST=all tests in test/tpm_test/tpmtest.py pass
Change-Id: If7da02849aba9703573559370af5fae721d594fc
Signed-off-by: nagendra modadugu <ngm@google.com>
Reviewed-on: https://chromium-review.googlesource.com/340853
Commit-Ready: Nagendra Modadugu <ngm@google.com>
Tested-by: Nagendra Modadugu <ngm@google.com>
Reviewed-by: Nagendra Modadugu <ngm@google.com>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
This could be a pain, but we do no want to keep any state when cr50
firmware is upgraded.
BRANCH=none
BUG=chrome-os-partner:44745, chrome-os-partner:51977
TEST=not much yet, will be tested when debugging cr50 functionality
Change-Id: Ic26d3f9f20c6edb77c76c941d04c31948f02be20
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/348292
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
This change is motivated by an internal use case.
BRANCH=none
BUG=none
TEST=make buildall -j
Successfully used the exported functions on Cr50.
Change-Id: I5a54b4ea407866c7d7a4bd075d7773ac81e00930
Signed-off-by: Nadim Taha <ntaha@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/348215
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
This fixes two race conditions that lead to a watchdog timeout:
1) ticks_to_usecs()
common/timer.c:process_timers() wraps its body in a
"while (next.val <= get_time().val)" loop meant to ensure that
it never returns after having scheduled an expired timer
(to address potential __hw_clock_event_set() overflows/underflows).
However get_time() through __hw_clock_source_read() calls ticks_to_usecs()
which "expands" the hw_rollover_count by a truncated clock_div_factor which
causes that loop condition to observe a "current time" that is up to ~15us
in the past (assuming a 24MHz clock). This race arises frequently with
workloads that repeatedly sleep for a short duration.
2) __hw_clock_event_irq()
The HW timer rollover interrupt was configured to be higher priority than
the event timer interrupt (i.e. it can preempt it) which is problematic if:
- There is a scheduled deadline soon after a "clksrc_high / .le.hi" boundary
- An earlier (before the clksrc_high rollover) event timer interrupt kicks in
- After the event timer interrupt handler gets to "now = get_time()"
in common/timer.c:process_timers() the rollover interrupt triggers
incrementing clksrc_high (i.e. the overflow case)
- The rollover interrupt handler arms the event timer to trigger at
that deadline (mentioned in the first bullet) and returns
- The original event timer interrupt handler resumes execution but finds
no events to schedule since the "timer_deadline[tskid].le.hi == now.le.hi"
clause won't evaluate to true. It will then call __hw_clock_event_clear()
before returning causing a watchdog timeout
This commit also contains a fix to properly initialize the HW timer
after a sysjump.
BRANCH=none
BUG=none
TEST=Reproduced both races and successfully tested the fix. The workload I was
using to reproduce (typically within an hour) has been running smoothly
for the past 24 hours.
Change-Id: Ic0b0958e66e701b52481fcfe506745ca1c892dd1
Signed-off-by: Nadim Taha <ntaha@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/347465
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
When the AP or EC is off, the RX line is low. Holding the UART RX line
low causes an interrupt storm. This change disables the UART TX and RX
on the peripheral when the device is powered off so the interrupts wont
be triggered.
BUG=chrome-os-partner:53514,b:28885578
BRANCH=none
TEST=run taskinfo on cr50 and make sure the IRQ count for 181 is a
reasonable number.
Change-Id: I42c779253860a2b1dd27ab41fb7097c887cc23ff
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/347355
Use the power and servo connection states to enable and disable the
EC and AP UART output. Contention between the cr50 and servo
can prevent either uart from working, and possibly damage kevin or
servo. If both UARTs are enabled, then cr50 cant know if servo is
connected, so it is best if the UARTs are disabled before connecting
servo.
If servo is connected or if a device is not powered on then the UART
output wont be enabled. The two UARTs are enabled separately and one can
be enabled without the other. Any disabled UART will be monitored for a
servo connection. If servo is detected, then all UARTs will be disabled.
BUG=chrome-os-partner:52056,chrome-os-partner:52322
BRANCH=none
TEST=manual
Power on the EC only. Check only the EC UART is enabled.
Without disabling the uarts power on the AP and verify both are
now enabled.
Turn of the AP. run 'uart enable. Verify only the EC UART is
enabled. Then attach servo and check that the AP and EC UART
are disabled.
Change-Id: Ife27c9360e91b07f86ff8bfcec7f4fd423c31d25
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/342828
There are a couple of issues that cr50 has when it cannot know the state
of servo, the EC, and the AP. This change adds support so we can detect
when the AP or EC has been powered on and when servo has been connected.
It uses the UART RX signals to monitor the power state of the AP and EC.
The TX signals are used to monitor the state of servo.
BUG=chrome-os-partner:52056,chrome-os-partner:52322
BRANCH=none
TEST=verify device states are correct when the AP and EC are powered on
or off and when Servo is attached or detached
Change-Id: Id0a2281b65cb367ecc8d0ca2f9a576672318a5fb
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/344019
Only way to set alarm previously was through
rtcalarm command on EC console. Implemented
interface through ectool so that the AP can set
it as well.
BUG=chrome-os-partner:52218
BRANCH=None
TEST=from AP console, run ectool rtcalarm <sec>
Should see [event set 0x02000000] from EC
console in approximately <sec> seconds.
Change-Id: I3202b826cb994dbca456b8b9c22bbca4dbe2766a
Signed-off-by: Shelley Chen <shchen@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/347493
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Full implementation of NvMem read, write, and commit functions.
Includes partition definitions, shared memory allocation, and
initialization function.
Includes a set of unit tests located in ec/test/nvmem.c which
verify functionality.
This module is required by Cr50, however this CL does not
include any Cr50 specific code.
BUG=chrome-os-partner:44745
BRANCH=none
TEST=manual
make runtests TEST_LIST_HOST=nvmem and verify that all tests pass
Change-Id: I515b094f2179dbcb75dd11ab5b14434caad37edd
Signed-off-by: Scott <scollyer@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/345632
Commit-Ready: Scott Collyer <scollyer@chromium.org>
Tested-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
This change provides a console command for setting,
and loading a usb serial number from flash. This
feature adds CONFIG_USB_SERIALNO, and currently only
has a useful implementation when PSTATE is present.
BUG=chromium:571477
TEST=serialno set abcdef; serialno load; reboot
BRANCH=none
Change-Id: I3b24cfa2d52d54118bc3fd54b276e3d95412d245
Signed-off-by: Nick Sanders <nsanders@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/337359
Reviewed-by: Randall Spangler <rspangler@chromium.org>
The console adc command prints adc values in the
order they appear in hardware, however they are lableled
in the order they are enumerated in board.h, which is not
necessarily the same.
This prints the correct name and value pairs, and removes
the adc_read_all_channels function which is not otherwise
used.
BUG=chromium:571476
BRANCH=None
TEST="adc" command associates correct values with names now.
Change-Id: I688641953d20082224b4120eaefe0d634ad4c74c
Signed-off-by: Nick Sanders <nsanders@google.com>
Reviewed-on: https://chromium-review.googlesource.com/340892
Commit-Ready: Nick Sanders <nsanders@chromium.org>
Tested-by: Nick Sanders <nsanders@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
Before the change was made, the EC clock will be changed to 16MHz
when wake up from sleep mode, but we need it to keep at 8MHz.
This issue only occurs when EC sleep mode is implemented.
Signed-off-by: Dino Li <dino.li@ite.com.tw>
BRANCH=none
BUG=none
TEST=The 'IT83XX_ECPM_SCDCR3' register keeps default setting.
Change-Id: I206c5e657aba296684d60d6b30ed4071798dd96a
Reviewed-on: https://chromium-review.googlesource.com/345737
Commit-Ready: Dino Li <Dino.Li@ite.com.tw>
Tested-by: Dino Li <Dino.Li@ite.com.tw>
Reviewed-by: Randall Spangler <rspangler@google.com>
The 144-pins package IC(IT8320) supports these two GPIO groups.
Signed-off-by: Dino Li <dino.li@ite.com.tw>
BRANCH=none
BUG=none
TEST=1. Declare GPIO groups K/L in gpio.inc and using console commands
'gpioget'/'gpioset' to read/set GPIOs.
2. Choose four GPIO pins(GPIOK.0/1 and GPIOL.0/1)
and test interrupt functionally.
Change-Id: Ia618c314eeca1d061ffe172da762865f5df9b5c6
Reviewed-on: https://chromium-review.googlesource.com/345776
Commit-Ready: Dino Li <Dino.Li@ite.com.tw>
Tested-by: Dino Li <Dino.Li@ite.com.tw>
Reviewed-by: Randall Spangler <rspangler@google.com>
Enabled CONFIG_CMD_RTC_ALARM. EC_HOST_EVENT_RTC
is enabled when the rtc_alarm goes off,
alerting the AP to transition from S3->S0.
BUG=chrome-os-partner:52218
BRANCH=None
TEST=rtc_alarm <num> and see event set in ec console
after <num> seconds. Also, check if new bit set
through hostevent command in ec before/after
rtc_alarm goes off.
Change-Id: I53b1705ce0925000f35b9f80752035d198db3310
Signed-off-by: Shelley Chen <shchen@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/345474
Reviewed-by: Shawn N <shawnn@chromium.org>
