Add structures to keep track of which interrupts are associated with which pin.
There are IN[] events, and one PORT event. The IN[] events have an array.
The PORT event can be used for multiple pins at once.
BUG=chrome-os-partner:34477
BRANCH=none
TEST=Configured pins as IN[] events and PORT events, and saw console output.
Signed-off-by: Myles Watson <mylesgw@chromium.org>
Change-Id: I129a6586dca4d5eb141c86fd92fbfbb70080bc2a
Reviewed-on: https://chromium-review.googlesource.com/234392
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Tested-by: Myles Watson <mylesgw@chromium.org>
Commit-Queue: Myles Watson <mylesgw@chromium.org>
Updated to use parameters for GPIOTE_OUT, GPIOTE_IN, and GPIOTE_CONFIG
Updated with NRF51_GPIOTE_IN_COUNT to remove the magic number.
BUG=chrome-os-partner:34477
BRANCH=none
TEST=Configured IN[] events and PORT events and checked that they triggered
events and wrote to the console.
Signed-off-by: Myles Watson <mylesgw@chromium.org>
Change-Id: I2021ecbee67c39571f277c97082378dce4de024f
Reviewed-on: https://chromium-review.googlesource.com/234289
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Tested-by: Myles Watson <mylesgw@chromium.org>
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Commit-Queue: Myles Watson <mylesgw@chromium.org>
Add support for alternate functions for nrf51.
Add more register definitions for the nrf51.
Use assertions for conditions that should never happen.
Use BUILD_ASSERT to keep the sources in sync.
Add three more GPIOs to hadoken.
BQ27621_GPOUT - Configurable output from the fuel gauge.
LID_PRESENT_L - The input for the hall sensor.
IND_CHRG_DISABLE - The output to control inductive charging.
BUG=chrome-os-partner:34477
BRANCH=none
TEST=Used gpioget and magnets for LID_PRESENT_L
Used fuel gauge console commands to trigger BQ27621_GPOUT
Tested the assertions with gdb
Signed-off-by: Myles Watson <mylesgw@chromium.org>
Change-Id: I508f79ae45127104fa14f9f75fbf545f226387e4
Reviewed-on: https://chromium-review.googlesource.com/234286
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Tested-by: Myles Watson <mylesgw@chromium.org>
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Commit-Queue: Myles Watson <mylesgw@chromium.org>
define CONFIG_CMD_BATDEBUG to enable console commands.
If the battery is larger than 6Ah or smaller than 150mAh, scale the parameters
transparently to the user using macros.
BUG=chrome-os-partner:34477
BRANCH=none
TEST=Custom console commands for the fuel gauge
I also used a Logic16 from Saleae and the fuel gauge on hadoken.
Signed-off-by: Myles Watson <mylesgw@chromium.org>
Change-Id: I959d51c3188336e4ad0983528ad7e53a2955a764
Reviewed-on: https://chromium-review.googlesource.com/234285
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Tested-by: Myles Watson <mylesgw@chromium.org>
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Commit-Queue: Myles Watson <mylesgw@chromium.org>
Add absolute threshold on delta_z_inner for tap for battery to guarantee
that we have at least some minimum absolute change in z that has started
the tap for battery.
This change makes it such that if the accel readings are really steady
for a while, then a sudden noisy signal doesn't trigger tap for battery.
BUG=chrome-os-partner:34592
BRANCH=samus
TEST=use tapinfo on to observe tap values and do a double tap of varying
intensities. note that it should be just a little less sensitive to weak
taps.
Change-Id: I95367bc7f99b888e15e9ac3a2bc8c9cca32d30d6
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/237666
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Double the output data rate setting for accels for tap
for battery because with the lsm6ds0 sensor, the current
ODR does not guarantee that we get fresh data every time
we do a read.
BUG=chrome-os-partner:34592
BRANCH=samus
TEST=load onto samus, go to G3, use tapinfo on to see
ODR set to 476000Hz. add printf to lsm6ds0 to print when
data is not ready, and see that without this change, the
printf is hit once a minute or so, and with this change,
the printf is never hit, meaning new data is always ready.
Change-Id: Ib09cba0d70642f59df8a35b5b6bb4fd7b9a4fa3d
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/237665
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Fix accelerometer bug in which, if there is no new data from
the lsm6ds0 accel, it will use the old ajusted xyz instead of
the old raw xyz.
BUG=chrome-os-partner:34952
BRANCH=samus
TEST=add printf to case where it uses old data and sample faster
then ODR to read wrong data.
Change-Id: If0a6bbdec71d84567eae107aca6f1d0ab754919a
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/237664
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
With the type-c connector, it's common for VBUS to make contact before
D+/D-, which can lead to charger misdetection. To work around this, add
a 200ms delay and trigger re-detection when a charger is inserted. This
should fix most misdetects due to unintentional slow plug (though it's
still possible to misdetect if insertion is deliberately very slow).
BUG=chrome-os-partner:34584
TEST=Manual on Samus. Plug in Apple charger 20 times, verify that it is
always detected correctly. Deliberately plug in slowly, verify it is
detected as 500mA SDP port. Repeat tests with various other CDP / SDP
ports to verify detection never over-currents and always indicates a
charger is plugged (or not plugged) correctly.
BRANCH=Samus
Change-Id: I8a776f516d8e7f0cedcb9d8579239eba641cab09
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/237241
Reviewed-by: Alec Berg <alecaberg@chromium.org>
if power good is lost and the power button still press, we need cancel the long
press timer, otherwise EC will crash.
BUG=chrome-os-partner:34816
TEST=press power button during coreboot, and it can shutdown normally
BRANCH=None
Change-Id: Ia27c83137451abacce9d544741bbbe5787983215
Signed-off-by: Chris Zhong <zyw@rock-chips.com>
Reviewed-on: https://chromium-review.googlesource.com/237294
Reviewed-by: Jiazi Yang <Tomato_Yang@asus.com>
Reviewed-by: Alexandru Stan <amstan@chromium.org>
Commit-Queue: Eddie Cai <eddie.cai8848@gmail.com>
For factory testing, we need a way to simulate unplugging type-C cable.
To do so, we disable VBUS output and pull-up/pull-down on CC lines on
Plankton, so that the CC lines become floating.
BRANCH=None
BUG=chrome-os-partner:32163
TEST=Connect Plankton to Ryu. Try 'fake_disconnect' as SRC/SNK.
Change-Id: I73a7355e078b6aed4b7d281d480e0aedbc8c2db0
Signed-off-by: Vic Yang <victoryang@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/229662
Reviewed-by: Pin-chih Lin <johnylin@chromium.org>
Tested-by: Pin-chih Lin <johnylin@chromium.org>
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Ports should have source roles by default, and should go back to being
sources once we stop charging from them.
BUG=chrome-os-partner:31195
TEST=Manual on Samus. Connect Samus to dual-role port. Set override
port, verify that Samus charges. Attach dedicated charger, verify that
the dual-role port becomes a charge source again. Also pass unit tests.
BRANCH=Samus
Change-Id: Icf153117229cbf0f71d4bdeb888f73299acd5eeb
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/237452
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Add initial serial driver for mdcp2850 dp->hdmi converter. Driver
implements 'get information' (cmd:0x40) to provide rudimentary method
to test mcdp for functionality and assert GPIO if successful.
Future CLs may expose more serial functionality if necessary.
Signed-off-by: Todd Broch <tbroch@chromium.org>
BRANCH=samus
BUG=chrome-os-partner:34122
TEST=manual, when compiles with #define MCDP_DEBUG see successful
serial communication and result from get info.
buf:[00]0x04 [01]0x40 [02]0x00 [03]0xbc
...
buf:[00]0x0f [01]0x40 [02]0x00 [03]0x0e
[04]0x00 [05]0x01 [06]0x01 [07]0x00
[08]0x00 [09]0x00 [10]0x00 [11]0x00
[12]0x00 [13]0x00
family:000e chipid:0001 irom:1.0.0 fw:0.0.0
Change-Id: I35f9d9b0437633d1bd6a6c9fa14413bedb12f5c2
Reviewed-on: https://chromium-review.googlesource.com/235930
Trybot-Ready: Todd Broch <tbroch@chromium.org>
Tested-by: Todd Broch <tbroch@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Commit-Queue: Todd Broch <tbroch@chromium.org>
Set charge state machine voltage to just above the battery voltage
when AC is disconnected. Also send new current before sending new
voltage to charger when there is a change. These changes reduce
input current spikes caused by current inrush into the battery and
thereby decrease chance of overcurrenting power supply on connect.
BUG=chrome-os-partner:33862
BRANCH=samus
TEST=load onto samus instrumented with input current probe. when
AC is attached note that initial current spike is much lower with
this change.
Change-Id: I7760cd2b709c6b3536cf2a9449bb1f46800ce10a
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/237245
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Add internal pull-up to EC_IN_RW to match changes made in DVT.
Doesn't affect earlier boards because a hardware bug prevented
us from reading the correct state anyway.
BUG=none
BRANCH=samus
TEST=make -j buildall
Test on re-worked samus board with DVT changes. Tested PD MCU
can read the correct state of the gpio.
Change-Id: I27952022cfff2d1f7adcb93d4df47d63f1fd5470
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/237305
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Add EC2I control module for emulation board.
The EC2I bridge enables the EC to access the host controlled
module registers (e.g., host configuration module(PNPCFG) and SWUC)
Signed-off-by: Dino Li <dino.li@ite.com.tw>
BRANCH=none
BUG=none
TEST=EC2I read: Read a logical device page, the results are correctly.
EC2I write: Initialize PNPCFG success.
Change-Id: I900450d4a8c49182c438b69b5e738c12dc437fe4
Reviewed-on: https://chromium-review.googlesource.com/230410
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Commit-Queue: Dino Li <dino.li@ite.com.tw>
Tested-by: Dino Li <dino.li@ite.com.tw>
This conversion is needed in files outside of system.c, so add a new
function.
BUG=chrome-os-partner:34599
TEST=Manual on samus_pd. Run "pd 0 info" and verify "Image RW" is
printed.
BRANCH=Samus
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: Ia905ba9cf985f3714fa75c81670b8a39e9608f3d
Reviewed-on: https://chromium-review.googlesource.com/236980
Tested-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Commit-Queue: Shawn Nematbakhsh <shawnn@chromium.org>
Previously, handle_vdm_requests could dispatch another VDM message
via send_validate_message prior to main task returning to vdm state machine
(pd_vdm_send_state_machine). While it hasn't been problematic to-date it would
make honoring VDM specific timers or PDO priority difficult.
CL changes behavior so that if VDM being handled requires another VDM to be sent
its copied to the one entry queue (queue_vdm) where it will be
serviced upon VDM state machine entry later.
With this simplification, CL expands interlocks between PDO & VDO.
VDOs are only sent when source/sink is in the ready state & no
incoming packet is on the CC line. PDOs aren't sent when the VDM
state machine is busy.
CL also simplifies VDM console output to come only from request handler which
could save a few bytes.
Signed-off-by: Todd Broch <tbroch@chromium.org>
BRANCH=samus
BUG=chrome-os-partner:30645
TEST=manual,
1. dingdong/hoho still enter mode.
2. Can still update fw.
Change-Id: I2fe8643a6975205b2d0f510f4f1baf2d74c1e190
Reviewed-on: https://chromium-review.googlesource.com/235680
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Commit-Queue: Todd Broch <tbroch@chromium.org>
Tested-by: Todd Broch <tbroch@chromium.org>
The current power request function avoids redundant requests by
checking if we have previously requested vSafe5V or the max we
can request. But, if the max voltage that we can request changes,
then sending another max request is not redundant. This CL modifies
the request function to check for redundant requests by checking
the max voltage that can be requested, so if the max voltage
changes, then a new request is allowed.
BUG=none
BRANCH=samus
TEST=on pd console:
pd 0 dev 5
pd 0 dev 12
pd 0 dev 20
all send new request immediately.
Change-Id: Ifcdcc3eac9e566714f6dc609e46bbb0b94426499
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/236882
Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change the ENTERING_RW gpio name to match other boards so that common/system.c
sets the gpio automatically when jumping to RW.
BUG=none
BRANCH=samus
TEST=make buildall
Change-Id: I8290462a73d99dad0a9f5b8de7ea1c0edb56876e
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/236964
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
This addition allows the AP to query whether the PD device is currently
running from RO or RW FW.
BUG=chrome-os-partner:34599
TEST=Manual on Samus. Run 'ectool --name cros_pd infopddev 0' and verify
that correct RO/RW status of Zinger is printed. Verify that the output
matches the index printed by "pd 1 hash" on samus_pd console.
BRANCH=Samus
Change-Id: I4266cae931f5c7855ca0531717c4a18b138b2d62
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/236771
Reviewed-by: Alec Berg <alecaberg@chromium.org>
In order to reduce flash size on some constrained boards this CL
modifies the GPIO macro in gpio_list.h to change the name field from
that listed 'name' to the concat of 'port' and 'pin'.
Signed-off-by: Todd Broch <tbroch@chromium.org>
BRANCH=samus
BUG=chrome-os-partner:34489
TEST=manual
1. build with and without CONFIG_COMMON_GPIO_SHORTNAMES
See >500 bytes savings with config option
2. See reduced names for gpioget
Change-Id: I6ed2c1d16aae5923fdf47a1b2dbb2362598a19e0
Reviewed-on: https://chromium-review.googlesource.com/236766
Trybot-Ready: Todd Broch <tbroch@chromium.org>
Tested-by: Todd Broch <tbroch@chromium.org>
Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
Commit-Queue: Todd Broch <tbroch@chromium.org>
According to specification, a DCP port is only required to provide 500mA
@ 4.75V, though actual supply limit can vary upward significantly. Set
the current limit on DCP ports to 500mA to reflect this reality.
BUG=chrome-os-partner:32003
TEST=None
BRANCH=Samus
Change-Id: I46e25b44baaa41ddf173880e52d7485d952ebf23
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/236772
Reviewed-by: Alec Berg <alecaberg@chromium.org>
STM32 seems to actually measure the rising and falling time of the I2C clock, so
if one uses a really small resistor the timing will go faster than with a bigger
resistor.
This commit makes it so the I2C frequency is limited to max 100kHz (respecting
the spec) no matter what size resistor (essentially we assume 0 rise and fall
times). While this will make stuff slower on boards with big resistors (where
they might have been under 100kHz anyway) this is the best compromise (since the
spec does not specify min frequency) without getting config defines for the
fall/rise times.
The TSCLH of some boards would be too short with the recommended timing
settings from spec, so increases the TSCLH would be better for everyone.
This patch does not touch the higher frequencies since the rise and fall times
do contribute a lot more to clocks, if the same method was used for those
frequencies, the speeds would have to be a lot slower.
BUG=chrome-os-partner:34375
BRANCH=None
TEST=on any EC, note how frequency does not go above 100kHz
TEST=As per tSCL = tSYNC1 + tSYNC2 + { [(SCLH+1) + (SCLL+1)] x
(PRESC+1) x tI2CCLK } from datasheet
Change-Id: Ibbeecac7f3da1b22d2ba3bca29ee3c17bfe997f5
Signed-off-by: Chris Zhong <zyw@rock-chips.com>
Signed-off-by: Alexandru M Stan <amstan@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/234077
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Fix bug causing tap for battery not to work in G3 when AC
is attached. Problem was that the lightbar was being held
in reset and would not light up.
BUG=chrome-os-partner:34722
BRANCH=samus
TEST=tested on samus with AC attached and unattached in S3
and in G3, tap for battery lights up the lightbar. Also
verified that plugging and unpluggin AC in S3 and G3 causes
lightbar to light up.
Change-Id: I0fbd989399d372d287467200512bbdf2551884d3
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/236560
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
We actually need to care about x, the PRI register is actually a list of
registers (and we have code that uses some of the later ones).
BUG=None, discovered while chrome-os-partner:33451
TEST=Change priorities of irqs(like UART over GPIO(spi_event)), note how they
actually work and override each other as told
BRANCH=None
Change-Id: I9f5bf7ba9d4211f782ff260fbce17deb7c53a31f
Signed-off-by: Alexandru M Stan <amstan@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/236087
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
UART with no DMA is likely to drop RX characters when system is busy. This is
because the UART interrupt is lower priority than the spi_event GPIO interrupt.
We can work around this by enabling the DMA, so no UART interrupts are required
while recieving, since everything will happen in DMA.
This replaces the other patch(CL 236089) which suggested changing UART IRQ
priority.
BUG=chrome-os-partner:33451
TEST=get firmware to poll the EC for keyboard presses, type really fast on the
keyboard, note how no character is lost anymore
TEST=faft dev mode test now passes, faft is able to type "kbpress $(insert args
for Ctrl+D) 1" correctly without missing characters because firmware is loading
the EC with keyboard polls
TEST=While '+'s are scrolling on the EC terminal paste something big like this:
"kbpress 1 1 1
kbpress 1 1 0
123456789012345678901234567890
". Both kbpresses should be interpreted/executed properly(no "kbprss") and there
should be no missing digits in the echo back.
BRANCH=None
Change-Id: I01d4eaa23f10f07083875846ea48c34da2e2f6ce
Signed-off-by: Alexandru M Stan <amstan@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/236365
Reviewed-by: Randall Spangler <rspangler@chromium.org>
When the EC is busy enough to start missing RX characters an ORECF might come
(Overrun error), we never check for this bit, so that means the interrupt
handler will be called in a loop because it never clears that bit.
This disables the overrun detection feature.
BUG=chrome-os-partner:33451
TEST=get firmware to poll the EC for keyboard presses, type really fast on the
keyboard, note how system does not watchdog reset anymore but loses the
occasional character instead.
BRANCH=None
Change-Id: I711483768e4ba80aaeb4a324c7dee790b3a23682
Signed-off-by: Alexandru M Stan <amstan@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/236088
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Modify board_set_active_charge_port to return status indicating whether
the selected charge port was rejected. If rejected, zero out its
available charge and attempt to select a different charge port.
Also, reduce the length of related console prints.
BUG=chrome-os-partner:34677
TEST=Manual on Samus. Plug C-to-Arec into port 1, verify that charge
manager does not select port 1 as active and charging icon is not seen
in OS.
BRANCH=Samus.
Change-Id: I56e3337f90c04b93ef7cc9873af6ee0f4b1ffc7d
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/236361
Reviewed-by: Alec Berg <alecaberg@chromium.org>
According the STM32L RM, when writing to RCC_CFGR to change HSI or MSI
clock source, SWS bits of RCC_CFGR register have to be checked if the
new clock source is taken into account. Also, when writing ACC64 bit and
LATENCY bit to FLASH_ACR register, those bits have to be checked too.
Also changed in this CL is to disable MSI if HSI is enabled, and disable
HSI if MSI is enabled.
BUG=chrome-os-partner:32936
BRANCH=none
TEST=passed suspend_stress_test on big, blaze and nyan
Change-Id: I3ec660d149ecdec3ca3097239612bf2c542d0548
Signed-off-by: Yen Lin <yelin@nvidia.com>
Reviewed-on: https://chromium-review.googlesource.com/234490
Reviewed-by: Kary Jin <karyj@nvidia.com>
Tested-by: Kary Jin <karyj@nvidia.com>
Reviewed-by: Andrew Bresticker <abrestic@chromium.org>
(cherry picked from commit 400d9dca8c41f74cf0c2587e881707b80bb17d3d)
Reviewed-on: https://chromium-review.googlesource.com/236050
Allow CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON to be defined at the board
level to be the minimum battery percentage required for power-on. If the
battery level is below the threshold, or if the battery is missing,
power button presses will be ignored.
BUG=chrome-os-partner:31127
TEST=Manual on Samus with subsequent commit. Verify that AP continues
to boot normally when charge level exceeds
CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON. Verify that power button
presses are ignored when the charge level is below the threshold, and
we return to G3.
BRANCH=Samus
Change-Id: I0ff3f7ddabf38080332470e172c8b2e307bf1655
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/236021
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Added check for collision just before transmitting on CC line.
To check for collision, RX monitoring is left on all the time
(except when in the act of receiving or transmitting, or in
between receiving and sending a goodCRC), and a
simple check for RX transmission started is used to see if the
CC line is idle or not.
RX monitoring is also changed to only trigger on 3 edges within
20us, as per the PD spec.
When a collision is detected by seeing that CC is not idle, the
transmitting packet is dropped.
BUG=chrome-os-partner:30135
BRANCH=samus
TEST=load onto samus and zinger. make sure we negotiate and make
sure custom VDMs succeed. enabled pings and made sure we stay
alive with pings for a few min.
Also added code to pd_rx_handler to toggle a test point on EVT
board to verify the timing of when we get RX interrupts:
Change-Id: I22d172163319437d3d901e019eda79d4d592f6b8
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/226118
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Cortex-m0 we supports 2 bit priorities for the NVIC, yet we clear with 0x7 (3
bits). Change so we now clear with 0x3
Also limited priority to the max available (so we don't set extra bits we don't
want or modulus the priority, otherwise setting priority 8 will actual give you
priority 0) in both cortex-m and cortex-m0.
BUG=None, discovered while looking at the code
TEST=Should be no functional change, NVIC priorities should still work the same.
BRANCH=None
Change-Id: I31ba041449cae96983753b297e2631c310a406c4
Signed-off-by: Alexandru M Stan <amstan@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/236086
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Add a rate limiter to host commands so that a host that is continuously
sending host commands doesn't watchdog the EC.
BUG=chrome-os-partner:33905
BRANCH=samus
TEST=loaded onto samus and tested remote update of zinger 10 times.
also tested EC + PD software sync.
Change-Id: Ia024179c46b2180ee97ea1902de343306142311c
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/235530
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
In order to reduce flash size on some constrained boards this CL
modifies the GPIO macro in gpio_list.h to change the name field from
that listed 'name' to the concat of 'port' and 'pin'.
Signed-off-by: Todd Broch <tbroch@chromium.org>
BRANCH=samus
BUG=chrome-os-partner:34489
TEST=manual
1. build with and without CONFIG_COMMON_GPIO_SHORTNAMES
See 897 bytes savings with config option
2. See reduced names for gpioget
> gpioget
0 E6
0 F2
1 B0
Change-Id: Ife1e1e2bcfa620ba87fe6c1ce2b47fe258c46514
Reviewed-on: https://chromium-review.googlesource.com/234587
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Commit-Queue: Todd Broch <tbroch@chromium.org>
Tested-by: Todd Broch <tbroch@chromium.org>
Change backboosting workaround into a new extpower task. This
new task runs exactly what used to be run in a deferred function,
but at higher priority than charger task, which means that i2c
transactions from this new task will occur before charger task
i2c transactions.
This fixes the EC watchdog when writing PD device firmware
because the hooks task is no longer blocked on trying to grab
the i2c mutex for talking to BQ.
BUG=chrome-os-partner:33905
BRANCH=samus
TEST=loaded onto samus and tested remote update of zinger 10 times.
Change-Id: I01d259857aefc6bf456ab217bf46536237bc4008
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/235862
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
